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Chethan QC Interview Questions

The document consists of a series of technical questions related to project design, floorplanning, power planning, and routing in VLSI design. It covers various aspects such as macro placement, channel length decisions, handling of IR drop, and timing checks during placement. Additionally, it addresses concepts like clock tree synthesis, crosstalk, and the importance of cell density and padding in design optimization.

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swathigadige0362
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20 views1 page

Chethan QC Interview Questions

The document consists of a series of technical questions related to project design, floorplanning, power planning, and routing in VLSI design. It covers various aspects such as macro placement, channel length decisions, handling of IR drop, and timing checks during placement. Additionally, it addresses concepts like clock tree synthesis, crosstalk, and the importance of cell density and padding in design optimization.

Uploaded by

swathigadige0362
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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1. Tell me about yourselfl?

2. Tell me about your project?


3. What complexity you faced in your project?
4. How many macros you had in your design and how you placed those?
5. How you did the floorplan?
6. How much utilization you had and which 'nm' you worked?
7. If you have '150' macros and '2.5M' instances how will you handle?
8. How will you decide the channel lenght?
9. Why VDD and VSS has to pass in between the macro channel?
10. If i don't want VDD and VSS to pass in b/w the channel then what will happen?
11. Why we need to apply the blockage in between the macros?
12. If instances placed in the place of macro channel what will happen?
13. After placing the macros what you will do?
14. How you do the power plan and why we need to do the power plan?
15. Have you placed I/O pads?
16. How you place the pins and what is the criteria?
17. Why power ring metal width is more and how they decide the width of that metal?
18. How they decide number power stripes and what basis?
19. Why IR Drop will come?
20. How you decide the quality of floorplan and power plan?
21. In placement, what you did and what complexity you faced?
22. What you will do to fix the congestion?
23. What are the reasons to get cell density and pin density and how you will fix
that?
24. How partial blockage will help? is there any other method to fix it?
25. What is cell padding and module padding?
26. If you apply the module padding, how it will effect on area?
27. What timings will you check in placement?
28. Why only setup? why don't you check the hold?
29. How you will optimize the fanout?
30. What is HFNS and how it will help?
31. If my utilization is 65% at floorplan and when it comes to placement it is 75%,
will you accept that?
32. Why you don't accept that utilization?
33. What is the setup and hold time of the flip flop?
34. In librarty, how they characterised the setup and hold time of the flip flop?
35. What are the goals of CTS?
36. What you did in CTS stage?
37. What are the types of clock tree?
38. What is H-tree and how it will build and what is the disadvantages of that?
39. Suppose i need to minimize the skew, what you will do for that?
40. How you fix the latency in your design?
41. If your target latency is '1ns' and your getting '1.5ns', how will you acheive
that latency?
42. What is NDR and why we need that?
43. Why cross talk will come?
44. Is it possible that your clock net can became a victim?
45. If your clock net is victim and your getting a positive crosstalk, will it help
for setup or hold?
46. What you did in routing stage and have you fixed any violations?
47. What is the reason for shorts and how you fixed it?
48. He gave a design and he said i have selected one instance, i need the fanin and
fanout of that instance by usign dbget command can you get those.
49. What are physical cells and in which stage you are going to place?

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