Computer Organization and Architecture ( Assignment -1 )

1-Mark Questions

1. What is the purpose of a compiler?

Answer: It translates high-level language code into machine code.
Enhanced Note: Compilers optimize code and handle complex structures like
loops and functions.
2. What is the von Neumann bottleneck?
Answer: The limitation caused by sharing a single bus for instruction and data
access.
Enhanced Note: This creates a bottleneck as the CPU must alternate between
fetching instructions and data.
3. What is immediate addressing mode?
Answer: The operand is a literal value embedded in the instruction.
Enhanced Note: Example: MOV R1, #10 moves the value 10 directly to register R1.
4. What is the role of the Arithmetic Logic Unit (ALU)?
Answer: It performs arithmetic (e.g., addition) and logical (e.g., AND) operations.
Enhanced Note: The ALU is the computational core of the CPU.
5. Define addressing mode.
Answer: The method used to specify how operands are accessed in an instruction.
Enhanced Note: It determines whether the operand is in a register, memory, or
instruction itself.
6. What is direct addressing mode?
Answer: The operand is the memory address specified in the instruction.
Enhanced Note: Example: LOAD R1, [1000] loads data from memory address 1000
into R1.
7. What does the fetch phase do in the CPU cycle?
Answer: It retrieves the next instruction from memory using the Program Counter.
Enhanced Note: The instruction is placed in the Instruction Register for further
processing.
8. What is a register?
Answer: A small, high-speed storage location within the CPU for temporary data.
Enhanced Note: Registers operate at CPU speed, unlike slower main memory.
9. What is the role of the Program Counter (PC)?
Answer: It holds the memory address of the next instruction to be fetched.
Enhanced Note: The PC is critical for sequential instruction execution and is
updated after each fetch.
10. Name one role of the operating system.
Answer: It manages processes, memory, or I/O devices.
Enhanced Note: For example, it schedules CPU time for processes or allocates
memory.
11. What is the Accumulator register used for?
Answer: It stores intermediate results of computations.
Enhanced Note: Common in single-accumulator architectures for arithmetic
operations.
12. What is a stored program computer?
Answer: A computer that stores both program instructions and data in the same
memory, following the von Neumann architecture.
Enhanced Note: This allows programs to be modified as data, enabling flexibility in
computation.
13. What is the Instruction Register (IR)?
Answer: It holds the current instruction being decoded or executed.
Enhanced Note: The IR feeds the instruction to the control unit for decoding.
14. What is an operand?
Answer: The data or memory address on which an instruction operates.
Enhanced Note: Operands can be registers, memory locations, or immediate
values.
15. What is the function of the Control Unit (CU)?
Answer: It directs CPU operations, coordinating the fetch-decode-execute cycle.
Enhanced Note: The CU generates control signals to manage data flow between
memory, ALU, and registers.
16. Name one type of instruction in an instruction set.
Answer: Arithmetic, logical, data transfer, or control flow instruction.
Enhanced Note: Example: ADD (arithmetic), JMP (control flow).
17. What is the purpose of the decode phase?
Answer: It interprets the instruction to determine the operation and operands.
Enhanced Note: The control unit decodes the opcode and prepares the CPU for
execution.
18. Define an opcode.
Answer: The operation code in an instruction that specifies the operation to be
performed (e.g., ADD, MOV).
Enhanced Note: It’s typically the first part of an instruction, interpreted by the
control unit.
19. What is the purpose of an assembler?
Answer: It translates assembly language into machine code.
Enhanced Note: It converts human-readable mnemonics (e.g., MOV) into binary
instructions.
20. Name one difference between CISC and RISC.
Answer: CISC uses complex, multi-cycle instructions; RISC uses simple, single-
cycle instructions.
Enhanced Note: CISC aims to reduce code size, while RISC focuses on execution
speed.
5-Mark Questions

1. What is the role of registers in a CPU? Provide examples of common registers.

Answer: Registers are small, high-speed storage locations within the CPU used to
hold temporary data during processing. They enable fast data access compared to
main memory. Common registers include:
o Program Counter (PC): Stores the address of the next instruction.
o Instruction Register (IR): Holds the current instruction being decoded.
o Accumulator: Stores intermediate arithmetic or logical results.
o General-Purpose Registers (R1, R2): Used for various data manipulations.
Registers improve CPU efficiency by reducing memory access time.
Enhanced Note: Registers are critical for tasks like holding operands during
ALU operations or maintaining program state.
2. Explain the concept of addressing modes with two examples.
Answer: Addressing modes define how operands are accessed in an instruction.
They specify whether the operand is a value, register, or memory address.
o Immediate Addressing: The operand is a literal value in the instruction, e.g.,
ADD R1, #5 adds 5 to register R1.
o Direct Addressing: The operand is a memory address, e.g., LOAD R1, [1000]
loads the value at memory address 1000 into R1.
Enhanced Note: Addressing modes enhance flexibility, allowing efficient
data access for different instruction types (e.g., arithmetic, data transfer).
3. Differentiate between a compiler and an assembler.
Answer:

• Compiler: Translates high-level programming languages (e.g., C, Java) into machine

code, performing syntax checking, optimization, and generating executable code. It
works with complex code structures and produces machine code for entire
programs.
• Assembler: Translates low-level assembly language (e.g., MOV, ADD) into machine
code, where each instruction typically maps to one machine instruction.
Assemblers are simpler, handling mnemonic-based code, and do not perform
extensive optimization like compilers.
Enhanced Note: Compilers produce intermediate code (e.g., bytecode in Java),
while assemblers produce direct binary. Example: A C compiler converts x = y + z
into multiple machine instructions; an assembler converts ADD R1, R2 into a single
instruction.

4. Describe the fetch phase of the fetch-decode-execute cycle.

Answer: In the fetch phase, the CPU retrieves the next instruction from memory. The
Program Counter (PC) holds the memory address of the instruction. The Control Unit uses
this address to fetch the instruction via the address bus and loads it into the Instruction
Register (IR). The PC is then incremented to point to the next instruction. This phase
ensures the CPU has the instruction ready for decoding and execution.

Enhanced Note: The fetch phase is critical for pipelining in modern CPUs, where fetching
the next instruction overlaps with decoding or executing the current one.

5. Explain the role of the operating system in program execution.

Answer: The operating system (OS) plays a critical role in program execution. It loads the
program from secondary storage into main memory, allocating necessary memory space.
The OS initializes the execution environment by setting the Program Counter (PC) to the
program’s starting address. It manages processes, scheduling them for CPU time and
handling context switching for multitasking. The OS also coordinates I/O operations,
ensuring proper communication with devices, and manages memory, preventing conflicts
between programs. Finally, it handles program termination, freeing resources for other
tasks.

Enhanced Note: The OS also provides error handling (e.g., for invalid memory access) and
supports system calls for program-device interaction.

15-Mark Questions

1. Discuss the roles of the operating system and compiler/assembler in program

execution.
Answer:
o Operating System:
▪ Program Loading: Loads the program from secondary storage into
RAM, allocating memory.
▪ Process Management: Schedules the program as a process,
assigning CPU time and handling multitasking via context switching.
▪ Memory Management: Ensures memory isolation and efficient
allocation.
▪ I/O Management: Manages communication with I/O devices.
▪ Termination: Frees resources when the program ends.
o Compiler/Assembler:
▪ Compiler: Translates high-level code (e.g., C) into machine code,
optimizing for performance and checking syntax errors. It generates
an executable file.
▪ Assembler: Converts assembly code (e.g., MOV R1, R2) into machine
code, with a one-to-one mapping of instructions.
Interaction: The compiler/assembler produces machine code that
 ▪ the OS loads into memory. The OS then manages the execution
environment, ensuring the CPU can fetch, decode, and execute the
instructions. For example, a C program is compiled into machine
code, loaded by the OS, and executed via the fetch-decode-execute
cycle.
Enhanced Note: The OS and compiler/assembler together bridge
high-level programming and hardware execution, ensuring efficient
resource use and correct program behavior.

2. Explain instruction formats and addressing modes with examples.

Answer:

1. Instruction Format: Defines the structure of a machine instruction, typically

including:
o Opcode: Specifies the operation (e.g., ADD, LOAD).
o Operands: Data or addresses involved.
Example: A 32-bit instruction like ADD R1, R2 might be formatted as:
| 8-bit Opcode | 12-bit Operand 1 (R1) | 12-bit Operand 2 (R2) |
For ADD R1, R2, the opcode is ADD, and operands are registers R1 and R2.
2. Addressing Modes: Define how operands are accessed. Common modes include:
o Immediate: Operand is a literal, e.g., ADD R1, #5 (adds 5 to R1).
o Direct: Operand is a memory address, e.g., LOAD R1, [1000] (loads value at
address 1000 into R1).
o Indirect: Operand is the address in a register, e.g., LOAD R1, [R2] (loads
value at the address in R2).
o Register: Operand is in a register, e.g., ADD R1, R2 (adds R2 to R1).
o Indexed: Address is base + offset, e.g., LOAD R1, [R2 + 4] (loads value at
address in R2 plus 4).
These formats and modes ensure flexibility in accessing data, optimizing
CPU operations.
Enhanced Note: Instruction formats vary by architecture (e.g., fixed-length in
RISC, variable-length in CISC), impacting decoding complexity.

3. Explain the organization of a stored program computer with a labeled diagram.

Answer: A stored program computer, based on the von Neumann architecture,
stores both instructions and data in the same memory. Its key components are:

• CPU: Contains the Arithmetic Logic Unit (ALU) for computations, the Control Unit
(CU) for coordinating operations, and registers for temporary data.
• Memory: Stores instructions and data in RAM (volatile) or secondary storage (non-
volatile).
• I/O Devices: Facilitate user interaction (e.g., keyboard, monitor).
• Bus System: Includes data bus (transfers data), address bus (specifies memory
locations), and control bus (sends control signals).
Operation: The CPU fetches instructions from memory, decodes them, and
executes them using the ALU and registers, with the OS managing resources.
Diagram:
• +-----------------+ +-----------------+
• | Input |<-------->| CPU |
• | Devices | | (ALU, CU, |
• | |<-------->| Registers) |
• +-----------------+ +-----------------+
• | | ^
• | | |
• v v |
• +-----------------+ +-----------------+
• | Output |<-------->| Memory |
• | Devices | | (RAM, Storage) |
• +-----------------+ +-----------------+
• ^ ^
• | |
• +--------Bus System-------+

4. Discuss the instruction set of a computer and its types. Compare CISC and
RISC architectures.
Answer:

• Instruction Set: The collection of all instructions a CPU can execute, defining its
capabilities. Types include:
o Arithmetic: ADD, SUB, MUL (e.g., ADD R1, R2).
o Logical: AND, OR, NOT (e.g., AND R1, R2).
o Data Transfer: LOAD, STORE (e.g., LOAD R1, [1000]).
o Control Flow: JUMP, BRANCH (e.g., JMP 2000).
o I/O Instructions: For device communication.
• CISC vs. RISC:
o CISC (Complex Instruction Set Computing):
▪ Features complex instructions (e.g., multi-cycle operations like MULT
in x86).
▪ Variable-length instructions, reducing code size but increasing
complexity.
 ▪ Example: MULT R1, [1000] (multiply R1 by value at address 1000).
▪ Advantages: Fewer instructions needed; supports complex
operations.
▪ Disadvantages: Slower execution, complex hardware design.
o RISC (Reduced Instruction Set Computing):
▪ Uses simple, uniform instructions (e.g., ARM’s ADD R1, R2, R3).
▪ Fixed-length instructions, simplifying decoding and pipelining.
▪ Example: ADD R1, R2, R3 (adds R2 and R3, stores in R1).
▪ Advantages: Faster execution, simpler hardware, better for
pipelining.
▪ Disadvantages: Larger code size due to simpler instructions.
Comparison: CISC is suited for complex tasks with fewer
instructions, while RISC is optimized for speed and simplicity,
common in modern systems like mobile devices.
Enhanced Note: RISC’s simplicity enables techniques like pipelining
and superscalar execution, while CISC’s complex instructions reduce
the number of instructions per program.

5. Describe the fetch-decode-execute cycle in detail with an example.

Answer: The fetch-decode-execute cycle is the process by which a CPU executes
instructions:

• Fetch: The CPU retrieves an instruction from memory using the Program Counter
(PC). The instruction is loaded into the Instruction Register (IR), and the PC is
incremented.
• Decode: The Control Unit interprets the instruction’s opcode to determine the
operation and identifies operands (e.g., registers or memory addresses).
• Execute: The CPU performs the operation, such as arithmetic (via ALU), data
transfer, or branching (updating PC).
Example: For ADD R1, R2 (add R2 to R1):
• Fetch: PC points to the instruction’s address (e.g., 1000). The instruction is fetched
into IR, and PC becomes 1001.
• Decode: The opcode ADD is identified, with operands R1 and R2.
• Execute: The ALU adds the values in R1 and R2, storing the result in R1.
The cycle repeats for the next instruction, ensuring continuous program execution.
Enhanced Note: Modern CPUs use pipelining to overlap fetch, decode, and execute
phases, improving performance.