Systolic FIR Filter FPGA Implementation

Using Single-Channel Method

A. Ramesh Kumar K. Hemanth Lakshmi B. Sriraj P. Raja Rajasri
Associate prof., dept of ECE Phani Prasad Department of Department of ECE
VNR Vignana Jyothi Institute Department of ECE ECE VNR Vignana Jyothi
Of Engineering and VNR Vignana Jyothi VNR Vignana Jyothi Institute
Technology Institute Institute Of Engineering and Of Engineering and
(affiliated to JNTUH) Of Engineering and Technology Technology
Hyderabad, India Technology (affiliated to JNTUH) (affiliated to
[email protected] (affiliated to Hyderabad, India JNTUH)
JNTUH) [email protected] Hyderabad, India
Hyderabad, India [email protected]
[email protected]

Abstract— consumption of conventional FIR filter topologies are constrained,

To effectively reduce noise in Electrooculography (EOG) signals, a which might be an issue in real-time applications.
novel architecture for a Finite Impulse Response (FIR) filter is
Proposed a novel FIR filter architecture aimed at a successful noise
proposed in this project. EOG signals—which are used to detect
reduction in EOG data. The recommended architecture addresses the
eye movements—are frequently distorted by various kinds of noise, shortcomings of traditional FIR filter architectures by applying a
including electromagnetic interference and muscle activity. state-of-the-art coefficient quantization technique that reduces the
number of multipliers required in the filter. Also, a cutting-edge
Traditional FIR filter architectures have limitations in terms of
method for reducing the filter's memory size is proposed, which
power usage and delay, which can be problematic in real-time uses less power. The architecture is implemented in hardware, and
applications. The suggested architecture overcomes these performance evaluation is done through simulation. The proposed
architecture is evaluated using both simulated and real EOG signals.
drawbacks by employing a cutting-edge method for coefficient Comparing the proposed design to conventional FIR filter
quantization that lowers the quantity of multipliers needed in the topologies, simulation results show that both latency and power
filter. A fresh approach to decreasing the memory size of the filter consumption are significantly reduced. The recommended
coefficient quantization method can cut the number of multipliers
is also suggested, which also reduces power usage. The architecture needed in half and the memory footprint of the filter in half. These
is built in hardware, and simulation is used to assess how well it upgrades lead to a decrease in power usage. The results demonstrate
performs. the suggested architecture's ability to successfully reduce noise
while maintaining the quality of the EOG signal. Using genuine
EOG signals, the suggested architecture is also put to the test
In comparison to conventional FIR filter architectures, simulation
findings show that the proposed architecture significantly reduces Comparing the proposed design to conventional FIR filter
both delay and power consumption. The number of multipliers topologies, simulation results show that both latency and power
needed can be reduced by up to 50% using the proposed coefficient consumption are significantly reduced. The recommended
quantization method, and the memory footprint of the filter can be coefficient quantization method can cut the number of multipliers
reduced by up to 30% using the memory reduction technique. needed in half and the memory footprint of the filter in half.. These
Power consumption decreases as a consequence of these
upgrades lead to a decrease in power usage. The results demonstrate
improvements.
the suggested architecture's ability to successfully reduce noise
while maintaining the quality of the EOG signal. Using genuine
EOG signals, the suggested architecture is also put to the test. By
I. INTRODUCTION
utilizing a unique method for coefficient quantization and a novel
strategy for reducing the filter's memory footprint, the
A non-invasive method called electrooculography (EOG)
is used to measure eye movements by capturing the electrical recommended architecture considerably decreases both latency and
potential variations that the eye produces. EOG signals are power consumption when compared to standard FIR filter
frequently applied in oculomotor dynamics research, brain-
computer interfaces, and eye-tracking systems. However, architectures. The same outlined structure can be used for real-time
the usefulness of EOG signals in these applications may be EOG signal processing applications to increase the utility of gadgets
constrained by the frequent contamination of these signals by
other sources of noise, such as electromagnetic interference like eye tracking systems and brain-computer interfaces. The novel
(EMI) and muscle activity. To improve the quality of the EOG method for reducing the filter's memory footprint and the
data, noise suppression is frequently required.. A popular
method for reducing noise in EOG signals is the use of Finite recommended method for coefficient quantization can also be used
Impulse Response (FIR) filters. These filters are distinguished in other signal processing applications.
by their linear phase and capacity to reduce noise while
maintaining the signal's integrity. However, the delay and power
 and systems.
The best strategy may also improve the functionality of
other gadgets, such as virtual reality goggles, disability assistive II. ADDERS AND MULTIPLIERS
technology, and medical software that monitors patients' eye The following sub-sections describe different types of
movements for neurological problems. The presence of multiple adders and multipliers.
The first sub-section describes about the 4-bit CSA and
sources of noise, including EMI and muscle activity, is one of its operation. The second-sub section describes about how
the biggest obstacles in EOG signal processing. Certain types of the 16-bit CSA will be forming using 4-bit CSA. The third
sub-section describes about the Booth Multiplier and its
noise can be particularly problematic in real-world applications
because they can make it difficult to correctly detect eye
movements and interpret the resultant EOG data. Due to their
limits in power utilization and latency, conventional FIR filter
topologies might not be suitable for real-time EOG signal
processing applications.

By utilizing cutting-edge coefficient quantization

techniques to decrease the number of multipliers needed in the
filter, the suggested invention fixes these flaws. Moreover, a
new technique is proposed to reduce the memory size of the
filter, which also reduces the power consumption. By lowering
the amount of multipliers and memory needed for the filter, the
suggested architecture can dramatically reduce both latency and
power consumption when compared to standard FIR filter
architectures. The results show that the proposed architecture
can effectively suppress noise while preserving the EOG signal
integrity. The proposed architecture is also tested with his real
EOG signal. This is a key component of the proposed design as
it ensures that the EOG signal can be correctly interpreted and
applied in real-world environments. DS. To suppress the noise
in the EOG signal, this work introduces a novel delay and
energy efficient FIR architecture. Compared with conventional
FIR filter architectures, the proposed architecture significantly
reduces both delay and power consumption by adopting a new
coefficient quantization technique and a novel approach to
reduce the memory footprint of the filter. To do. The proposed
design can be used to improve the functionality of devices such
as eye-tracking systems and brain-computer interfaces, making
it suitable for real-time EOG signal processing applications. The
proposed coefficient quantization technique and a new technique
for reducing the memory footprint of filters are a valuable
addition, especially to the field of signal processing and EOG
signal processing, as they can be used for other signal
processing applications. The suggested design also benefits from
the fact that it may be implemented on a variety of hardware
platforms, including application-specific integrated circuits
(ASICs) and field-programmable gate arrays (FPGAs). This
increases the potential impact of the proposed architectures in
various fields and enables their integration into various devices
operation. The fourth sub-section describes about a Principle second set outputs are carried as inputs for the third set
Element (PE) will be formed. and the inputs for the fourth set are the outputs of the third
A. 4-BIT CARRY SELECT ADDER set.

A CSA is often made up of ripple carry adder and a

mux. During the addition of two n-bit values with a
CSA, two ripple carry adders are required to calculate
the value twice, one taking the carry-in as zero while the
other assuming the carry-in as one. After calculating the
two outcomes and selecting the correct carry-in, the mux
selects the appropriate sum and carry-out. The internal
structuring of the 4-bit CSA is displayed
below.

Fig. 1. 4-Bit CSA

Fig. 3. 16-Bit CSA Schematic
B. 16- BIT CARRY SELECT ADDER
C. 8-BIT BOOTH MULTIPLIER
To implement the 16-bit CSA 4-bit CSA is the base idea
in which cascading of the 4-bit CSA takes place, but the first With fewer additions and subtractions, the Booth
adder will not have two sets of Full Adders because the first algorithm is a fast way to multiply binary numbers in
Cin will always be 0 so in order to reduce the time it will be their signed 2's complement representation. The idea
helpful. behind it is that while strings of 0s in the multiplier
just require shifting, strings of 1s in the multiplier
starting with bit weight 2k to all the way having bit
weight 2m are equivalent to 2(k+1) to 2m [10]. Like
all multiplication techniques, the booth procedure
necessitates looking at the multiplier bits and shifting
the partial result. Before shifting, the multiplicand may
be increased, decreased, or left unchanged in
accordance with the guidelines listed below:
1) Every time the multiplicand comes across the
first least significant 1 in a series of 1s in the
multiplier, it is subtracted from the partial product.
2) It is added to the partial product when the
multiplicand comes across the first 0 in a series of 0s
in the multiplier (presuming there was a preceding
Fig. 2. 16-Bit CSA "1").

Each of the sectors in a CSA does two parallel additions, 3) When the multiplier bit is the same as the
one with a Cin as zero and the other with a Cin as one. A preceding multiplier bit, the partial product is
16- bit CSA is divided into sectors as shown in Fig. 2 that unaltered.
range in length from 1 to 6 and represent the least to most
significant bits. The 16-bit CSA Schematic sector in Figure
3 serves as an example of the overall idea.
Fig. 2 states that on passing from the first set of Full
Adders the next step carries out by taking inputs as
output from the first set to the second set of Full Adders.
The

Fig. 4. 8-Bit Booth Multiplier

The SC is a sequence counter that displays the total number The mathematical expression of the FIR filter is
of bits, and the initial values of the AC and Qn 1 bits are
zero in the flowchart below. For multiplicand bits, there is
BR, and for the multiplier, there is QR.
Then, two multiplier bits appeared. These are identified as
Qn and Qn 1, where Qn stands for the last bit of QR and Qn To design a 1-Tap Systolic FIR Filter we need to have a
1 for the Qn bit that has been raised by one. Before Multiplier and Adder. The 16-bit Carry Select Adder and 8-
executing the arithmetic shift operation, we must remove the bit Booth Multiplier are used in this paper.
multiplier from the partial product in the accumulator AC if
two of the multiplier's bits are equal to 10. (ashr). Before
executing the arithmetic shift operation (ashr), which
contains Qn + 1, we must add the multiplicand to the partial
product in accumulator AC if both multipliers are equal to 1.
The arithmetic shift operation is used by Booth's method to
move the AC and QR bits one bit to the right while keeping
the sign bit in AC in place. And the sequence counter is
decremented indefinitely until the computational loop is
repeated. [11].

Fig. 7. Block diagram of 1-Tap Systolic FIR Filter

III. IMPLEMENTATION

A. PROPOSED MODEL
In this proposed model the input that we are initially
giving is Xin, Yin, and FIR filter coefficients. Where Xin
is an 8-bit input whereas Yin is 16-bit input and the output
is a 16-bit binary output (Yout).
The proposed model is shown in Fig.8

Fig. 5. 8-Bit Booth Multiplier Algorithm

D. 1-TAP SYSTOLIC FIR FILTER

For direct-form FIR filters, systolic FIR filters are
frequently the best option. The systolic design's multiplier-
adders chain creates a pipeline FIR structure that is fully
used. With a one-unit delay, the input data are fed into a
series of registers or flip-flops that serve as buffer units. The
adder chain generates the final output by accumulating the
inner products. demonstrates four coefficient systolic FIR
filters in the form of DSP blocks. The DSP blocks improve
latency while optimizing design implementation. Because
there is no adder tree, this technique requires fewer
hardware resources than direct FIR design [12]. The DSP
blocks, which make up half of the tap number, are used to
calculate parameters like latency. To obtain N coefficients
the systolic FIR filter takes N slices. Fig. 8. Proposed Model

B. IMPLEMENTATION OF 1-TAP SYSTOLIC

FIR FILTER
For 1-Tap Systolic FIR Filter in this paper 8-bit input is
passed down to the multiplier and the 16-bit FIR Filter
Coefficient input to the FIR Filter Coefficient. Thus, after
the multiplication is completed by the Multiplier it will be
directed to the Adder and after the addition is completed we
will be getting our 16-bit FIR output.
By implementing the Adder and Multiplier desired
Fig. 6. 1-Tap Systolic FIR Filter
output of a 1-Tap Systolic FIR filter will be formed as
shown in Fig. 12. This 1-Tap Systolic FIR Filter will be D. IMPLEMENTATION OF 256-TAP SYSTOLIC
used as the Principal Element (PE) for further FIR FILTER
implementations.
In the 256-Tap Systolic FIR Filter take the 64-Tap FIR
Filter four times in a cascaded manner to get it.
In other words, take PE 256 times in a cascaded manner
in order to implement it.
The implemented 16-Tap Systolic FIR Filter using
Verilog code in the Xilinx software module is shown in
Fig.11.

Fig. 9. 1-Tap Systolic FIR Filter

As shown in Fig. 9 the 1-Tap Systolic FIR Filter is

implemented using Verilog code in Xilinx software. It is the
Principal Element.

C. IMPLEMENTATION OF 16-TAP SYSTOLIC

FIR FILTER
In the 16-Tap Systolic FIR Filter, the PE should be
used 16 times in a cascaded manner in order to get it.
In other words, take PE 256 times in a cascaded manner
to get it.
The implemented 16-Tap Systolic FIR Filter using
Verilog code in the Xilinx software module is shown in
Fig.10.

Fig. 11. 256-Tap Systolic FIR Filter

IV. RESULT

A. 1-TAP SYSTOLIC FIR FILTER

Fig.12 demonstrates the simulation output of the 1-Tap
Systolic FIR Filter. It shows the output as 5 when the Xin is
given as 5 and the FIR Filter coefficient is 1 and Yin is 0.

Fig. 12. Results of 1-Tap Systolic FIR Filter

B. 256-TAP SYSTOLIC FIR FILTER

Fig.13 demonstrates the simulation output of the 256-
Fig. 10. 16-Tap Systolic FIR Filter Tap Systolic FIR Filter. It shows the output as 1280 when
the Xin is given as 5 and FIR Filter coefficient is 1 and Yin
is 0.
 number of slices that represent the optimal region while
increasing maximum frequency responsiveness. By
comparing this proposed FIR filter to the existing FIR
filters, this proposed symmetric single-channel systolic FIR
filter introduced here greatly decreases the amount of
hardware resources needed and speeds up operation. Future
iterations of the enhanced algorithm will be compatible with
modern communication networks since they will only
require a specific number of slices on the FPGA device.
Signal processing tasks can also be performed using the
suggested method.

Fig. 13. Results of 256-Tap Systolic FIR Filter

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