NIT Jamshedpur - Computer Organization and Architecture
End Semester Exam - Complete Solved Paper (CS1402)
Q1) 1A) What are the differences between static RAM and dynamic RAM? Why the memory organisa
Static RAM (SRAM): Faster, expensive, no need for refreshing, used in cache.
Dynamic RAM (DRAM): Slower, cheaper, needs periodic refreshing, used in main memory.
Memory organization is hierarchical to balance speed and cost - faster, smaller memory (like cache) is placed
closer to CPU, while slower, larger memory (like HDD) is placed farther.
Q2) 1B) Show the block diagram of one 25616-bits RAM chip. How many such chips are needed for
Block Diagram: Each chip has 256 words 16-bit each = 4KB.
Required memory = 2048 16 bits = 32KB.
So, 32KB / 4KB = 8 chips needed.
Interconnection involves connecting address lines (A0-A7) to all chips, with chip select lines determining
which chip is active.
Q3) 2A) What is cache memory? What is hit ratio? Techniques to increase it?
Cache memory is a small, fast memory close to CPU storing frequently used data.
Hit Ratio = (Hits / (Hits + Misses)).
To increase hit ratio: use larger/faster cache, better mapping techniques, prefetching, and good replacement
policies.
Q4) 2B) Why is cache memory mapping required? Compare direct and associative mapping. Compu
Mapping is needed to locate cache lines.
Direct Mapping: one memory block maps to one cache line.
Associative Mapping: any memory block can map to any cache line.
Given 128KB memory and 16KB cache:
Number of blocks in cache = 16KB / block size (assume 1B) = 2^14.
Number of memory blocks = 2^17 (128KB).
Tag bits = 17 - log2(2^14) = 3 bits.
NIT Jamshedpur - Computer Organization and Architecture
End Semester Exam - Complete Solved Paper (CS1402)
Q5) 3A) Limitation of restoring division. Divide 17 by 3 with register values.
Restoring division is slow and requires restoring partial remainder.
Binary of 17 = 10001, 3 = 11. Use restoring method to divide. Steps involve shifting, subtracting divisor,
checking sign, restoring if negative, and recording quotient bits.
Q6) 3B) Can pipelining add two arrays of floating-point numbers?
Yes, pipelining can be used, but floating-point operations are complex and cause data hazards. Requires
separate stages (fetch, decode, align, execute, normalize). Special care is needed for dependencies.
Q7) 4A) What is pipeline? Show max speedup for k stages.
Pipeline divides task into stages; instructions enter one per clock cycle.
Speedup = Time_non-pipelined / Time_pipelined = n / (k + n - 1). For large n, max speedup ~ k.
Max speedup is ideal only when there are no hazards and equal stage times.
Q8) 4B) What is hazard? Types and solutions?
Hazards are problems that stall pipeline:
1. Data Hazard: Use forwarding or stalls.
2. Structural Hazard: Use duplicate hardware.
3. Control Hazard: Use branch prediction or delay slots.
Q9) 5A) What is asynchronous data transfer? Explain destination-initiated handshaking.
Asynchronous transfer doesn't use a common clock. Destination-initiated transfer:
- Destination sends READY signal.
- Source puts data and sends DATA VALID signal.
- Destination acknowledges.
Used when source and destination operate at different speeds.
Q10) 5B) Programmed I/O vs Interrupt-initiated I/O?
NIT Jamshedpur - Computer Organization and Architecture
End Semester Exam - Complete Solved Paper (CS1402)
Programmed I/O: CPU waits and checks device status - wasteful.
Interrupt I/O: Device sends interrupt when ready - CPU is free till then, more efficient.
Q11) 5C) Explain the DMA operation using necessary diagram.
DMA allows direct transfer between I/O and memory without CPU involvement:
Steps:
1. CPU sets up DMA controller with address and size.
2. DMA requests bus.
3. CPU grants control.
4. DMA transfers data.
5. DMA interrupts CPU after completion.
See diagram in previous response.
