4 | Microcontrollers and Applications

Microprocessors and microcontrollers are semiconductor chips that can function as a

processor in a computing system. In the process of familiarizing the readers with an overview of
their operations and the commonly available processing platforms, the next section will highlight
the basic organization of modules in a computing system.

1.2 Basic Computer Organization

Any computing system
consists of three different
components: Central Processing CPU
Unit (CPU), memory and
peripheral devices (primarily the Address bus
I/O devices). The CPU needs to Data bus
communicate with the memory
modules and peripherals to Control bus
accomplish its computational Memory Peripherals
task. This communication takes
place via a strips of wire, called a
Fig 1.2: A typical computer system
bus. A bus may typically be of
width 8-bits, 16-bits, 32-bits etc.
having number of wires equal to its bit-width. For a bus of, say 16-bits, 16 bits of data could be
transferred from CPU to memory/peripherals, or vice versa, at a time. This enhances the speed of
data transfer, compared to single-wire connections. Transfer of information over a bus may be
unidirectional or bidirectional in nature. For a unidirectional bus, transfer is from a master device
(for example, CPU) to a slave device (for example, memory/peripherals), while for a bidirectional
bus, flow of information may also be from the slave device to the master. In any computer system,
there are three types of buses: address bus, data bus and control bus. Out of these, address bus and
control bus are generally unidirectional, while the data bus is bidirectional. A typical bus
connection in a computer system has been shown in Fig 1.2.
1.2.1 Address Bus
CPU uses the address bus lines to identify a memory location or a peripheral that it wants
to access. A memory chip consists of a number of addressable locations. Each location may
correspond to one or more bytes of space, typically known as word size of the memory. Availability
of more number of bits in the address bus of CPU enables it to refer to more number of memory
locations and/or I/O devices. For a CPU with x-bit address bus, the total number of distinct
addresses that it can generate is 2x. Out of these, some may correspond to memory locations, while
others to identify peripherals. On the other hand, a typical memory chip has a set of address lines.
For a chip with 1024 (1 kilo) locations, number of address lines is 10 (as 210 = 1024). If the bit
pattern corresponding to m appears in the address lines, the location m in the chip gets accessed.
Apart from that, each memory chip contains a chip select input which needs to be enabled to access
the chip. This helps in combining more than one memory chips with smaller capacities to cover the
full address range of a processor. It has been illustrated in the following example.
 Microcontrollers and Applications | 5

Example 1.2: Suppose that the CPU

Memory 1
has 16-bit address bus. Thus, total
memory space accessible by it is 216 = Address
64k. Consider each memory chip to be A0-A13 CS
of size 16k with 14 address lines. To get
64k memory, four such chips need to be A14 Memory 2
connected. To develop the system, as A15 Address

CPU
shown in Fig 1.3, least significant 14 00

Decoder
0 01 CS
address lines (A0 to A13) are connected 10
directly to all the four memory chips. 1 11 Memory 3
The next two higher order address lines Address
A14 and A15 are passed through a 2-to-4 CS
decoder to generate 4 chip select signals
for the memory chips. Thus, for the Memory 4
addresses generated by the CPU in the Address
range of 0000H-3FFFH Memory 1 is CS
accessed. For addresses 4000H-7FFFH,
8000H-BFFFH, and C000H-FFFFH, Fig 1.3: Memory interfacing with CPU
Memory 2, Memory 3 and Memory 4
are accessed, respectively.
In Example 1.2, if some I/O devices need to be connected as well, some of the decoder
output lines may be connected to enable those devices. This, of course, will reduce the amount of
memory that could be attached in the system.
1.2.2 Data Bus
This is used to transport data between the CPU and memory and/or I/O devices. More the
width of the data bus, more data can be transferred at a single go. However, having more number
of lines in a data bus (or, any other bus) also means more required area on the board (housing the
full system) to route them
8-bit Data Bus
between the modules,
increasing the cost of the D0-3
system. Typical size of data
bus varies between 8 to 64 D4-7
CPU

Address & CS
Memory 1 Memory 2
bits. Processing power of the
CPU is often guided by the
width of the data bus. If the
data bus width is 8-bits,
modules internal to the CPU Fig 1.4: Connecting memory modules in parallel
are generally designed to do
operations (such as, addition, subtraction, multiplication etc.) on 8-bit operands only. It may be
noted that data bus of individual memory chips may be of lesser width than the CPU data bus. A
6 | Microcontrollers and Applications

number of memory chips may be operated in parallel to match the data bus lines of the CPU. For
example, in Fig 1.4, individual memory chips are of 4-bit data bus. Two such chips are connected
in parallel to cater to the 8-bit data bus requirement of the CPU.
1.2.3 Control Bus
Apart from the address and data bus lines, CPU also need several control signals connected
to the memory chips and I/O devices. Further, it needs to check the status of devices connected to
the system. Sometimes, devices need to contact the CPU proactively on occurrence of some event,
for example, the user pressing a key on the keyboard. These control and status lines, from and to
the CPU, collectively form the control bus. There cannot be any typical sizes for the control bus.
However, two very important control signals for any CPU is the Read (RD) and the Write (WR).
The signal RD is activated when the CPU needs to read the content of a memory location or input
device. Similarly, WR is activated when the CPU wants to modify the content of a memory location
or output some data to an output device.
A computer system
normally contains two types of RD
memory modules – Random WR
Access Memory (RAM) and
CPU

RAM ROM
Read Only Memory (ROM).
Content of ROM is permanent in
nature and is used to hold
program/data that is not going to
change frequently. Examples of Fig 1.5: RD, WR signals to memory
such content include booting
program of the system, some specific bit pattern that may be used to display some pattern in output
device, etc. ROM content could be reprogrammed only by using some additional devices,
commonly known as Programmer. On the other hand, content of RAM is volatile. It is used to keep
user programs and data. The CPU can only read the contents of ROM, however, may do both read
and write operations for RAM. The control lines RD and WR are to be connected accordingly, as
shown in Fig 1.5.
Example 1.3: Fig 1.6 shows a computer system with a processor having 16-bit address bus and
8-bit data bus. The system has a total of 64kB of memory interfaced with the processor. Out of
these 64kB, 16kB is ROM and 48kB RAM. Individual memory chips are of capacity 16k 4-
bits. Thus, each 8-bit memory word has been configured by connecting two such memory chips
in parallel. Address lines A0 to A13 have been connected to the address lines of the memory chips.
A 2-to-4 decoder has been used to generate the chip select signals from the highest order address
bits, A14 and A15. The RAM chips have got both the RD and WR control signals connected to
them, as their locations may both be read and written by the CPU. On the other hand, only the
RD line has been connected to the ROM chips, as the ROM locations could only be read by the
CPU. It may be noted that the data lines of ROM are unidirectional, coming out of the memory
chip. For RAM chips, the data lines are bidirectional, as data may both be read or written onto
 Microcontrollers and Applications | 7

them. Processor generates address in the range of 0 to 64k that get mapped onto pair of memory
chips to give 8-bit data.

D0-D7

D0-D3
D4-D7
ROM ROM
A0-A13 CS CS

A14
A15
CPU

RAM RAM
00
Decoder

0 01 CS CS
10
1 11

RAM RAM
CS CS
RD
WR

RAM RAM
CS CS

Fig 1.6: Interfacing 16KB ROM and 48KB RAM with CPU

1.2.4 CPU Internals

After looking into the interfacing of CPU with other components in the system, next, let
us go into internal structure of the CPU. Fig 1.7 shows the structure of a typical CPU. It consists of
the following components.
1. A set of Registers to store information temporarily. The information stored may be the data
on which the CPU needs to operate, or the address of a memory location containing the
data to be fetched into CPU, for operation. The registers could be of sizes 8-bit, 16-bit, 32-
bit, 64-bit etc. in different CPUs. More the number of registers in a CPU, it is better. As in
that case, for most of the operations, CPU will find the corresponding data within itself and
thus does not need additional time to fetch from memory. Wider registers enable larger
data size. However, to limit the size and cost of the CPU, number of registers in a CPU is
restricted. For most of the contemporary processors, it is not more than 64.
2. An Arithmetic Logic Unit (ALU) to carry out to carry out the arithmetic and logic operations
intended by the program instructions. Examples of arithmetic operations are ADD,
SUBTRACT, MULTIPLY, DIVIDE etc. Logic operations include AND, OR, NOT as the
most common ones.
8 | Microcontrollers and Applications

3. Some special function registers are often put into the CPU, as noted next.
a. Program Counter (PC): It points to the address of the next instruction to be
executed. After fetching the next instruction from memory to CPU, PC is
incremented by size of the instruction (in number of bytes), to make it point to the
next instruction. When the CPU is powered on or is reset, PC is loaded with a fixed
value, predecided by the designer of the CPU. Content of PC is put into the address
bus to fetch the next instruction to be executed by the processor. In some of the
processors, PC is called Instruction Pointer (IP).
b. Flags: This register holds the status information with respect to the last operation
carried out by the ALU. It contains bits named as ZERO, CARRY etc. The ZERO
flag bit is set if the last operation performed by the ALU has zero as the computed
result. Similarly, the CARRY bit is set if the last operation resulted into a value
beyond the range that can be stored in the registers. The flags help in making
decisions regarding the instruction sequence to follow.

Instruction
External Address Bus
external components
Register
Registers
Control signals
to internal and

Instruction Program
Decoder & Counter
Control

Internal Bus

ALU External Data Bus

Flags

Fig 1.7: Structure of a typical CPU

c. Instruction Register (IR): This register holds the instruction as it is fetched from
the memory. Each instruction is stored in memory in a coded form. Once it reaches
the IR, the Instruction Decoder is used to decode it. Based on the instruction, the
controller generates the control signals over successive time frames to accomplish
the intended task of the instruction.
 Microcontrollers and Applications | 9

1.2.5 Operation of CPU

CPU executes the instructions one-by-one starting with the instruction at memory
location pointed to by the PC. It typically follows the sequence of operations “Fetch 
Decode  Execute” for each instruction. The operations continue till the processor executes
a HALT instruction, or as long as the processor is powered. The sequence of operations has
been enumerated in Table 1.1.
Table 1.1: Steps in instruction execution
Fetch 1. Address of next instruction pointed to by PC is put on the address bus.
2. RD signal activated.
3. Next instruction from memory reaches Instruction Register.
4. PC incremented to point to the next instruction.
Decode 5. Decoder decodes the instruction and decides the sequence in which
various control signals are to be activated to accomplish the instruction.
Execute 6. Operands for the instruction brought from memory and/or registers.
7. Operation carried out in ALU, Flags updated.
8. Result stored back in register/memory.

Example 1.4: Next we shall look into instruction execution by a hypothetical CPU shown in Fig
1.8.

External Address Bus

Instruction
Register W
R0
Control signals

R1
Instruction Program
Decoder & R2 Counter
Control

Internal Bus

ALU External Data Bus

Flags
Fig 1.8: A hypothetical CPU
10 | Microcontrollers and Applications

The CPU has three registers R0, R1 and R2 in it. Apart from that, there is a special register W
that can hold an address. The address field present in an instruction may be copied from IR to it
and made available to the address bus to access memory locations. To understand the control
signals generated over the time-steps, we assume that each register has got two signals associated
with it – load and enable. When the load signal is activated, the content from the bus it is
connected to, is copied into it. When the enable signal is activated, content of the corresponding
register is put onto the bus. For example, to copy the content of register R0 to register R1, the
signals to be activated are enable_R0 and load_R1. Similarly, ALU has control signals to
perform different arithmetic and logic operations. We shall consider the following three
instructions.
 LOAD R0, 1000 ; Load the content of Memory[1000] into R0
 ADD R0, R1, R2 ; R2  R0 + R1
 STORE R2, 3000 ; Store the content of R2 at Memory[3000]
Control signals activated at different time steps to execute these instructions have been shown
in Table 1.2.
Table 1.2: Control signals activated for different instructions
Instruction Time Control Signals
Step
t1 Enable_PC, RD
t2 Load_IR
LOAD R0, 1000 t3 Decode, Increment_PC
t4 Load_W, Enable_IR
t5 Enable_W, RD, Load_R0
t1 Enable_PC, RD
ADD R0, R1, R2 t2 Load_IR
t3 Decode, Increment_PC
t4 Enable_R0, Enable_R1, Add_ALU, Load_R2
t1 Enable_PC, RD
t2 Load_IR
STORE R2, 3000 t3 Decode, Increment_PC
t4 Load_W, Enable_IR
t5 Enable_W, WR, Enable_R2
 Microcontrollers and Applications | 11

It may be noted that the time steps t1 and t2 correspond to Fetch stage, t3 corresponds to
Decode phase and the rest of the time steps constitute the Execute phase of operation. Fetch and
Decode stages (that is, time steps t1 to t3) are same for all instructions, Execute phase depends
upon the instruction being carried out.

1.3 8085: An 8-bit Microprocessor

A microprocessor is a single silicon chip that includes all the components of a processor,
such as, ALU, registers, controller etc. to form a CPU. From our knowledge of digital design, it is
understood that the components inside a CPU (as discussed in Section 1.2.4) can be realized using
discrete electronic circuit elements, such as, logic gates and flip-flops. This strategy of processor
design was followed in the late 1960s. However, the devices used to be quite large and too slow.
In the early 1970s, with the advancement in semiconductor chip manufacturing process, entire CPU
logic could be fabricated on a single silicon chip, leading to the invention of microprocessors. The
size of the processor was almost several thousand times smaller and speed several hundred times
higher. This has been possible as in semiconductor technology, on-chip communication is much
faster than off-chip.

The first microprocessor was Intel’s 4004, introduced in 1971. It has been a 4-bit processor with
10-bit address bus and 4-bit data bus, operating at 108 kHz. It was quickly succeeded by 8008 (8-
bit data bus), 8080 and 8085. The microprocessor 8085, introduced in 1976, is a processor with 8-
bit data bus, 16-bit address bus, operating at 3 MHz clock.

Was there a miniprocessor?

Answer is “no”. From discrete component based design, the processors evolved into
microprocessors. However, compared to today’s complex processors, the microprocessors
designed at the beginning were too simple.

1.3.1 The 8085 Chip

The 8085 CPU comes as a 40-pin chip with a supply voltage requirement of +5V. It can
operate with a single-phase clock frequency 3 MHz, though some advanced versions (8085A-2)
can operate upto 5 MHz. The pin layout of the chip has been shown in Fig 1.9(a). The pins can be
grouped as per their functionality. The grouping of pins has been shown in Fig 1.9(b).
12 | Microcontrollers and Applications

VCC VSS
X1 40 VCC X1
1 1 40 20
X2 2 39 HOLD X2 28 A
2 15 High order
RESET OUT 3 38 HLDA SID A address bus

Ports
Serial I/O
SOD 4 37 CLK (OUT) 5 21 8
SOD
SID 5 36 RESET IN 4
TRAP 6 35 READY 19 AD7

Externally Initiated Signals

RST 7.5 IO/M TRAP
7 34 6 Multiplexed
RST 6.5 8 33 S1 RST 7.5 Address/Data
7
RST 5.5 9 32 RD RST 6.5 bus
8

8085A
8085A

INTR 10 31 WR RST 5.5 12 AD0

11 30 9 ALE
INTA ALE INTR 30
AD0 12 29 S0 10 S

Status Signals
Control and
29 S 0
AD1 13 28 A15
READY 33 1
AD2 14 27 A14 35 IO/M
HOLD 39 34 RD
AD3 15 26 A13
RESET IN 32
AD4 16 25 A12 36 WR
AD5 A11 31
17 24
INTA
AD6 18 23 A10 11 RESET OUT
Ack.

AD7 19 22 A9 HLDA 3
38
VSS 20 21 A8 37 CLK (OUT)

Fig 1.9(a): 8085A pin diagram Fig 1.9(b): Grouping of 8085A pins

Address and Data Bus: The 8085 CPU has 16-bit address bus A15-A0 and 8-bit data bus D7-D0.
To reduce the overall pin count,
the lower order address bus A7-A0
has been multiplexed with data AD7-0
bus lines D7-D0. For memory D7-0 Memory
Latch
8085

access, corresponding to the 16-bit ALE EN

address, the higher order address A15-8 A15-0
bits A15-A8 are held continuously
at higher order address bus.
However, the lower order address
bits, A7-A0 are held on the lines Fig 1.10: Address bus demultiplexing
AD7-AD0 only for some initial
time. After that, the data corresponding to the access is available on the lines AD7-AD0. A special
control signal, ALE (Address Latch Enable) is kept high for the duration in which the address bits
 Microcontrollers and Applications | 13

are available in AD7-AD0. ALE signal could be used to demultiplex the address and data lines by
using an external latch, as shown in Fig 1.10.

X1, X2, CLK (OUT): A crystal is connected between X1 and X2 to generate clock signal for 8085.
Internally, the crystal frequency is divided by 2. Thus, to make the processor work at 3 MHz, the
crystal frequency should be 6 MHz. The processor clock is also available at CLK (OUT) pin to
connect to other peripherals that may need synchronization with the processor clock.

Externally Initiated Signals: There are several pins in this category. Out of them, INTR, TRAP,
RST 7.5, RST 6.5 and RST 5.5 are known as interrupt lines. An activation on these lines will cause
the 8085 CPU to suspend its current work and diverge to some special routine, which may be for
serving some special device etc. For example, if a keyboard has been interfaced to 8085 via some
interrupt line, a key press may cause an interrupt to the processor. The processor now diverges to
a special routine to read the key value. Once the service is over, the processor will resume its
suspended work. The line INTA is to acknowledge an INTR input. The signals HOLD and HLDA
are used for interfacing other bus masters to the system. A bus master may be responsible for bulk
data transfer from memory. On getting signal in the HOLD line, the 8085 relinquishes its control
over address, data and control lines. It is acknowledged in the HLDA pin. The bus control is
regained via interrupt when the secondary bus master no more needs the bus. On getting a low in
the RESET IN line, the processor resets with its program counter becoming zero and activating the
RESET OUT pin to inform the interfaced devices.

Serial I/O Ports: The lines SID (Serial Input Data) and SOD (Serial Output Data) can be used for
serial I/O operations, one bit at a time.

Status Signals: Signals like RD, WR are used for memory interfaces. The lines S0, S1 and IO/M
indicates the operation that the 8085 is currently doing, such as, memory read, memory write, I/O
read, I/O write, fetch, interrupt etc.

1.3.2 Internal Architecture of 8085

Fig 1.11 shows the internal architecture of 8085A CPU. This is also known as the
Processor Programming Model, since it depicts the programming resources of the CPU, available
to the user/programmer. For the 8085A CPU, it consists of a set of general purpose and a few
special purpose registers.

General Purpose Registers (GPRs): There are six general purpose registers to store 8-bit data
inside the CPU. These are named as B, C, D, E, H and L. The registers can be paired into three 16-
14 | Microcontrollers and Applications

bit registers – BC, DE and HL. The registers can hold operands for different operations. The 16-bit
pairs can also be used to provide address to operand stored in memory.

RST 5.5
RST 6.5
RST 7.5
TRAP
INTR
INTA

SOD
SID
Interrupt Control Serial Control
8-bit Internal Data Bus

A reg (8) Temp reg(8) Flags (8) IR (8)

B reg (8) C reg (8)

D reg (8) E reg (8)
ALU (8)

H reg (8) L reg (8)

Instruction Stack Pointer (16)
Decoder Program Counter (16)

X1
Timing and Control Address Address/Data
X2
Buffer (8) Buffer (8)
HLDA
S0
S1

HOLD

RESET OUT
WR
Ready
CLK (OUT)

RESET IN
IO/M
RD

ALE

A15-A8 AD7-AD0
Address Bus Address/Data Bus

Fig 1.11: Internal Architecture of 8085A

Special Purpose Registers: There are several special purpose registers, as noted next.
1. Accumulator (A register): This is an 8-bit register, acting as one of the source operands
and the destination for all ALU operations. ALU can perform 8-bit arithmetic and logic
operations. While carrying out the ALU operation, a temporary register (marked as Temp
in Fig 1.11) holds the second operand for two-operand operations.
 Microcontrollers and Applications | 15

2. Flags: This is an 8-bit register, though only 5 bits of it are used to contain status
information corresponding to the last ALU operation. The flag bits are Zero (Z), Carry
(CY), Sign (S), Parity (P) and Auxiliary Carry (AC).
3. Program Counter (PC): A 16-bit register that contains the address of the memory location
corresponding to the next instruction to be executed.
4. Stack Pointer (SP): A 16-bit register that is used to point to a RAM location corresponding
to “stack”. The “stack” is a part of RAM that is used in the context of subprogram call or
an interrupt. For both these situations, processor saves the return address in stack, before
jumping to the subprogram. So that, when the subprogram/service routine is over, the PC
could be reloaded with the value saved in stack, and thus resume the suspended operation.
Availability of stack aids in realizing nested subprograms as well.

1.3.3 Instruction Set of 8085

The instructions supported by the 8085 CPU can be classified into five groups, as detailed
in Table 1.3. A complete discussion on the same is beyond the scope of the book. Readers may
consult the references mentioned at the end of the unit for the same.
Table 1.3: Classification of 8085 instructions
Type Purpose Examples
Data Transfer data from source to MOV C, A ; A register copied to register C
Transfer destination. The source may be a MVI B, 4FH ; B register gets 4FH
register, a memory location or an
MOV A, M ; A gets Memory[address in HL]
immediate value. Destination may
be a register or a memory location. LXI H, 125AH ; H gets 12H, L gets 5AH
Both operands cannot be memory.
Arithmetic Several arithmetic operations are ADD B ; A gets A + B
Operations supported – addition, subtraction, SUB C ; A gets A – C
increment, decrement.
INR L ; L gets L + 1
Logical Logical operations, such as, AND, ANA B ; A gets A AND B
Operations OR, XOR, Rotate, Compare, CMP C ; Compare A with C, flags affected
Complement are supported.
RLC ; Rotate accumulator left
Branching Jump conditionally or JMP 1000H ; PC loaded with 1000H
unconditionally, call subprogram, JC 1000H ; PC loaded with 1000H is CY=1
return from subprogram
CALL 1000H ; Subprogram call
RET ; Return from subroutine
16 | Microcontrollers and Applications

Machine Special instructions affecting the HLT ; Halt the CPU operation
Control operation of the CPU RST ; Software interrupt
NOP ; Do nothing

Example 1.5: The following is a 8085 code fragment that can find the maximum of a set of
numbers stored from the memory location 3000H. The number of numbers in the set is stored at
location 3000H, the numbers start from 3001H. The largest number will be stored at location
5000H.
LXI H, 3000H ; Set HL-pair to the address of the array
MOV C, M ; Get number of numbers in C
INX H ; Make HL-pair to point to the first number
MOV A, M ; Get first number in A, assume it to be the largest
DCR C ; Decrement count
L1: INX H ; Make HL-pair point to the next number
CMP M ; Compare current largest in A with next number
JNC L2 ; If CY=0, it means A is still the largest, no action
MOV A, M ; Update new largest in A
L2: DCR C ; Decrement count
JNZ L1 ; Goto L1, if some numbers left
STA 5000H ; Store the largest at memory location 5000H

1.4 8086: A 16-bit Microprocessor

The processor 8086 was introduced in 1978 with 20-bit address bus and 16-bit data bus.
However, as many of the existing microprocessor based systems were developed around 8085
processor with 8-bit data bus. In the year 1979, a variant 8088 was introduced with internal
architecture same as 8086 but having 8-bit external data bus. Both 8086 and 8088 are 40-pin chips.
Over 8085 or other 8-bit processor and many of the interfaced devices had 8-bit data bus only,
 Microcontrollers and Applications | 17

necessity was felt to have a processors,

16-bit 8086/88 processor enjoys
VCC
advantages like increased memory CLK
addressing (1 mega, compared to 64 BHE/S7
kilo), increased speed (upto 10 MHz), GND A19/S6 Multiplexed Address
powerful instruction set, possibility of GND and Status Signals
working in a multiprocessor A16/S3
INTR
environment. The 8086 chip can NMI
operate in two modes – the minimum
HOLD AD15
mode and the maximum mode. The READY
minimum mode is very close in RESET
operation as 8085. Details of signals in Multiplexed Address
the minimum mode has been shown in and Data Buses
Fig 1.12. The MN/MX pin set to ‘1’
forces the minimum mode, while INTA AD0
setting the input to ‘0’ enables the HOLDA
ALE
maximum mode operation. For the M/IO
maximum mode operation, a bus RD Control and
controller (such as, 8288) is employed WR Status Signals
to generate the necessary control TEST DEN
signals. Pins of 8086 change their MN/MX DT/R
functionality slightly to give inputs to
the bus controller. For example, the
pins S0, S1 and S2 are introduced Fig 1.12: The 8086 in Minimum Mode
instead of DEN, DT/R and M/IO
respectively. Another control LOCK is used to prevent other processors from getting control of the
bus.

1.4.1 Internal Architecture of 8086

The internal architecture of 8086 CPU has been shown in Fig 1.13. It can be logically
divided into two internal units – the Bus Interface Unit (BIU) and the Execution Unit (EU). BIU is
responsible for fetching instructions, read/write data from/to memory locations and I/O ports. EU
is entrusted with the job of executing the instructions fetched by the BIU.

Bus Interface Unit (BIU): The BIU interfaces the 8086 with external memory and I/O devices.
The 8086 has 20-bit address bus and a 16-bit data bus. Thus, it can access a total of 1 mega memory
locations of size 16-bit each. A 20-bit address produced by the 8086 processor consists of two parts
– segment and offset, each of 16-bit width. An address is computed by left shifting the 16-bit
segment value by 4 bits, creating a 20-bit value and then adding the 16-bit offset to it. That is,
𝑎𝑑𝑑𝑟𝑒𝑠𝑠 16 𝑠𝑒𝑔𝑚𝑒𝑛𝑡 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓𝑓𝑠𝑒𝑡
18 | Microcontrollers and Applications

Address Bus (20 bit)

AH AL AX
BH BL BX ALU
CH CL CX
DH DL DX
SP
General CS
BP
Registers DS
SI
SS
DI
ES
ALU Data Bus IP
(16 bit) Internal Bus 8086 Bus
Comm. Regs. Control
System
Temporary Registers
Internal Instruction Queue
Control 1 2 3 4 5 6
ALU System

Flags Execution Bus Interface

Unit (EU) Unit (BIU)
Fig 1.13: Internal Architecture of 8086

To specify the segment part, the 8086/88 CPU uses four segment registers, each of 16-bit
width – Code Segment register (CS), Data Segment register (DS), Stack Segment register (SS) and
Extra Segment register (ES). The processor allows four active segments for any program, at a time.
The code segment of a program is supposed to contain the program code. The data and stack
segments are to contain the data part and the stack part of the program, respectively. An additional
segment is allowed that is typically used as an extra data segment. When a program is loaded into
the memory, the segment registers CS, DS, ES and SS are initialized suitably to point to the base
of those segments. It may be noted that each segment can be of size upto 64 k, thus the amount of
active part of a program, at any point of time is 4 64 k 256 k. Of course, the segment registers
can be reloaded with some other values to refer to program fragments (code, data etc.) beyond 256
k size limit.
To perform program fetch, another 16-bit register, Instruction Pointer (IP) is used. IP is
equivalent to PC on 8085. To get the next instruction from memory, the register pair CS:IP is used
to generate the 20-bit address, 16 CS IP using the 20-bit ALU present in the BIU. Successive
bytes are fetched into an Instruction Queue (6 bytes in 8086, 4 in 8088). Presence of this instruction
queue enables fetch-execute overlap in 8086/88. When the current instruction is being executed by
the EU, BIU may bring in successive instructions, upto 6 bytes, into the queue.
 Microcontrollers and Applications | 19

Execution Unit (EU): The EU is responsible for decoding and executing individual instructions.
It has a 16-bit ALU for performing arithmetic and logic operations. Apart from a few temporary
registers (not available to the user), there are three sets of registers, as noted next.
 General Purpose Registers: There are four, 16-bit general purpose registers – AX, BX, CX
and DX. Each of them can also be used to behave as two 8-bit registers. AX is composed
of 8-bit registers AH and AL, BX containing BH and BL, CX containing CH and CL and
DX being composed of DH and DL. The register AX also behaves as accumulator, as in
8085.
 Pointer Registers: Stack Pointer (SP) and Base Pointer (BP) are the two 16-bit registers,
used to access data in the stack segment. SP is incremented/decremented automatically
during stack operations. Memory access via SP and BP uses SS as the segment register,
the address being computed as, 16 SS SP or BP .
 Index Registers: The 16-bit Source Index (SI) and Destination Index (DI) registers are used
primarily for indexed memory access. By default, the access via SI uses DS as the segment
register (address = 16 DS + SI) and via DI uses ES as the segment register (address = 16
ES + DI). They are also used in single-byte instruction MOVSB to transfer the content
from a source block (pointed to by DS:SI) to a destination block (pointed to by ES:DI) with
CX register holding the number of bytes to be transferred.
The instruction set of 8086/88 processor can be grouped into the following categories.
 Data Transfer Instructions – MOV, XCHG, PUSH, POP etc.
 Arithmetic Instructions – ADD, SUB, MUL, DIV etc.
 Logical Instructions – AND, OR etc.
 String Manipulation Instructions – MOVS, LODS, STOS, REP etc.
 Process Control Instructions – STC, STD, NOP, HALT, WAIT, LOCK etc.
 Control Transfer Instructions – JMP, JE, JC, CALL, RET etc.
A detailed discussion on the instructions is beyond the scope of this book and can be found in the
references noted at the end of the Unit.

1.5 Microcomputer Systems

Computing systems built around microprocessors are commonly known as

microcomputers. They have got applications in almost all domains of scientific and business
computations. Apart from the processor, such systems typically contain components, such as,
RAM, ROM, General Purpose Input-Output (GPIO) interfaces, Communication interface, Timers,
Counters, Analog Interfaces (such as, Analog-to-Digital and Digital-to-Analog Converters (ADCs
and DACs) etc.
20 | Microcontrollers and Applications

The generic components

in a microcomputer Data Bus

Microprocessor
system has been shown
in Fig 1.14. The

Counter

Comm.

DAC &
Timer/

Serial
microcomputer systems ROM RAM GPIO

ADC
available today can be
broadly classified into
the following categories.
Address Bus
Fig 1.14: Generic Microcomputer System
1. Personal
Computer (PC)/Desktop: These are mostly single-user systems with applications, such as,
office automation, finance, internet access, limited computation etc. They often contain
large number of system and application software.
2. Workstation: These are high performance desktop systems that specialize in executing
certain engineering/scientific applications efficiently. Typical examples of such
applications are Computer-Aided Design (CAD), Computer-Aided Engineering (CAE) and
Computer-Aided Manufacturing (CAM). The workstations generally possess high-end
microprocessors, large memory (both primary and secondary) and often a high-resolution
screen, specialized I/O devices etc.
3. Single-Board Computers: These are computers housed on a single Printed Circuit Board
(PCB) and is often used for educational and training purposes. Apart from the
microprocessor, the board contains limited amount of ROM, RAM, chips to realize
timer/counter operations and interfaces for very simple I/O devices (like matrix keyboard,
seven-segment LED, LCD modules, switches for digital inputs, etc.). The ROM contains
a simple monitor program, responsible for monitoring the system resources and aiding in
executing user programs.
4. Single-Chip Microcomputers (Microcontrollers): In this category, the entire
microcomputer system is fabricated onto a single silicon chip. Such systems are typically
used in different controller applications.

1.6 8-Bit Microcontroller Architecture

Fig 1.15 shows the block diagram of a typical microcontroller. On a single chip, it
integrates a processor along with its interrupt logic, oscillator to generate clock, memory (ROM
and RAM), Analog-to-Digital and Digital-to-Analog Converters, Parallel and Serial I/O Interfaces,
one or more Timers/Counters etc. However, to keep the area and power consumption within a
reasonable limit, the processor is often made much simpler than powerful microprocessors, ROM
and RAM space is limited to hold small application programs only. Microcontrollers are most
widely used in dedicated applications, known as Embedded Systems, such as, mobile phones, digital
camera, security alarm, plant control etc. to name a few. Some microcontrollers, particularly those