UNIT 3: REDUCED INSTRUCTION SET COMPUTERS (RISC)

Characteristics of a Microprocessor
1. Instruction Set : The set of complete instructions that the
microprocessor executes is termed the instruction set.
2. Word Length : The number of bits processed in a single instruction is
called word length or word size. The Greater the word size is the larger the
processing power of the CPU.
3. System Clock Speed : A Clock speed determines how fast the single
instruction can be executed in the processor. The microprocessor is
controlled by the System Clock. A Clock speeds are generally measured in
the millions of a cycles per second (MHz) and thousand million cycles per
second GHz. A Clock speed is considered to be the very important aspect of
predicting a performance of the processor.

Instruction Set Architecture (ISA)

An ISA is defined as the design of a computer from the Programmer's

Perspective. It defines how software interacts with hardware,
impacting system performance, power efficiency, and
programmability

 is the fundamental blueprint of a computer processor that

defines:

 The set of commands the processor can execute

 How programs interact with the hardware
 The available operations, data types, registers
 Memory addressing methods
 Input/output mechanisms

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This basically means that an ISA describes the design of a Computer in
terms of the basic operations it must support. The ISA is not
concerned with the implementation-specific details of a computer. It
is only concerned with the set or collection of basic operations the
computer must support.

ROLE OF INSTRUCTION SET ARCHITECTURE (ISA) IN COMPUTER

SYSTEM DESIGN

1. Hardware-Software Interface

The ISA serves as a standardized contract between software and

hardware, defining:

 How programs issue commands to the processor (e.g., arithmetic,

memory access, I/O operations).
 What operations are supported (e.g., floating-point math, vector
processing, atomic instructions).
 How data is represented (e.g., integer sizes, floating-point formats,
endianness).

This abstraction allows software developers to write code without needing to

know the underlying hardware implementation, while ensuring that
processors from different manufacturers (e.g., Intel, AMD, Apple) can run the
same software if they support the same ISA (e.g., x86, ARM).

2. Design Foundation

The ISA dictates key aspects of processor design, influencing:

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  Processor Complexity

o CISC (e.g., x86) requires complex decoders to handle variable-

length instructions.
o RISC (e.g., ARM, RISC-V) simplifies hardware with fixed-length
instructions.
 Performance Characteristics

o Single-thread speed (affected by pipeline depth, branch

prediction).
o Multithreading support (e.g., SIMD, hyper-threading).
 Power Efficiency

o RISC architectures (e.g., ARM) are more power-efficient,

making them ideal for mobile devices.
o CISC (e.g., x86) trades power for backward compatibility.
 Cost of Implementation

o More complex ISAs (x86) require larger chip designs and

higher R&D costs.
o Simpler ISAs (RISC-V) reduce manufacturing costs.

3. Compatibility Guarantee

The ISA ensures binary compatibility across different hardware

implementations:

 Same ISA, Different Microarchitectures:

o An Intel Core i9 and an AMD Ryzen both implement x86-64,

allowing them to run the same Windows/Linux software.
o Apple’s M-series chips use ARM ISA but outperform many x86
chips due to microarchitecture optimizations.
 Long-Term Software Support:

o x86 maintains decades of backward compatibility (e.g., 32-

bit code still runs on modern CPUs).

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 o ARM evolves while maintaining ecosystem stability (e.g., ARMv8
to ARMv9).

4. Performance Determinant

The ISA shapes how efficiently a processor executes code:

 Clock Speed Potential

o RISC’s simpler instructions allow higher clock speeds (e.g.,

Apple M2 hits ~3.5 GHz vs. Intel’s ~5 GHz, but with better IPC).
 Parallel Processing Capability

o SIMD (Single Instruction, Multiple Data) extensions (e.g.,

AVX in x86, NEON in ARM) accelerate multimedia workloads.
o Multi-core scaling depends on ISA support for atomic
operations and cache coherence.
 Instruction Throughput

o Pipelining efficiency (RISC’s fixed-length instructions decode

faster).
o Superscalar execution (multiple instructions per cycle)
depends on ISA simplicity.

5. System Optimization

The ISA guides critical hardware design choices:

 Memory Hierarchy

o Defines cache policies (write-back vs. write-through).

o Influences virtual memory support (page tables, TLBs).
 Pipeline Structure

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 o Deep pipelines (Intel Pentium 4) vs. short pipelines (Apple M-
series).
o Branch prediction requirements (more crucial for CISC).
 Cache Organization

o L1/L2/L3 cache sizes and prefetching strategies depend on

ISA access patterns.
o ARM’s big.LITTLE uses ISA flexibility to mix high-power and
efficiency cores.

PROCESSOR ARCHITECTURES ARE PRIMARILY DIVIDED INTO TWO

TYPES BASED ON THEIR INSTRUCTION SET DESIGN.

1. THE COMPLEX INSTRUCTION SET COMPUTER (CISC)

ARCHITECTURE features hundreds of complex, multi-step instructions
that use variable-length encoding and support multiple memory
addressing modes. Designed to minimize the number of instructions
per program, CISC processors incorporate specialized hardware for
complex operations, making them particularly efficient for certain
computing tasks. Prominent examples include Intel's x86 and AMD
processors, which power most modern personal computers and
servers.

CISC (Complex Instruction Set Computer) Characteristics

CISC architectures are designed to provide a rich set of instructions that

closely align with high-level programming constructs, simplifying compiler
design and improving code density. CISC architectures prioritize flexibility,
rich instruction sets, and memory access at the cost of hardware
complexity and power efficiency.

1. Large and Complex Instruction Set

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  Wide variety of instructions (typically 100–250).
 Includes multi-step operations (e.g., single instructions for string
manipulation, polynomial evaluation).
 Some instructions are highly specialized (e.g., ENTER/LEAVE for
stack frame management in x86).
 Macro-like operations (e.g., a single instruction may perform
memory load, arithmetic, and store).

2. Multiple Addressing Modes (5–20 Varieties)

CISC supports flexible operand access methods, including:

 Register Direct (ADD R1, R2)

 Memory Direct (MOV AX, [0x1234])
 Indexed Addressing (MOV AX, [BX+SI+10])
 Indirect Addressing (MOV AX, [BX])
 Base+Displacement (MOV AX, [BP-4])
 Immediate (MOV AX, #42)
 Auto-increment/Decrement (MOV AX, [BX+])

Impact:

 Simplifies compiler code generation.

 Increases hardware complexity due to multiple decoding paths.

3. Variable-Length Instruction Encoding

 Instructions can range from 1 byte to over 10 bytes (e.g., x86

instructions).
 Prefix bytes modify instruction behavior (e.g., operand size, locking).
 Complex decoding logic required to parse instruction boundaries.

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Disadvantage:

 Inefficient pipelining due to irregular instruction lengths.

 Requires additional hardware (e.g., instruction length decoders).

4. Memory-Based Operations

 ALU operations can directly access memory (e.g., ADD [MEM],

AX).
 Supports complex memory operands (e.g., MUL [BX+DI], CL).
 Multi-memory operands per instruction (e.g., MOV [DST], [SRC] in
some CISC designs).

Advantage:

 Reduces register pressure (fewer load/store instructions).

 Improves code density.

Disadvantage:

 Slower execution (memory accesses are slower than register

operations).
 Higher power consumption (memory operations are energy-
intensive).

5. Microcoded Control Unit

 Complex instructions are broken into micro-operations (µops).

 Microprogram ROM stores sequences for each instruction.
 Allows backward compatibility (new instructions can be added via
microcode updates).

Disadvantage:

 Slower than hardwired logic (extra fetch/decode steps for

microcode).

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6. Hardware-Managed Complexity

 Out-of-order execution (in modern CISC CPUs like x86).

 Branch prediction (to mitigate pipeline stalls).
 Speculative execution (executing instructions before branches are
resolved).

Impact:

 Helps mitigate inefficiencies caused by CISC’s irregular instruction set.

 Increases power consumption and die size.


7. Backward Compatibility Emphasis

 Legacy support (e.g., x86 still supports 16-bit real mode).

 Instruction set extensions (MMX, SSE, AVX) add complexity.

Example:

 Modern x86 CPUs decode CISC instructions into RISC-like µops for
efficiency.

8. Compiler-Friendly Design (Originally)

 Goal: One machine instruction per high-level statement.

 Example: CALL instruction handles stack frame setup/teardown.
 Modern reality: Compilers often avoid complex CISC instructions for
optimization.

REDUCED INSTRUCTION SET COMPUTER (RISC) ARCHITECTURE

employs a smaller set of simple, atomic instructions that use fixed-length
formats and primarily focus on register-based operations. Following a load-
store architecture where memory access occurs only through specific

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instructions, RISC processors are optimized for single-cycle instruction
execution, enabling faster and more power-efficient performance. This
design approach is exemplified by processors like ARM, RISC-V, and MIPS,
which dominate mobile devices and embedded systems due to their
efficiency and simpler hardware design

RISC design philosophy

 RISC is a design philosophy aimed at delivering simple but

powerful instructions that execute within a single cycle at a
high clock speed.
 The RISC philosophy concentrates on reducing the complexity of
instructions performed by the hardware.
 The RISC philosophy provides greater flexibility and intelligence in
software rather than hardware.
 RISC design places greater functionality to the compiler rather
than the hardware.

THE RISC PHILOSOPHY IS IMPLEMENTED WITH FOUR MAJOR

DESIGN RULES/PRINCIPLES

1. Instructions: RISC has a reduced number of instruction classes.

These classes provide simple operations so that each is executed
in a single cycle. The compiler synthesizes complicated operations
by combining several simple instructions. Each instruction is a
fixed length to allow the pipeline to fetch future instructions before
decoding the current instruction.
2. Pipeline: The processing of instructions is broken down into
smaller units that can be executed in parallel by pipelines. The
pipeline advances by one step on each cycle for maximum
throughput.
3. Register: RISC machines have a large general-purpose register
set. Any register can contain either data or an address. Registers

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 act as the fast local memory store for all data processing
operations. The purpose is to prevent in large amounts of
interactions with memory
4. Load-store architecture: The processor operates on the data
held in registers. Separate load and store instructions transfer data
between the register bank and external memory.

RISC (REDUCED INSTRUCTION SET COMPUTER) CHARACTERISTICS

RISC architectures emphasize simplicity, speed, and efficiency by

reducing instruction complexity and relying on optimized hardware design.

1. Small and Simple Instruction Set

 Fewer instructions (typically 50–120, compared to CISC’s 100–250).

 Each instruction performs a single, atomic
operation (e.g., ADD, LOAD, STORE).
 No complex multi-step instructions (e.g., no "string copy" or
"polynomial evaluate" in hardware).
 Uniform instruction encoding simplifies decoding.

effect
✔ Easier pipelining (fewer edge cases).
✔ Faster decode/execute stages.

2. Limited Addressing Modes (Mostly Register-Based)

RISC minimizes addressing modes to reduce hardware complexity:

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  Register-direct (ADD R1, R2, R3).
 Immediate (ADDI R1, R2, #10).
 Base+Offset (LW R1, 8(R2) for memory access).
 PC-relative (for branches, e.g., BEQ R1, R2, label).

Impact:
✔ Simplifies instruction decoding.
✔ Encourages efficient register usage.

3. Load-Store Architecture (Memory Access Only via LOAD/STORE)

 All computations happen in registers (no ADD [MEM], R1).

 Explicit LOAD/STORE instructions for memory access.
 Reduces memory bottlenecks (registers are faster).

effect
✔ Faster execution (register operations take 1 cycle).
✔ Easier pipelining (no memory delays in ALU ops).

4. Fixed-Length Instruction Encoding

 All instructions are the same size (typically 32-bit or 64-bit).

 Simplifies instruction fetch & decode (no variable-length parsing).
 Aligned to word boundaries (improves cache efficiency).

effect
✔ Predictable fetch/decode (better for pipelining).
✔ No wasted cycles on instruction alignment.

5. Single-Cycle Execution (For Most Instructions)

 Basic ALU operations (ADD, SUB, AND, OR) complete in 1 cycle.

 Only LOAD/STORE may take multiple cycles (due to memory
latency).
 Hardwired control (no microcode delays).

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Impact:
✔ Higher instructions per clock (IPC) than CISC.
✔ Enables efficient pipelining.

6. Hardwired Control (Not Microprogrammed)

 No microcode ROM (instructions execute directly in hardware).

 Faster than CISC (avoids microcode lookup overhead).
 Less flexible (harder to add new instructions).

effect
✔ Faster execution.

7. Large Register File (Minimizes Memory Access)

 More general-purpose registers (GPRs) than CISC (typically 16–

32).
 Register windows (in some ISAs like SPARC) speed up function calls.
 Reduces LOAD/STORE traffic (more data stays in registers).

effect
✔ Faster than memory access (registers have zero latency).

8. Efficient Pipelining (One Instruction per Clock Cycle)

 Deep pipelines (5–15 stages in modern RISCs).

 Superscalar execution (multiple instructions per cycle).
 Branch prediction (to avoid pipeline stalls).

effect:
✔ Near 1 IPC (instruction per cycle) in optimal cases.

9. Compiler-Centric Design

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  Relies on compiler optimizations (software handles instruction
scheduling).
 No complex hardware workarounds (unlike CISC’s out-of-order
execution).
 Encourages "RISC philosophy" in code generation.

effect:
✔ More efficient than CISC for optimized code.

RISC vs. CISC: Key Differences

CISC (Complex
RISC (Reduced Instruction
Feature Instruction Set
Set Computer)
Computer)

Instruction Large (100–250

Small (50–120 instructions)
Set Size instructions)

Instruction Complex (multi-step, Simple (single-cycle atomic

Complexity macro-like ops) ops)

Many (5–20 modes, Few (mostly

Addressing
e.g., memory-indirect, register/immediate/base+offset
Modes
indexed) )

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 CISC (Complex
RISC (Reduced Instruction
Feature Instruction Set
Set Computer)
Computer)

Memory Direct (ALU ops can Load-Store only (registers for

Access use memory operands) computation)

Instruction Variable-length (1–10+ Fixed-length (typically 32/64-

Encoding bytes) bit)

Execution Multi-cycle (some Mostly single-cycle (except

Cycles complex instructions) load/store)

Microprogrammed
Control Unit Hardwired (direct execution)
(uses microcode ROM)

Register File Fewer GPRs (8–16) More GPRs (16–32+)

Lower (variable
Pipelining Higher (fixed-length,
lengths, complex
Efficiency predictable flow)
decoding)

Tries to map HLL

Relies on compiler for
Compiler Role statements to single
optimization
instructions

Power Higher power

Lower power consumption
Efficiency consumption

Backward Strong (e.g., x86 Minimal (clean-slate designs

Compatibility supports legacy like RISC-V)

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 CISC (Complex
RISC (Reduced Instruction
Feature Instruction Set
Set Computer)
Computer)

modes)

Modern x86 (Intel/AMD), IBM

ARM, RISC-V, MIPS, SPARC
Examples zSeries

ARM
ARM stands for Advanced RISC Machine. It refers to a family of Reduced
Instruction Set Computing (RISC) processor architectures that are known for
their low power consumption, high performance, and compact size,
making them ideal for embedded and portable devices. ARM processors
are designed and licensed by ARM Holdings, a British semiconductor and
software design company.

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Description and Key Features:

 RISC Architecture: ARM processors are based on the RISC (Reduced

Instruction Set Computer) design principle, which simplifies the
instruction set, allowing for faster execution and lower energy use
compared to Complex Instruction Set Computing (CISC) architectures.
 Licensing Model: ARM Holdings does not manufacture chips directly
but licenses the architecture and core designs (e.g., ARM7, ARM9,
ARM11) to semiconductor companies like Qualcomm, Samsung,
Broadcom, and Texas Instruments. This has made ARM one of the most
widely used processor cores in the world.
 Market Dominance: By 2009, ARM processors accounted for
approximately 90% of all 32-bit embedded RISC processors,
showcasing their dominance in the embedded systems market.

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  Power Efficiency: One of the most critical advantages of ARM
processors is their low power consumption, making them especially
suitable for portable electronics such as:
o PDAs (Personal Digital Assistants)
o Cell phones
o Handheld game consoles
o Multimedia players
o Digital TVs and cameras

ARM DESIGN PHILOSOPHY PRINCIPLES

1. Simplicity and Efficiency (RISC Design)

 ARM uses a reduced set of instructions that execute in a single

clock cycle.
 Fewer instructions mean simpler hardware, faster execution, and lower
power consumption.
 In contrast to complex instruction sets like x86, ARM uses fewer, more
optimized instructions which reduce processing time and heat.

2. Power Efficiency

 ARM designs are optimized for low power consumption, making

them ideal for battery-powered devices.
 Use of techniques like clock gating, dynamic frequency scaling,
and sleep modes to save power.
 Smartphones use ARM processors to balance performance with
long battery life.

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3. Modularity and Scalability

 ARM architecture allows for customization and scalability,

supporting a wide range of devices from IoT sensors to servers.
 Licensees (e.g., Qualcomm, Apple) can adapt the core design to meet
specific performance or power needs.

4. High Performance per Watt

 ARM focuses on delivering maximum performance with minimal

energy use, rather than raw performance alone.
 Apple’s M-series chips (M1, M2) deliver powerful computing
performance using ARM architecture while maintaining excellent
energy efficiency.

5. Load/Store Architecture

 Only load and store instructions access memory; all other

operations occur between registers.
 This improves the predictability and performance of instruction
execution.
 Arithmetic operations (like add, subtract) are performed on registers,
reducing memory access delays.

6. Conditional Execution

 Most ARM instructions can be executed conditionally, reducing the

need for branches and improving pipeline efficiency.
 Avoiding performance losses due to frequent branching in control-
heavy code like loops and conditionals.

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Applications of ARM Architecture

Application
Real-Life Example Description
Area

Use ARM-based processors

Samsung Galaxy,
(Exynos, Snapdragon, Apple
Smartphones iPhone (A-series
Silicon) for performance and
chips)
battery life.

ARM Cortex-M series used in low-

Embedded Automotive ECUs,
power, real-time embedded
Systems Smart Thermostats
controllers.

Smart home devices,

ARM processors manage sensors
IoT Devices fitness trackers (e.g.,
and communications efficiently.
Fitbit)

High-performance, low-power
Apple MacBooks with
Laptops/PCs computing using ARM
M1/M2/M3 chips
architecture.

Routers and modems

ARM used for packet processing
Networking (e.g., from Cisco,
and communication protocols.
Netgear)

Smartwatches like
ARM cores optimize power and
Wearables Apple Watch,
space.
Samsung Gear

Drones & Use ARM processors for real-time

DJI drones
Robotics control and image processing.

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REASONS WHY ARM DOMINATES MODERN COMPUTING

ARM (Advanced RISC Machines) has become the most widely used processor
architecture in the world, powering everything from smartphones to
supercomputers.

1. Unmatched Power Efficiency

Best Performance per Watt

 ARM’s RISC design minimizes power consumption while maintaining

high performance.

Ideal for Battery-Powered Devices

 Smartphones, tablets, and wearables rely on ARM for long battery life.

Advanced Power Management

 Features like big.LITTLE, DVFS (Dynamic Voltage & Frequency

Scaling), and power gating optimize energy use.

2. Scalability & Flexibility

From Tiny IoT to Supercomputers

 ARM designs scale from ultra-low-power Cortex-M (microcontrollers)

to high-performance Cortex-A (smartphones)
and Neoverse (servers).

Customizable Cores

 Companies like Apple, Qualcomm, and Samsung license ARM designs

and customize them.

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Heterogeneous Computing

 ARM supports big.LITTLE, mixing high-power & efficiency cores for

optimal workload handling.

3. Cost-Effectiveness

Licensing Model (ARM Doesn’t Manufacture Chips)

 Companies pay to use ARM designs but avoid costly fabrication.

Lower Silicon Area = Cheaper Chips

 RISC’s simplicity means smaller dies → higher yields and lower costs.

4. High Performance Without High Clock Speeds

Efficient Execution (Higher IPC)

 ARM does more work per clock cycle, reducing the need for high
frequencies (which consume exponentially more power).

Massive Multi-Core Designs

 ARM scales well with many cores (e.g., 128+ cores in server chips).

5. Software & Ecosystem Advantages

Dominant in Mobile (Android & iOS)

 99% of smartphones run on ARM (Apple, Qualcomm, Samsung,

MediaTek).

Growing in PCs & Servers

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  Windows on ARM (Snapdragon X Elite) and macOS (Apple Silicon) are
challenging x86.

Cloud & Data Center Adoption

 AWS Graviton, Ampere Altra, and Google’s ARM servers reduce data
center power costs.

TECHNOLOGICAL SHIFTS FROM CISC TO RISC & REASONS BEHIND

THE TRANSITION

Key Shifts:

1. Instruction Set Simplification

o CISC: Complex, multi-step instructions (e.g., REP MOVSB for

string copy).
o RISC: Atomic, single-cycle instructions (e.g., ADD, LOAD).
2. Fixed-Length Instructions

o CISC: Variable-length (x86: 1–15 bytes).

o RISC: Fixed-length (ARM/RISC-V: 32-bit).
3. Load-Store Architecture
o CISC: Memory operands allowed in most instructions.
o RISC: Only LOAD/STORE access memory.
4. Hardwired Control

o CISC: Microcoded execution (slow).

o RISC: Hardwired logic (fast, low power).
5. Pipelining & Parallelism

o CISC: Irregular pipelines (due to variable instructions).

o RISC: Deep, efficient pipelines (5–15 stages).
6. Focus on Compiler Optimization

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 o CISC: Hardware handles complexity.
o RISC: Compiler generates optimized instruction sequences.

Reasons for Transition:

 Performance: RISC’s simpler design enables higher clock speeds and

IPC.
 Power Efficiency: Critical for mobile/embedded devices (ARM
dominates smartphones).
 Cost: RISC chips are cheaper to design/manufacture.
 Scalability: RISC’s modularity suits multicore/SIMD designs (e.g.,
Apple M-series).

HYBRID PROCESSORS: COMBINING RISC & CISC

How Hybrid Designs Work:

1. CISC Frontend (x86)

o Maintains backward compatibility.

o Decodes complex CISC instructions into RISC-like µops (micro-
operations).
2. RISC Backend (Execution Core)

o Processes µops in a pipelined, superscalar fashion.

o Uses load-store principles internally.

Real-World Example: Intel x86 (Since Pentium Pro, 1995)

 CISC Layer: x86 instructions (e.g., ADD [MEM], REG).

 RISC Core: Breaks instructions into µops (e.g., LOAD MEM → REG, ADD
REG → REG).
 Benefits:

o Retains x86 software compatibility.

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 o Gains RISC-like execution efficiency.

Impact:

 Modern x86 CPUs (Intel Core, AMD Ryzen) outperform pure CISC
designs by translating to RISC internally.
 ARM’s hybrid approach (e.g., Cortex-X for performance, Cortex-A for
efficiency).

Why Hybrid?

 Legacy Support: x86 must run decades of software.

 Performance: RISC cores execute µops faster than native CISC.
 Flexibility: Balances complexity and efficiency.

CONTRIBUTION OF RISC DESIGN TO POWER EFFICIENCY AND

ENERGY SAVINGS IN MOBILE DEVICES

The Reduced Instruction Set Computing (RISC) architecture, which

underpins ARM processors, plays a crucial role in making mobile devices
(smartphones, tablets, wearables) energy-efficient. Here’s how RISC design
principles directly contribute to power savings:

1. Simplified Instruction Set → Lower Power Consumption

 Fewer, Fixed-Length Instructions:

o RISC uses a small set of simple, uniform instructions (e.g., 32-bit

fixed length in ARM).
o Unlike Complex Instruction Set Computing (CISC), which has
variable-length instructions, RISC reduces decoding complexity,
saving power.
o Example: ARM’s ADD, SUB, LDR (load), and STR (store) are
optimized for minimal hardware overhead.
 Load-Store Architecture:
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 o Only load and store instructions access memory; computations
use registers.
o Reduces memory accesses (which are power-hungry) and
minimizes wasted cycles.
o Example: In an ARM CPU, LDR R1, [R2] loads data into a register
before computation, avoiding repeated memory fetches.

2. Efficient Pipelining → Higher Performance per Watt

 Pipelining-Friendly Design:

o RISC’s simple instructions allow deep, efficient pipelining

(breaking tasks into stages).
o Fewer pipeline stalls (compared to CISC) mean fewer wasted
clock cycles → less dynamic power.
o Example: ARM Cortex-A7x CPUs use 10+ stage pipelines for
high throughput without excessive power draw.
 Lower Clock Speeds for Same Performance:

o Since RISC executes more instructions per cycle (IPC), it doesn’t

need high clock speeds (which exponentially increase power
consumption).
o Example: Apple’s M-series chips outperform x86 CPUs at lower
frequencies (e.g., M2 at 3.5 GHz vs. Intel at 5 GHz).

3. Smaller Die Size → Less Static Power Leakage

 Compact, Optimized Hardware:

o RISC cores require fewer transistors than CISC (e.g., x86),

reducing silicon area.
o Smaller dies → lower leakage current (static power loss when
idle).
o Example: ARM Cortex-M0+ (for IoT) uses just 12,000 gates,
minimizing leakage.

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  Better for Mobile Process Nodes:

o RISC’s simplicity scales well with advanced fabrication (5nm,

3nm), where leakage is a major concern.
o

4. Advanced Power Management Features

 Dynamic Voltage & Frequency Scaling (DVFS):

o RISC’s predictable workloads allow fine-grained power

adjustments.
o Example: ARM big.LITTLE shifts tasks between high-power
(Cortex-X) and low-power (Cortex-A5xx) cores.
 Power Gating & Sleep States:

o Unused CPU sections can be turned off completely (e.g.,

ARM’s TrustZone for secure sleep modes).

5. Software Optimization → Less Work, Less Energy

 Compiler-Friendly Design:

o RISC’s regularity makes it easier for compilers to generate

efficient code (fewer redundant operations).
o Example: Android’s ART runtime optimizes ARM machine code
for better battery life.
 Reduced Overhead from Complex Instructions:

o No microcode translation (unlike x86), saving decode power.

REVIEW QUESTIONS

SECTION A: Microprocessor Basics and Instruction Set Architecture

(ISA)

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 1. Discuss the significance of the instruction set, word length, and system
clock speed in determining the performance of a microprocessor.
Illustrate your answer with relevant examples.
2. Explain the concept of Instruction Set Architecture (ISA) and its role as
a hardware-software interface. How does the ISA influence system
performance, power efficiency, and compatibility across platforms?
3. Critically evaluate how ISA determines processor design decisions with
respect to processor complexity, performance characteristics, power
efficiency, and cost of implementation. Use examples such as RISC-V,
ARM, and x86 to support your arguments.

SECTION B: CISC and RISC Architectures

4. Compare and contrast the CISC (Complex Instruction Set Computer)

and RISC (Reduced Instruction Set Computer) architectures based on
their instruction sets, addressing modes, instruction encoding,
execution cycles, and compiler design. Provide real-world processor
examples to support your discussion.
5. Describe the architectural and operational features that make RISC
processors more power-efficient than their CISC counterparts. In your
explanation, include aspects like instruction encoding, pipeline design,
and load-store architecture.
6. Explain the purpose and mechanism of microcoded control in CISC
architectures. What are the advantages and disadvantages of this
approach compared to hardwired control in RISC processors?

SECTION C: ARM Architecture and Its Global Significance

7. Analyze the ARM design philosophy by explaining its key principles,

such as simplicity, power efficiency, modularity, and conditional

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 execution. How do these principles contribute to ARM’s dominance in
mobile and embedded systems?
8. Discuss five real-life application areas where ARM processors are
widely used. For each application, explain how ARM’s features make it
a suitable choice over alternative processor architectures.
9. ARM processors are known for their high performance per watt.
Discuss the various architectural strategies and design features that
ARM employs to achieve this efficiency.

SECTION D: Industry Trends and Hybrid Architectures

10. Examine the key technological shifts that led to the global
transition from CISC to RISC processor architectures. What were the
primary drivers behind this transition, and how did it impact mobile
and embedded system design?
11. With reference to modern hybrid processors like Intel's x86 and
Apple’s ARM-based M-series chips, explain how combining CISC and
RISC features in a single processor design benefits system
performance and legacy support.
12. Evaluate how RISC design contributes to energy savings in
mobile devices. Your answer should include a discussion on instruction
simplicity, pipelining, power management features, and compiler
optimization.

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