Department of Electronics and Communication Engineering

23AD311 -Digital Principles and Computer Organization

Lab Manual
SYLLABUS

1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of encoder and decoder circuits
5. Implementation of functions using Multiplexers.
6. Implementation of the synchronous counters
7. Implementation of a Universal Shift register.
8. Simulator based study of Computer Architecture
 LIST OF EXPERIMENTS

CYCLE I

1. Verification of Boolean theorems using logic gates.

2. Design and implementation of combinational circuits using gates.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of encoder and decoder circuits
5. Implementation of functions using Multiplexers.
6. Implementation of the synchronous counters
7. Implementation of a Universal Shift register.
8. Simulator based study of Computer Architecture

CONTENT BEYOND THE SYLLABUS

1. Design of decade counter.

2. Design combinational circuit by using HDL Program.
EX. NO: 1(a) STUDY OF LOGIC GATES
DATE :

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:
S. No. COMPONENT SPECIFICATION QTY
1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each
gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level when
any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when both
the inputs are low.

NOT GATE:

The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both inputs
are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs
are low. The output is low when one or both inputs are high.

X- OR GATE:
The output is high when any one of the inputs is high. The output is low when
both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
AND GATE:

SYMBOL: PIN DIAGRAM:

OR GATE:
NOT GATE:

SYMBOL: PIN DIAGRAM:

X-OR GATE :

SYMBOL : PIN DIAGRAM :

2- INPUT NAND GATE:

SYMBOL: PIN DIAGRAM:

3- INPUT NAND GATE :

NOR GATE:

APPLICATIONS:
 Logic gates are the basic building blocks of digital systems. Each gate has
individual applications.
 Wherever the occurrence of any one/more than one event is needed to be detected
or some actions are to be taken after their occurrence, in all those cases OR gates
can be used. Suppose in an industrial plant if one or more than one parameter
exceeds the safe value, some protective measure is needed to be done by using OR
gates.
 AND gate as enable gate and Inhibit gate. Enable gate means allowance of data
through a channel and Inhibit gate is just the reverse of that process i.e.
disallowance of data through a channel.
 Ex-OR, Ex-NOR gates are used in generation of parity generation and checking
units. NOT gates are also known as inverter because they invert the output given to
them and show the reverse result. It can be used in CMOS inverters

RESULT:

Thus the study of logic gates was verified.

EX. NO: 1(b) VERIFICATION OF BOOLEAN THEOREMS
USING LOGIC GATES
DATE :

AIM:
To verify the boolean theorems using digital logic gates.

APPARATUS REQUIRED:

S. No. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NOR GATE IC 7402 1
5. IC TRAINER KIT - 1
6. PATCH CORD - 14

THEORY:

The construction of the Boolean algebra is entirely based upon certain

fundamental law and theorems which are must used in the multiplication of Boolean
expressions. Each of these rules is formulated by using the basic Boolean operations, and
can be verified either algebraically or by using the truth table method of perfect induction
in which we provide 0 and 1 values of each variable in the expression.
The laws of Boolean algebra can be divided into three groups with each
law expressed in a dual pair, i.e,. logical sum and logical product. The first group
contains the three laws called commutative, associative and distributive laws. The second
group contains four basic identities and a law of double complementation. The laws in
the third group are not basic, but derived from these laws, there are 2 theorems also
which are called de-morgans theorems.

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C
3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

(A’)’ = A

6. Idempotent Law
1. A+A = A
2. A.A = A

7. Complementary Law
1. A+A' = 1
2. A.A' = 0

8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the individual
complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B

9. Consensus Theorem
Consensus theorem is used to simplify the Boolean expression by eliminating the
redundant terms.
AB+A'C+BC = AB+A'C
Proof: AB+A'C+BC = AB+A'C+BC (A+A')
= AB+A'C+ABC+A'BC
= AB (1+C) + A'C(1+B)
= AB+A'C (using OR law, 1+C=1 and 1+B=1)

PROCEDURE:

1. Connect the 14th pin of IC to the supply and the 7 th pin to the ground.
2. Connect the input of the gates to logic switches.
3. Connect the output of the gates to LED through a resistor.
4. Switch ON the power supply.
5. Check the truth tables of different gates for various inputs. If LED is glowing,
then the output is ‘1’. If it is not glowing, then the output is ‘0’
6. Switch OFF the power supply.
 COMMUTATIVE LAW:

A+B = B+A

A A+B B B+A
B A

TRUTH TABLE:

A B A+B B+A
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1

ASSOCIATIVE LAW:

A+(B+C) = (A+B)+C
A


A

A+(B+C)
B

C C (A+B)+C

TRUTH TABLE:

A B C A+(B+C) (A+B)+C
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1
DISTRIBUTIVE LAW:

A+(B.C) = (A+B).(A+C)

TRUTH TABLE:

A B C A(B+C) AB+AC
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

DE-MORGAN’S THEOREM:

(A+B)’ = A’.B’

TRUTH TABLE:

A B (A+B)’ A’B’
0 0 1 1
0 1 0 0
1 0 0 0
1 1 0 0
ABSORPTION LAW

A+AB = A TRUTH TABLE:

A B Y=A+AB
0 0 0
0 1 0
1 0 1
1 1 1

INVOLUTION (OR) DOUBLE COMPLEMENT LAW

TRUTH TABLE:

(A’)’ = A A A’ Y=(A’)’
0 1 0
1 0 1

IDEMPOTENT LAW

i) A+A = A TRUTH TABLE:

A A Y=A+A
0 0 0
1 1 1

ii) A.A = A TRUTH TABLE:

A A Y=A.A
0 0 0
1 1 1

RESULT:

Thus the boolean theorems using digital logic gates was verified.
 EX NO: 2 DESIGN AND IMPLEMENTATION OF COMBINATIONAL
CIRCUITS USING GATES
DATE:

AIM:
To design the logic circuit and verify the truth table of the given Boolean
expression, F (A,B,C,D) = Σ (0, 1, 2, 5, 8, 9, 10). [Design can be changed by changing
the Boolean expression]

APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 3
2. OR GATE IC 7432 2
3. NOT GATE IC 7404 4
4. EX-OR GATE IC 7486 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 27

K-MAP SIMPLIFICATION:

Given , F (A,B,C,D) = Σ (0,1,2,5,8,9,10)

The output function F has four input variables hence a four variable Karnaugh Map is
used to obtain a simplified expression for the output as shown,

From the K-Map,

F = B’ C’ + D’ B’ + A’ C’ D
Since we are using only two input logic gates the above expression can be re-written as,
F = C’ (B’ + A’ D) + D’ B’
Now the logic circuit for the above equation can be drawn.
CIRCUIT DIAGRAM:

TRUTH TABLE:
PROCEDURE:

1. Connections are given as per the circuit diagram

2. For all the ICs 7th pin is grounded and 14th pin is given +5 V supply.
3. Apply the inputs and verify the truth table for the given Boolean expression.

APPLICATIONS:
 Boolean theorems are used to simplify various digital logic circuits. It is dealing
with 0’s and 1’s. It is very useful in the field of data transmission.
 The entire arithmetic operations can be easily done. It can be used to check the
operations of logic gates.

RESULT:
Thus the design of logic circuit and truth table of the given Boolean
expression was verified.
EX NO: 3 IMPLEMENTATION OF 4-BIT BINARY ADDER/SUBTRACTOR
CIRCUITS
DATE :

AIM:
To design and implement 4-bit adder and subtractor using IC 7483.

APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY.
1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output
carry from each full adder connected to the input carry of next full adder in chain. The
augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from
right to left, with subscript 0 denoting the least significant bits. The carries are connected
in chain through the full adder. The input carry to the adder is C0 and it ripples through
the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry C0
must be equal to 1 when performing subtraction.
4 BIT BINARY ADDER/SUBTRACTOR:
The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit
is adder circuit. When M=1, it becomes subtractor.

PROCEDURE:
(i) Connections were given as per circuit diagram.
(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.
PIN DIAGRAM FOR IC 7483:

LOGIC DIAGRAM:
4- BIT BINARY ADDER

LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR
 LOGIC DIAGRAM:
4- BIT BINARY ADDER/SUBTRACTOR

APPLICATIONS:
 Adders/subtractors mainly for arithmetic operations in digital systems. Binary
adder subtractor is a single circuit that is capable of adding and subtracting
numbers.
 A full adder can be converted into a full subtractor by complementing the input
before applying it and a gate for generating carry. When the control input to the
circuit is zero the circuit serves as a binary subtractor.

RESULT:
Thus the design and implementation of 4-bit adder and subtractor using IC 7483 was
verified
EX NO: 4 IMPLEMENTATION OF ENCODER AND DECODER
DATE:

AIM:
To design and implement an encoder and decoder circuits using logic gates

APPARATUS REQUIRED:

S.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P NAND GATE IC 7410 2
2. OR GATE IC 7432 3
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 27

THEORY:
ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates the
binary code corresponding to the input value. In octal to binary encoder it has eight
inputs, one for each octal digit and three output that generate the corresponding binary
code. In encoder it is assumed that only one input has a value of one at any given time
otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the
outputs are zero. The zero outputs can also be generated when D0 = 1.

DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded
input into coded output where input and output codes are different. The input code
generally has fewer bits than the output code. Each input code word produces a different
output code word i.e there is one to one mapping can be expressed in truth table. In the
block diagram of decoder circuit the encoded information is present as n input producing
2n possible outputs. 2n output values are from 0 through out 2n – 1.
LOGIC DIAGRAM FOR ENCODER:
TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1

LOGIC DIAGRAM FOR DECODER:

TRUTH TABLE:
INPUT OUTPUT
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
APPLICATIONS:

 An encoder is a device, circuit, transducer, software program, algorithm or person

that converts information from one format or code to another, for the purposes of
standardization, speed, secrecy, security or compressions.
 An audio encoder may be capable of capturing, compressing and converting
audio. A video encoder may be capable of capturing, compressing and converting
audio/video. An email encoder secures online email addresses from email
harvesters
 A decoder is a device which does the reverse operation of an encoder, undoing the
encoding so that the original information can be retrieved. The same method used
to encode is usually just reversed in order to decode. Decoding is necessary in
applications such as data multiplexing, 7 segment display and memory address
decoding.

RESULT:

Thus the design and implementation of an encoder and decoder circuits using logic
gates was verified.
EX NO: 5
DATE: IMPLEMENTATION OF FUNCTION USING MULTIPLEXER

AIM:
To design and implement multiplexer using logic gates and verify the truth table.

APPARATUS REQUIRED

S.No. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
5. PATCH CORDS - 32

THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that
selects binary information from one of many input lines and directs it to a single output
line. The selection of a particular input line is controlled by a set of selection lines.
Normally there are 2n input line and n selection lines whose bit combination determine
which input is selected.
A multiplexer is used in the generation of combinational logic functions in sum of
product form. When used in this way, the device can replace discrete gates, can often
greatly reduce the number of ICs and can make design changes much easier.
MULTIPLEXER:
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
TRUTH TABLE:
S1 S0 Y = OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3

CIRCUIT DIAGRAM FOR MULTIPLEXER:

PROCEDURE:

1. Connections are given as per logical diagram.

2. Logical inputs are given as per logical diagram.
3. Observe the output and verify the truth table.

RESULT
Thus the design and implementation of multiplexer using logic gates and the truth table
was verified.
EX NO: 6 DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS
DATE: UP/DOWN COUNTER

AIM:
To design and implement 3 bit synchronous up/down counter.

APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. 3 I/P AND GATE IC 7411 1
3. OR GATE IC 7432 1
4. XOR GATE IC 7486 1
5. NOT GATE IC 7404 1
6. IC TRAINER KIT - 1
7. PATCH CORDS - 35

THEORY:
A counter is a register capable of counting number of clock pulse arriving at its
clock input. Counter represents the number of clock pulses arrived. An up/down counter
is one that is capable of progressing in increasing order or decreasing order through a
certain sequence. An up/down counter is also called bidirectional counter. Usually
up/down operation of the counter is controlled by up/down signal. When this signal is
high counter goes through up sequence and when up/down signal is low counter follows
reverse sequence.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.
TRUTH TABLE :

K MAP
STATE DIAGRAM:

CHARACTERISTICS TABLE:

Q Qt+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0

LOGIC DIAGRAM:
APPLICATIONS:
 A synchronous counter has an internal clock, and the external event is used to
produce a pulse which is synchronized with this internal clock. Synchronous
counters are used in rotary shaft encoders.
 It can be used in Programmable Logic Controllers (PLC) as well as in semi-
automated parking lot gates

RESULT:

Thus the design and implementation of 3 bit synchronous up/down counter was
verified.
EX NO: 7 IMPLEMENTATION OF UNIVERSAL SHIFT REGISTER
DATE:

AIM:
To design and implement
(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY.
1. D FLIP FLOP IC 7474 2
2. OR GATE IC 7432 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip
flop is connected to the input of next flip flop of the register. Each clock pulse shifts the
content of register one bit position to right.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table

PIN DIAGRAM:
SERIAL IN SERIAL OUT:
TRUTH TABLE:

CLK Serial in Serial out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

LOGIC DIAGRAM:

SERIAL IN PARALLEL OUT:

TRUTH TABLE:
OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1
LOGIC DIAGRAM :

PARALLEL IN SERIAL OUT:

TRUTH TABLE:
CLK Q3 Q2 Q1 Q0 O/P
0 1 0 0 1 1
1 0 0 0 0 0
2 0 0 0 0 0
3 0 0 0 0 1

LOGIC DIAGRAM:

PARALLEL IN PARALLEL OUT:

TRUTH TABLE:
DATA INPUT OUTPUT
CLK DA DB DC DD QA QB QC QD
1 1 0 0 1 1 0 0 1
2 1 0 1 0 1 0 1 0
LOGIC DIAGRAM :

RESULT:

Thus the design and implementation of SISO,SIPO,PIPO,PISO was verified.

 EX NO: 8 SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE
DATE:

Aim:

To study the simulator based computer architecture

THEORY:

Computer architecture is one of the important subjects offered at universities across the
world. Teaching in traditional way can be insufficient if the teaching focus is solely on the
textbook materials. One of the most critical aspects on teaching this discipline is how to support
the theoretical concepts of the subject with appropriate practical experience, usually organized as
laboratory experiments. But practically, students are unable to understand the subject. For this
reason, may educators have begin using different computer architecture simulators based on
hardware and software to solve this problem. There are mainly about three simulators: Logic sim,
CEDAR and CPT sim.

LOGISM:

Logisim is a simple software which can be used for implementing circuits with basic
gates. Users of this simulator can draw the circuits using the tool box available. The
circuit automatically propagates circuit values through the circuit by selecting the suitable tool
and the user can toggle the input conditions to learn how the circuit behaves in other situations.
Student themselves were able to understand how to connect basic gates to make simple as wll as
complex circuits with the help of Logisim.
CEDAR

CEDAR is a power simulator in which the student can implement a complete computer and will
be able to understand the internal details of a computer more clearly. Using CEDAR simulator
student can 1) build the entire computer hardware using fundamental logic gates; 2) write an
assembler to translate the test program into machine level program; 3) load the program into the
memory of the computer; and 4) run the test program on these hardware. After the
implementation students can see how a computer executes a program and what are the signals
generated during each clock pulse.
CPU Sim
CPU Sim is an interactive simulation tool in which the user can specify the details of the
CPU to be simulated, such as register set, of microinstructions, set of machine instructions and
set of assembly language instructions. Users of the tool can write their own machine or
assembly language program and run on the CPU they have created. It simulates the computer
architecture at register transfer level so that the students will get a better understanding about
the system. User of the simulator has to specify the hardware units and the microinstructions
for the CPU and then create the set of machine instructions. Corresponding to each machine
instruction a sequence of microinstructions is to be formed.

RESULT:
Thus the simulator based computer architecture was studied.
 CONTENTS BEYOND THE
SYLLABUS

EX NO: 1 Design of Decade Counter

DATE:

AIM:

To design and implement a decade counter.

APPARATUS REQUIRED:
S.No. COMPONENT SPECIFICATION QTY.
1. JK FLIP FLOP IC 7476 2
2. AND GATE IC 7400 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 35

Theory
The modulus for counters for counters is the number of unique states through which the
counter will sequence. The maximum possible number of states of a counter is 2 n, where n is the
number of flip flops in the counter. A decade counter with a count sequence of zero (0000) through
nine (1001) is a BCD decade counter because its ten-state sequence produces the BCD code. This type
of counter is useful in display applications in which BCD is required for conversion to a decimal
readout.

Procedure

1) Place the IC on IC Trainer Kit.

2) Connect VCC and ground to respective pins of IC Trainer Kit.
3) Connect the inputs to the input switches provided in the IC Trainer Kit.
4) Connect the outputs to the switches of output LEDs
5) Apply various combinations of inputs according to the truth table and observe condition
of LEDs
 Decade counter

Timing diagram

Truth Table
RESULT:

Thus the design and implementation a decade counter was verified

EX NO: 2 SIMULATION OF COMBINATIONAL CIRCUITS USING HDL
DATE:

AIM:
To write a verilog code for basic gates and combinational circuits.

TOOLS REQUIRED:
Xilinx ISE 12.1

THEORY:
Simulation is the discipline of designing a model of an actual or physical
system, executing the model on a digital computer, and analyzing the execution output.
For analysing digital systems, simulation tools are used. It can be done using HDL. It is
known as Hardware Description Language. HDL is a specialized computer language used
to program the structure, design and operation of electronic circuits, and most commonly,
digital logic circuits. The functioning of combinational circuits can be verified using
HDL.

PROGRAM:
AND gate
module andg(y,a,b);
output y;
input a,b;
and a1(y,a,b);
endmodule

OR gate
module org(y,a,b);
output y;
input a,b;
or r1(y,a,b);
endmodule

NOT gate
module notg(y,x);
output y;
input x;
not n1(y,x);
endmodule

NAND gate module

nandg(y,a,b);output y;
input a,b;
nand r1(y,a,b);
endmodule
NOR gate module
norg(y,a,b);output y;
input a,b;
nor r1(y,a,b);
endmodule

EX OR gate
module exor(y,a,b);
output y;
input a,b;
xor n1(y,a,b);
endmodule

EXNOR gate
module exnor(y,a,b);
output y;
input a,b;
xnor n1(y,a,b);
endmodule

Half Adder

module ha_rtl(s,c,a,b);
output s,c;
input a,b;
assign{c,s}=a+b;
endmodule

Full Adder

module fa(carry,sum,a,b,c);
output carry,sum;
input a,b,c;
reg sum,carry;
always@(a or b or c)
begin
sum =a^b^c;
carry =(a&b)|(a&c)|(b&c);
end
endmodule
Half subtractor

module half_sub(d,b,x,y);
output d,b;
input x,y;
assign d= x ^ y;
assign b= ~x & y;
endmodule

Full Subtractor

module full_sub(d,bout,x,y,bin);
output d,bout;
input x,y,bin;
assign d= x ^ y ^ bin;
assign b= (~x & y ) | (~x & bin) | (y & bin);
endmodule

RESULT
Thus the verilog code for basic gates and combinational circuits were

stimulated