Von Neumann Model (Processor Components)

Processor Components

1. Arithmetic and Logic Unit (ALU):

• The ALU performs arithmetic and logic operations in a program. Some computers have two ALUs:

one for fixed-point and one for floating-point calculations.

• Operations like multiplication and division use sequences of addition, subtraction, and bit-shifting.

For example, shifting 00110111 two places left to 11011100 is equivalent to multiplying by 4.

• The Accumulator (ACC) register temporarily stores results during ALU operations.
2. Control Unit (CU):

• The CU fetches instructions from memory, interprets them, and sends signals along the control bus

to coordinate other components. This ensures data flow and instructions are synchronized.

3. System Clock:

• The clock generates timing signals to keep components synchronized, preventing the system from

crashing.

4. Immediate Access Store (IAS):

• IAS (or primary memory/RAM) temporarily holds data and programs the CPU needs, speeding up

operations compared to slower backing storage.

• General Purpose Registers (GPRs):

• Store temporary data during program execution.

• Versatile and can be used for arithmetic, logic, or data transfer operations.

• Accessible by most instructions in a CPU’s instruction set.

• Often used to optimize performance by reducing memory access, Example: The ACC register.

• Special Purpose Registers (SPRs):

• Hold critical information like program status, control data, or memory addresses.

• Designed for specific tasks, such as managing execution flow or hardware configuration.

• Limited accessibility, often restricted to certain instructions.

• Ensure proper functioning of the CPU, such as tracking the next instruction or handling exceptions.

• Example: Program Counter (PC) for instruction sequencing.

Status Register Flag (SR):

The status register uses flags to indicate the results of arithmetic or logic operations:

• Carry Flag (C): Set if there’s a carry after addition.

• Negative Flag (N): Set if the result is negative.

• Overflow Flag (V): Set if an overflow occurs in arithmetic operations.

• Zero Flag (Z): Set if the result is zero.

FLags:

01 NV CZ
00 000 0 0
0 0
Adding two positive numbers gave a negative result, setting the Negative Flag to 1. This happens

because the result exceeded the positve number signed range, triggering the Overflow Flag to 1.
 Flags:
000 000
000
00 NVC. O 0 0
A carry was generated, setting the Carry Flag to 1, and a ninth-bit overflow occurred, setting the

Overflow Flag to 1.

System Buses

System buses are essential components in computers, facilitating parallel data transmission, with

each wire transmitting one bit. The three main types in the Von Neumann architecture are:
Address Bus:

• Carries addresses from the CPU to memory and is unidirectional (one-way), preventing addresses

from returning to the CPU.

• Its width is critical; for example, a 16-bit bus can address 65,536 memory locations, while a 32-bit

bus can address over 4 billion.

Data Bus:

• Bidirectional, allowing data to flow between the CPU, memory, and I/O devices.

• Its width determines the amount of data transported in one cycle (e.g., 16-bit, 32-bit, or 64-bit),

affecting overall performance.

Control Bus:

• Also bidirectional, it carries control signals from the control unit (CU) to other components and is

typically 8 bits wide.

• It works alongside the system clock, which synchronizes operations by defining clock cycles.

Higher clock speeds can improve processing speed (e.g., 3.5 GHz)

A -> control bus

B -> address bus

C -> data bus

1. Bus Width: Wider buses enhance performance by increasing the number of addressable locations

and data transmission capabilities.

2. Increase Clock Speed: Adjusting clock speeds in the BIOS boosts performance but risks instability

and overheating. For example, increasing from 2.1 GHz to 4 GHz doubles the CPU's performance,

enabling 4 billion F-E cycles per second instead of 2.1 billion.

3. Cache Memory: Faster than main memory, cache (using SRAM) improves performance by storing

frequently accessed data.

4. Multi-Core Processors: Multiple cores (each with an ALU, CU, and registers) can improve performance,

but adding cores doesn’t always double it. For example, dual-core processors share one communication

channel, and quad-core processors have more channels but still face overhead from managing communication

between cores.

Several factors limit the benefits of more cores:

• Communication Overhead: Managing communication between cores consumes time and reduces efficiency.

• Software Compatibility: Not all software is optimized for multi-core processing, leaving some cores idle.

• Memory Access: If memory speed doesn't match core speed, delays occur.

• Other Hardware Factors: Two computers with different configurations may perform differently:

1. One might have more RAM, enabling faster multitasking.

2. The other might have a dedicated GPU for enhanced parallel processing.
 Fetch-Execute Cycle

The fetch-execute cycle describes how a processor retrieves and executes instructions using buses

and registers. Here's a overview:

Fetch:

• The processor fetches the next instruction from the memory address indicated by the program

counter (PC).

• This address is copied to the memory address register (MAR) via the address bus.

• The instruction at that address is then transferred to the memory data register (MDR), and from

the MDR, it moves to the current instruction register (CIR).

• The PC is incremented to point to the next instruction.

Execute:

• The decoded instruction is executed by sending control signals to the appropriate components in

the computer system.

Register Transfer Notation (RTN) of Fetch exection cycle

The process can be represented in RTN as follows:

• MAR ← [PC]: Copies the contents of PC to MAR. #Loads 1000 to MAR

• PC ← [PC] + 1: Increments PC by 1. #ADD +1 in PC to 1000 <-- 1001

• MDR ← [[MAR]]: Loads data from the address in MAR into MDR. #First bracket loads 1000

then use 1000 as an address in memory and load 42 from memory

• CIR ← [MDR]: Copies data from MDR to CIR. #Copy 42 from MDR to CIR
990 30 0xAB1 000 0xEA2 1000
1000 42 0xAB1 00

1010 50 MDR CIR

1020 70 0aRT1 42 0xAW5 42

PC ooo
if wewrite MAR PC
Then MAR OXABI but with
MAR 4 000

Use of Interrupts in the Fetch-Execute Cycle

Interrupts enable efficient operation and multitasking in computers. Here’s how they function within

the fetch-execute cycle:

1. Interrupt Register:

A special register monitors interrupt signals during the fetch-execute cycle. If an interrupt occurs

(e.g., a fault while writing to a hard drive), a bit in this register changes status (e.g., from 0000 0000

to 0000 1000).

2. Checking Interrupts:

At the next cycle, the interrupt register is checked. If it indicates an active interrupt, the CPU

services it based on priority.

The CPU saves the current task's register contents and transfers control to the interrupt handler

(ISR).
3. Servicing the Interrupt:

After servicing the interrupt, the register is reset, and the previous task's register contents are

restored, allowing the CPU to resume from where it left off.

Overview of Interrupts

An interrupt is a signal that prompts the processor to pause its current task to handle the interrupt.

Causes include:

• Timing signals

• Input/output processes (e.g., a disk drive ready for data)

• Hardware faults (e.g., a printer jam)

• User interactions (e.g., pressing a key)

• Software errors (e.g., a missing .exe file)

Once received, the processor may continue or service the interrupt based on its type and priority.

Interrupts facilitate multitasking, allowing actions like downloading a file while playing music. When

servicing an interrupt, the processor saves the current task's status, executes the ISR, and then

restores the interrupted task’s status to continue processing.

Machine language, or machine code, is the simplest programming language, made of binary

instructions (0s and 1s) that a CPU directly understands.

Assembly Language

The first low level programming language to be developed was assembly language, this is closely

related to machine code. It uses:

Opcode (Operation Code): The part of a machine language instruction that specifies the operation

the CPU should perform (e.g., add, LDD, LDX). It tells the CPU what to do.

Operand: Part of an instruction that specifies the data or memory location the operation will act

upon. It tells CPU what to operate on, it include immediate values, registers, or memory addresses.

Label: A symbolic name used in assembly language to represent memory addresses or code

locations. Acts as a reference point for jumps or branches in the program (e.g., LOOP:). Simplifies

code readability and modification.

LDD Totals
opcode operand
Assembly language instructions

Data Movement Instructions Unconditional and conditional instructions

Input and output of

data instructions

Compare instructions

Arithmetic operation

instructions
Binary shifts

Logical Shift: Bits shifted out are replaced with 0s. Example: 10101111 left-shifted 3 places becomes

01111000.

Arithmetic Shift: Preserves the sign bit. Example: 10101111 right-shifted 3 places becomes 11110101.

Useful for multiplying/dividing by powers of 2.

• Right Arithmetic Shift: Divides by 2 for each shift, preserving the sign.

• Left Arithmetic Shift: Multiplies by 2 for each shift (similar to logical left shift).

Cyclic Shift: Bits shifted out re-enter at the opposite end. Example: 10101111 left-shifted 3 places

becomes 01111101.

Left Shift: Moves bits left; applies to all shift types.

Right Shift: Moves bits right; applies to all shift types.

Logical shifts in assembly language programming are LSL and LSR

AND (&): Use: Checks if a bit is set (i.e., checks if a particular bit is 1).

Example: Let's say we want to check if the 3rd bit is set (from the right).

A = 10101010 (binary) . B = 00000100 (binary, mask to check 3rd bit)

A & B = 00000000 (no bit is set at 3rd position, so result is 0).

If B was 00001000, the result would be 00001000, showing that the 4th bit is set.

OR (|): Use: Sets a bit to 1.

Example: Suppose we want to set the 2nd bit of A.

A = 10101010 (binary) B = 00000010 (binary, mask to set 2nd bit)

A + B = 10101010 | 00000010 = 10101010 (no change if the bit is already set). If the 2nd bit of A was 0, it would change to 1.

XOR (^): Use: Clears a bit that has been set (toggles the bit).

Example: Suppose we want to clear the 3rd bit of A.

A = 10101010 (binary) . B = 00000100 (binary, mask to toggle the 3rd bit)

A ^ B = 10101010 ^ 00000100 = 10101110 (clears the 3rd bit).

Summary of Effects:

1. AND: Check if the bit is set (bitwise 1 only if both are 1).

2. OR: Set a specific bit to 1 (bitwise 1 if either bit is 1).

3. XOR: Toggle a bit (changes it from 1 to 0 or from 0 to 1).

1. Single Pass Assembler: Translates assembly code directly into machine code in one go. The

machine code instructions are immediately placed into memory, ready to be executed.

2. Two Pass Assembler: Works in two stages, or "passes." The first pass generates a symbol

table, mapping labels to memory addresses, while the second pass generates the final machine

code. This method produces an object program that can be saved, loaded, and executed later. A

loader program may be required to load the object code into memory for execution.

Types of Addressing:

• Absolute/Direct Addressing: The operand's memory location contains the actual data. E.g., if memory

location 200 holds 20, then LDD 200 loads 20 into the accumulator. Absolute and direct addressing are the

same.

• Indirect Addressing: The operand's memory location contains an address, which points to the data. E.g., if

memory location 200 holds 20 and location 20 holds 5, then LDI 200 loads 5 into the accumulator.

• Indexed Addressing: Adds the index register (IR) value to the operand's address to locate data. E.g., if IR is 4

and memory location 204 holds 17, then LDX 200 loads 17 into the accumulator.

• Immediate Addressing: Uses the operand’s value directly. E.g., LDM #200 loads 200 into the accumulator.

• Relative Addressing: Adds the operand to the current address to find the next instruction. E.g., JMR #5 jumps

to the instruction 5 locations after the current one.

• Symbolic Addressing: Uses a label as a reference. E.g., if MyStore holds 20, then LDD MyStore loads 20 into

the accumulator.
USB (Universal Serial Bus) Ports

USB is a widely used standard for connecting devices to computers, known for its ease of use,

speed, and versatility.

Structure:

• 4 wires: 2 for power/ground, 2 for data signals.

Plug-and-Play:

• Device detected via data wire voltage change.

• Automatically identifies the device and loads the driver if available.

Pros:

• Automatic Detection: Devices are auto-configured.

• Correct Connection: Connectors fit only one way.

• Standardized: Widely supported across devices.

• Multiple Speeds: Different versions support varying data rates.

• Backward Compatibility: New versions work with older ones.

Cons:

• Speed Limit: Capped under 500 Mbps.

• Cable Length: Effective up to 5 meters.

• Obsolescence: Older standards (e.g., USB 1.1) may no longer be supported.

HDMI ports transmit high-definition audio and video from computers to HDMI-compatible devices,

replacing older VGA systems.

Key Features:

• High Definition: Supports HD resolutions (e.g., 1920 × 1080).

• Faster Refresh Rates: Typically 120Hz for smooth playback.

• Broad Color Range: Displays millions of colors for better quality.

• Bandwidth: Supports around 10 Gbps for high-quality transmission.

• Anti-Piracy: Includes HDCP protection to prevent unauthorized copying.

VGA (Video Graphics Array) Ports

• VGA was introduced in the late 1980s and has been largely replaced by HDMI in modern

applications. However, VGA ports are still used in some scenarios.

• Resolution and Color Limitations:

• Resolution: VGA supports a maximum resolution of 640 × 480 pixels.

• Refresh Rate: VGA can refresh at up to 60Hz, but only when limited to 16 colors. Reducing the

resolution allows VGA to support up to 256 colors.

• Analog Limitations: VGA uses an analog signal, which does not support the higher-definition visuals

and color depth required by modern displays.