DesignWare ARC EM Software Development Platform

User Guide
Version 5795-004 January 2019
Copyright Notice and Proprietary Information Notice
© 2019 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use,
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MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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[Link]
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Synopsys, Inc.
[Link]

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 Contents
List of Figures ....................................................................................................................................... 5
List of Tables......................................................................................................................................... 6
Accessing SolvNet ............................................................................................................................ 7
Contacting the Synopsys Technical Support Center ......................................................................... 7
1 Introduction ........................................................................................................................................ 8
1.1 Package Content ........................................................................................................................ 8
1.2 Getting Started ........................................................................................................................... 8
Installing Device Drivers ...................................................................................................... 8
Checking Default Board Settings ........................................................................................ 9
Installing and Configuring PuTTY........................................................................................ 9
Programming the FPGA Device ........................................................................................ 12
Starting U-Boot.................................................................................................................. 13
1.3 Location of Components On ARC EM SDP ............................................................................. 14
1.4 Software Packages .................................................................................................................. 15
2 Hardware Description ...................................................................................................................... 16
2.1 Overview of the ARC EM SDP Board....................................................................................... 16
2.2 Overview of the ARC EM Software Development Platform ...................................................... 18
2.3 Clocks and Resets ................................................................................................................... 19
Clocks ............................................................................................................................... 19
Reset ................................................................................................................................. 23
2.4 Interrupts .................................................................................................................................. 24
2.5 DMA ......................................................................................................................................... 24
2.6 Debug and Trace ..................................................................................................................... 24
Debug ............................................................................................................................... 25
ARC Real-Time Trace ....................................................................................................... 26
2.7 Configuration and Boot Modes ................................................................................................. 27
Boot Switches ................................................................................................................... 28
VCCIO Voltage Selection Switches................................................................................... 30
Miscellaneous Switches .................................................................................................... 31

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On-Board LEDs ................................................................................................................. 31
2.8 Memories ................................................................................................................................. 32
2.9 USB Interface ........................................................................................................................... 32
2.10 SD Card Interface..................................................................................................................... 33
2.11 Audio Interface ......................................................................................................................... 33
2.12 On-Board I2C Control Bus ....................................................................................................... 34
2.13 ADC.......................................................................................................................................... 34
2.14 Redpine® WiFi, Bluetooth, Zigbee Interface ............................................................................. 35
2.15 External Bus Interface .............................................................................................................. 35
Timing Diagrams ............................................................................................................... 36
2.16 Extension Interfaces ................................................................................................................. 37
Digilent Pmod™ ................................................................................................................ 37
Mikrobus ........................................................................................................................... 42
Arduino .............................................................................................................................. 43
Generic Header ................................................................................................................. 46
3 Programmer’s Reference ................................................................................................................. 49
3.1 Memory Map ............................................................................................................................ 49
APB Peripheral Address Map ........................................................................................... 50
Auxilary Based Peripherals ............................................................................................... 52
3.2 Software Interfaces .................................................................................................................. 53
Clock Registers ................................................................................................................. 53
Control Registers .............................................................................................................. 71
EBI Registers .................................................................................................................... 80
Glossary and References ................................................................................................................... 86
Glossary .......................................................................................................................................... 86
References ...................................................................................................................................... 87

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 List of Figures
Figure 1 Identification of COM Port ....................................................................................................................10
Figure 2 PuTTY Configuration ............................................................................................................................11
Figure 3 ARC EM SDP Programming of the Bitstream ......................................................................................12
Figure 4 Configuration LEDs ..............................................................................................................................13
Figure 5 Default Boot with ARC EM Initialization ................................................................................................13
Figure 6 ARC EM SDP Components - Top View ................................................................................................14
Figure 7 ARC EM SDP Components - Bottom View ..........................................................................................15
Figure 8 ARC EM SDP Block Diagram ...............................................................................................................16
Figure 9 ARC EM Software Development Platform Top-Level Diagram ............................................................18
Figure 10 ARC EM SDP Clock Architecture .......................................................................................................19
Figure 11 Graphical Overview of the Clock Domains .........................................................................................22
Figure 12 Reset Architecture ..............................................................................................................................23
Figure 13 ARC EM SDP Debug and Trace Headers ..........................................................................................25
Figure 14 Pinout of 10-Pin Debug Header ..........................................................................................................25
Figure 15 10-Pin to 20-Pin JTAG Adapter ..........................................................................................................26
Figure 16 Nexus Mictor 38 Interface ...................................................................................................................27
Figure 17 ARC EM SDP Configuration - Boot Switches and Buttons .................................................................27
Figure 18 Normal Read (Without External Wait) ................................................................................................36
Figure 19 Normal Write (Without External Wait) .................................................................................................36
Figure 20 ARC EM SDP Peripheral Extension Interfaces ..................................................................................37
Figure 21 Pinout Diagram of the Pmod_A, Pmod_B and Pmod_C Connectors .................................................38
Figure 22 MikroBus Headers ..............................................................................................................................42
Figure 23 Arduino Shield Interface .....................................................................................................................44
Figure 24 Generic Pin Header Interface .............................................................................................................46

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 List of Tables
Table 1 Overview of ARC EM SDP Clock Components ..............................................................................20
Table 2 Audio Clock Divider Settings ...........................................................................................................34
Table 3 ARC EM SDP On-board I2C Slave Addresses ...............................................................................34
Table 4 ADC Channel Usage .......................................................................................................................35
Table 5 Pin Description of the Pmod_A Connector ......................................................................................39
Table 6 Pin Description of the Pmod_B Connector ......................................................................................40
Table 7 Pin Description of the Pmod_C Connector .....................................................................................41
Table 8 Pin Description of the MikroBUS Connectors .................................................................................43
Table 9 Pin Description of the Arduino Shield Interface ...............................................................................45
Table 10 ADC Input........................................................................................................................................46
Table 11 Pin Description of the Generic Pin Interface ...................................................................................47
Table 12 ARC EM SDP Memory Map ............................................................................................................49
Table 13 APB Peripheral Address Map .........................................................................................................50
Table 14 Auxiliary Based IO Peripherals .......................................................................................................52
Table 15 CGU Clock Register Overview ........................................................................................................54
Table 16 CREG Control Register Overview ...................................................................................................72

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 Customer Support

Customer support is available through SolvNet online customer support and through contacting the
Synopsys Technical Support Center.

Accessing SolvNet
SolvNet includes an electronic knowledge base of technical articles and answers to frequently asked
questions about Synopsys tools. SolvNet also gives you access to a wide range of Synopsys online
services, which include downloading software, viewing Documentation on the Web, and entering a call
to the Support Center.
To access SolvNet:
1. Go to the SolvNet Web page at [Link]
2. If prompted, enter your user name and password. (If you do not have a Synopsys user
name and password, follow the instructions to register with SolvNet.)
If you need help using SolvNet, click SolvNet Help in the Support Resources section.

Contacting the Synopsys Technical Support Center

If you have problems, questions, or suggestions, you can contact the Synopsys Technical
Support Center in the following ways:
 Open a call to your local support center from the Web by going to
[Link] (Synopsys user name and password required), then
clicking “Enter a Call to the Support Center.”
 Send an e-mail message to your local support center.
o E-mail support_center@[Link] from within North America.
o Find other local support center e-mail addresses at
[Link]
 Telephone your local support center.
o Call (800) 245-8005 from within the continental United States.
o Call (650) 584-4200 from Canada.
o Find other local support center telephone numbers at
[Link]

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 1
Introduction

1.1 Package Content

The DesignWare ARC EM Software Development Platform package contains the following
items:
 DesignWare ARC EM Software Development Platform (ARC EM SDP).
 A 100-240 V AC power adapter (including adapters for the US, UK, and EU outlets).
 USB cable.

The DesignWare ARC EM Development Platform contains static-sensitive devices.

Warning

1.2 Getting Started

This section includes instructions for the following tasks:

1. Installing device drivers

2. Checking default board settings

3. Installing and configuring PuTTY

4. Starting U-Boot

Installing Device Drivers

Before the USB-JTAG and the USB-UART interfaces are used, you must install the required
drivers on the computer where you intend to run the MetaWare debugger or another serial
debug console (such as PuTTY or other hyper-terminals). For more information on the
MetaWare debugger, see MetaWare Debugger User’s Guide for ARC.
The driver is a part of the Digilent® Adept tool. You can download the most recent version of
the Digilent Adept tool from the Digilent website at [Link] and follow the
installation instructions provided by Digilent.

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Checking Default Board Settings

Check if the boot switches and jumpers are set to their default positions. For an overview of
the configuration options and the default settings, see Configuration and Boot Modes on
page 27.
Connect the ARC EM SDP to your PC by connecting the USB cable to the USB data port of
the ARC EM SDP and the PC.
Connect the power supply included in the product package to the ARC EM SDP.

Note The ARC EM SDP must be powered by an external power adapter.

Installing and Configuring PuTTY

PuTTY is a serial console that can be used as a simple debug console.
1. Download [Link] from [Link]
2. Open the Windows Control Panel.
3. In the category Hardware and Sound, click View devices and printers, and Digilent
Adept USB Device.
The Digilent Adept USB Device Properties windows opens.
Select the Hardware tab and note the COM port assigned to the USB Serial Port.
The example in Figure 1 uses the COM6 port:

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Figure 1 Identification of COM Port

4. Execute [Link].
The PuTTY Configuration window appears.
5. Set the Connection type to Serial.
6. Enter the name of the COM port in the Serial line field.
7. Set the Speed field to 115200 as shown in Figure 2.

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Figure 2 PuTTY Configuration

8. Click Open to launch the PuTTY terminal.

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Programming the FPGA Device

The FPGA on the ARC EM SDP board is configured by storing an FPGA bitstream in the
configuration memory of the ARC EM SDP. By default, no image is present in the
configuration memory and the configuration LED blinks red (see Figure 4).
The configuration memory can be accessed by connecting the USB cable to the USB data
port of the ARC EM SDP and the PC. When the ARC EM SDP is powered (power LED lights
green), the ARC EM SDP presents itself as a mass-storage device on the PC (see Figure 3).

Figure 3 ARC EM SDP Programming of the Bitstream

Drag-and-drop an FPGA bitstream to the USB drive and the bitstream is copied from the PC
to the configuration memory and programmed into the FPGA.
While the configuration memory is being written, the status LED blinks green. When a
bitstream is stored inside the configuration memory, the bitstream is automatically
programmed into the FPGA. During this process the configuration LED blinks red.
When the configuration is completed, the status LED on the ARC EM SDP stays green. For
a full description on the LEDs, see On-Board LEDs on page 31.

Note Updating the content of the configuration memory may take few minutes to complete.

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The bitstream remains present in the non-volatile configuration memory until it is overwritten
by another bitstream or is explicitly removed from the memory. This means that on a next
power cycle, or when pressing the CFG key, the FPGA is automatically programmed with the
bitstream present in the configuration memory.

Figure 4 Configuration LEDs

Starting U-Boot
Press the start button on the ARC EM SDP for the ARC EM core to start executing the
bootloader. After you press the start button, you see text similar as shown in Figure 5. This
figure shows a log from default booting, followed by U-Boot commands to initialize the ARC
EM SDP board and start an application called [Link] that resides on the SD card. The
entry point for this example application is 0x1000_0400.

Figure 5 Default Boot with ARC EM Initialization

U-Boot 2018.11 (Nov 27 2018 - [Link] +0100)

CPU: ARC EM11D v5.0 at 40 MHz

Subsys:ARC Data Fusion IP Subsystem
Model: snps,emsdp
Board: ARC EM Software Development Platform v1.0
DRAM: 16 MiB
MMC: Synopsys Mobile storage: 0
Loading Environment from FAT... OK
In: serial0@f0004000
Out: serial0@f0004000
Err: serial0@f0004000
emsdp# fatload mmc 0 0x10000000 [Link]
45728 bytes read in 28 ms (1.6 MiB/s)
emsdp# go 0x10000400
## Starting application at 0x10000400 ...

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For more information on the available U-Boot commands, you can execute the help function
in U-Boot.

1.3 Location of Components On ARC EM SDP

Figure 6 and Figure 7 show the placement of various components on the ARC EM SDP.

Figure 6 ARC EM SDP Components - Top View

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Figure 7 ARC EM SDP Components - Bottom View

1.4 Software Packages

See the [Link] portal for information on the available software packages for the
ARC EM SDP.
For more details on the embARC software releases for ARC EM SDP, see:
 [Link]
Additional documentation on how to get started can be found here:
 [Link]
Systems-Forum/wiki/ARC-Development-Systems-Forum-Wiki-Home

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 2
Hardware Description

2.1 Overview of the ARC EM SDP Board

Figure 8 ARC EM SDP Block Diagram
50-pin
Arduino PMOD (2x6) x3
header

I2C/ GPIO/ PWM/ SPI/ UART/ I3C

I2C/ GPIO/ PWM/ SPI/ UART

I2C/ GPIO/ PWM/ SPI/ UART

I2C/ GPIO/ PWM/ SPI/ UART

6

EBI, SPI, I2C

DC AC

14 8 8 8 42
ADC
Cortex Debug 10-pin

6
GPIO
SPI

4
UART

Bluetooth/
JTAG 4 WiFi
4
Interrupt e.g. RedPine
RS9113

4 SPI
PSRAM Addr
19
16MB Interrupt
Data 9D sensor
32 InvenSense
MPU-9250
I2C
Rght MEMs
microphn 2
Line out (r)
InvenSense Kintex-7 XC7K325T Audio
Left MEMs
ICS-41350 Codec Line out (l)
C2 microphn 2 PDM e.g. Line in (r)
4 I2S Maxim9880 Line in (l)
e.g. InvenSense
2 ICS-41350

MikroBus
4 SPI 12 I2C/ PWM/ SPI/ UART
DIN
CCLK 12.288 MHz
PROGRAM_B
Audio clock
FPGA configurator
UART

DONE
JTAG

4 SDIO QSPI
4 4
INIT

7
FTDI
38
12 MHz
SPI flash
SD-card 16MB
USB

Interface e.g. Micron

Conf N2 5Q128A
Memory

USB HUB
USB 24 MHz
USB

Micro-USB MICTOR

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The ARC EM SDP contains the following components:

 FPGA
o Xilinx® Kintex®-7 XC7325T-2
 Memory
o PSRAM (16 MB)
o SPI Flash (16 MB quad-mode XiP)
o Configuration memory (16 MB SPI flash)
 Interfaces
o Audio line in/out
o USB Data port (JTAG/UART/access to configuration memory)
o Micro- SD Card
o Wi-Fi®/Bluetooth®/Zigbee® module
o ADC (eight channels)
o Motion Sensor
o Digital MEMs microphone (2x)
o RTT Nexus, JTAG
 Extensions
o Arduino® Interface headers (UNO Rev3 compatible)
o MikroBUSTM headers
o Digilent PmodTM Interfaces (3x)
o Generic Pin Header (50 pins)

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2.2 Overview of the ARC EM Software Development Platform

Figure 9 ARC EM Software Development Platform Top-Level Diagram

I2C I2C
PDM PDM Audio Codec
I2S I2S

RTT RTT
9-D Sensor
I2C
MPU-9250 ARC EM Subsystem ADC ARDUINO (A)
SPI/ GPIO
SPI/ I2C/
PIN HEADER

UART
GPIO SPI ARDUINO (D)
AHB Target(s)
MUX
EBI/

Gen

GPIO
AHB Initiator(s) (DMI) JTAG PER I2C
PWM

Pmod/ Arduino MUX

PMOD1
DW_ARC_AHB
PMOD2

EBI SRAM ROM PMOD3

S
S S S

PWM
MikroBus

DW_MEM_AHB DW_apb_timer NIST TRNG

S S
DW_SDIO_AHB

DW_APB

S S S S S
S M S S
S
dwc_mobile Clock and Reset
PSRAM DW_apb_ssi DW_apb_uart DW_apb_ssi DW_apb_gpio CREG
storage (SDIO) DW_apb_uart Unit

RS9113
FTDI Quad-SPI Switches/
PSRAM SD Card Connect-IO-n
JTAG/ DBG UART Flash (XiP) LEDs
BT+WiFi+Zigbee

The ARC EM SDP provides the following main features:

 Flexible clock generation
 System clocks

 Audio clocks

- Audio reference clock input (12.288 MHz)

- Integer divider(s) for audio serial clock
 256 KB SRAM
 256 KB ROM
 SD card interface
 UART interfaces

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DW ARC EM Software Development Platform User Guide Clocks and Resets

 I2C interfaces
 SPI interfaces
 PWM interfaces
 JTAG interface

2.3 Clocks and Resets

Clocks
The ARC EM SDP uses a single 100 MHz reference clock from which all the system clocks
are generated. The clock generation is centralized in the Clock and Reset Unit (CRU). The
CRU implements several PLLs and integer dividers that allow for accurate fine-tuning of the
system clocks to the desired frequency. Figure 10 shows the ARC EM SDP clock architecture.

Figure 10 ARC EM SDP Clock Architecture

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Table 1 lists the summary of all the clocks and their sources.

Table 1 Overview of ARC EM SDP Clock Components

PLL Base Clock Clock Name Description Default

Frequency

Core Clock Domain

0 0 arc_clk ARC core clock 50 MHz (see

driving EM table footnote)
subsystem

AMBA Clock Domain

0 ahb_clk AHB clock for 100 MHz

bus
infrastructure
1
0 apb_clk APB clock for 50 MHz
bus
infrastructure

Reference Clock Domain

0 sdio_ref_clk SDIO reference 100 MHz

clock

1 spi_ref_clk SPI reference 20 MHz

clock

2 timer_ref_clk Timer reference 100 MHz

clock
2
3 uart_ref_clk UART reference 100 MHz
clock

4 ebi_ref_clk EBI reference 100 MHz

clock

5 i2c_ref_clk I2C reference 100 MHz

clock

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DW ARC EM Software Development Platform User Guide Clocks and Resets

PLL Base Clock Clock Name Description Default

Frequency

Audio Clock Domain

0 i2s_ref_clk I2S reference 12.228 MHz

clock
3
1 pdm_ref_clk PDM reference 12.288 MHz
clock

Note: The default ARC clock frequency may be different based on the configuration. For the actual frequency values,
see the build configuration description in the subsystem reference document that is delivered as part of the platform
package or the board header file.

Figure 11 shows a graphical representation of the different clock domains.

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Figure 11 Graphical Overview of the Clock Domains

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Reset
Figure 12 shows the top-level reset architecture of the ARC EM SDP.
When the ARC EM SDP is in reset, the resetn_out is asserted. This output pin resets all
components on the board that have a reset input pin (for example, the Redpine
communication module). The other board components have a power-on reset that assure the
correct sequence of de-asserting the board resets.
The ARC EM SDP has an external reset pin (resetn_in) that serves as an active low,
hardware reset. When the external hardware reset is active, the entire chip is reset. The chip
does not have an on-chip power-on-reset module, so it relies on the external circuitry to keep
resetn_in asserted low until all the chip power supplies and the system input clock are
stabilized.
The reset generated by the reset button is merged with a Power-on Reset circuit and the FTDI
‘ACBUS6’ GPIO pin. This allows for the board to be reset from a PC. For more information
on FTDI Chip, see FT2232H Datasheet .
After the ARC EM SDP is out of reset, resetn_out is asserted resetting all the ARC EM
SDP components. The resetn_out is also routed to the Mikrobus headers.

Figure 12 Reset Architecture

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2.4 Interrupts
The interrupt architecture of the ARC EM SDP depends on the design with which the FPGA
is programmed. Each interrupt in the design is assigned to a dedicated interrupt pin on the
ARC EM processor.
The assignment of the interrupt pins can be derived from the software header files delivered
as part of the product. For more information on the assignment of the interrupt pins, see the
subsystem reference document that is delivered as part of the platform package.

2.5 DMA
The DMA architecture of the ARC EM SDP depends on the design with which the FPGA is
programmed. Each DMA channel interface in the design is assigned to a dedicated DMA
interface on the ARC EM processors DMA controller.
The assignment of the DMA interface pins can be derived from the software header files
delivered as part of the product. For more information on the assignment of the DMA interface
pins, see the subsystem reference document that is delivered as part of the platform package.

2.6 Debug and Trace

The ARC EM SDP offers a rich set of debug and trace options:
 Debug:
 USB cable connected to the on-board 2-channel FTDI chip:

 Compatible with MetaWare debugger and GDB.

 Ashling Opella-XD, Lauterbach Trace-32, Digilent HS1 and HS2 support
through:

 A 10-pin 5 mm debug header and an adapter cable.

 Trace:
 Both on-chip through system memory or off-chip through the Nexus interface
into external host trace off-load is available.

Note The availability of the trace functionality depends on the build configuration.
For more details on the build configuration, see the subsystem reference
document that is delivered as part of the platform package.

 Ashling Ultra-XD and Lauterbach Trace-32 are supported.

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Figure 13 shows the various debug and trace headers.

Figure 13 ARC EM SDP Debug and Trace Headers

Debug
The ARC EM core provides debug access through an IEEE 1149.1 JTAG port.

[Link] USB Dataport

The USB Dataport can be connected to your PC using the USB cable included in the product
package. A USB converter from FTDI (FT2232HL) converts one channel to a serial
communication protocol (UART). The other channel is converted to JTAG.
The JTAG channel offered over this Dataport is compatible with the MetaWare debugger. The
serial communication channel is used as a console and can be monitored using a standard
hyper terminal application for example PuTTY. For more information, see Getting Started on
page 8.

[Link] 10-Pin Header Pinout

The ARC EM SDP includes a 10-pin debug header that can be used for a JTAG connection
towards the core.

Figure 14 Pinout of 10-Pin Debug Header

This header can be used to connect a standard 20-pin Ashling or Lauterbach probe header
using an adapter. Figure 15 shows the 10-pin to 20-pin JTAG adapter.

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Debug and Trace DW ARC EM Software Development Platform User Guide

Figure 15 10-Pin to 20-Pin JTAG Adapter

The adapter can be purchased from many distributors such as Mouser, Embedded Artists,
and Digikey.

ARC Real-Time Trace

The ARC EM SDP implements Real-Time-Trace capability (ARC RTT). When ARC RTT is
present in the configuration, it allows configurable/ programmable monitoring of:
 Program flow and instruction execution
 Data reads and writes
 Auxiliary reads and writes
 Core register writes

Note The trace functionality is only present when ARC RTT has been configured for the
subsystem.

Trace data can either be off-loaded from internal ARC RTT buffers to an on-chip memory (that
is, PSRAM), or to an off-chip memory in an external host using the Nexus 5001 interface.
The Nexus 5001 interface is a 16-bit high-speed interface and for the ARC EM SDP, it
supports a trace clock up to 50 MHz.

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Figure 16 Nexus Mictor 38 Interface

The ARC RTT interface is supported with the Ashling Ultra-XD and Lauterbach Trace-32
products.

2.7 Configuration and Boot Modes

Figure 17 shows the configuration switches, jumpers, and LEDs available on the ARC EM
SDP. In addition to jumpers and standard reset and start buttons there are also switches to
control the board boot mode and debug mode.
For further details on the jumpers and switches used in ARC EM SDP configuration, see the
following sections.

Figure 17 ARC EM SDP Configuration - Boot Switches and Buttons

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Boot Switches
[Link] JTAG Port Switches

These switches are used to control the way the JTAG signals are routed. This can be either
through the USB dataport, the 10-pin debug header or through the Nexus RTT interface.

USB mode.
JTAG signals are routed through the FTDI USB port. The Digilent plugin
of the MetaWare debugger can be used to access the core. No external
probe is required. This is the default setting.

JTAG mode.
JTAG signals are routed over the 10-pin debug header. An external
probe can be used to access to core.

RTT mode.
JTAG signals are routed over the 38-pin Mictor header. An external probe
can be used to access to core.

Reserved.

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DW ARC EM Software Development Platform User Guide Configuration and Boot Modes

[Link] Boot Start Mode Switch

This switch controls manual or automatic booting of the ARC EM SDP.

Manual mode.
The ARC EM SDP only starts booting after the START button is pushed.
This is the default setting.

Automatic mode.
The ARC EM SDP automatically starts booting after Reset.

[Link] Boot Image Location Switch

The following table provides an overview of the boot image location switch settings.

Ensure that these switches are set as depicted on the left (default position).
This setting ensures that the pre-bootloader starts executing the
bootloader that is stored in ROM.

Reserved for future use.

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VCCIO Voltage Selection Switches

[Link] VCCIO Voltage Selection

The following table provides an overview of the reference voltage selection for the generic pin
header.

1.8V.
VIO pins of the generic pin header output - 1.8 volts.

2.5V.
VIO pins of the generic pin header output - 2.5 volts.

3.3V.
VIO pins of the generic pin header output - 3.3 volts.

[Link] Factory Update

The following table provides an overview of the factory update mode.

Normal mode.
The JTAG port is connected to the program interface of the FPGA or
the JTAG chain of the ARC core depending on the board status and
the JTAG overwrite switch. This is the default setting.

Factory mode.
This mode allows the firmware for the FPGA configurator to be
updated.

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Miscellaneous Switches
[Link] USB JTAG Overwrite

This switch controls the muxing or the JTAG chain.

Normal mode.
While the status LED stays green, the USB JTAG is connected to the
debug interface of the ARC core. When the status LED indicates that no
design is present, the USB JTAG is connected to the program interface of
the FPGA. This is the default setting.

Program mode.
Independent of the status LED, the USB JTAG is connected to the
program interface of the FPGA.

On-Board LEDs
The ARC EM SDP includes the following LEDs:
 Eight user LEDs
 Three status LEDs
The status LEDs indicate the status of the board. The following table lists an overview of the
status LEDs.

ON.
Power is supplied to the board.

CONFIG.
The bitstream configuration is being programmed in the FPGA while the
config LED is blinking. When the config LED remains blinking, there is
no (valid) bitstream present inside the configuration memory.

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READY.
The bitstream located inside the configuration memory has been
successfully loaded into the FPGA.

UPDATE.
When the status LED blinks green, the content of the configuration
memory is updated. Upon completion, the new content is automatically
programmed in the FPGA.

The user LEDs can be controlled through the DesignWare GPIO. For more information, see
DesignWare DW_apb_gpio Databook.

2.8 Memories
The ARC EM SDP features the following memories:
 16 MB PSRAM memory
 16 MB user available SPI flash
o This SPI flash supports Quad-mode SPI and execute-in-place
 16 MB dedicated SPI flash storage for FPGA bitstream

2.9 USB Interface

The ARC EM SDP offers a single USB 2.0 host port, which is both used to access the FPGAs
configuration memory and as a DEBUG/ UART port as described in USB Dataport on page
25.
When connected using the USB cable to a PC, the ARC EM SDP presents itself as a mass-
storage device. This allows an FPGA configuration bitstream to be dragged and dropped into
the configuration memory. The FPGA bitstream is automatically loaded into the FPGA device
upon power-on reset, or when the configuration button is pressed.

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2.10 SD Card Interface

The ARC EM SDP features a micro SD-card interface supporting the following micro SD
cards:
 Secure Digital (SD)
 Secure Digital Input Output (SDIO)
 Secure Digital High Capacity (SDHC), with memory capacities up to 32 GB
 Secure Digital Extended Capacity (SDXC) which supports cards up to 2 TB

After U-Boot, the default settings operate the SD card in the SDR25 speed mode.

2.11 Audio Interface

The ARC EM SDP features stereo audio jacks for Line Out and Line In. The stereo audio
input and output signals are converted using a MAX9880A stereo codec from Maxim
Integrated, which provides the interface between the stereo I2S ports of the ARC EM SDP
and drives the Line Out and Line In interfaces. The I2S is controlled by the io_i2s_tx
and io_i2s_rx auxiliary based peripheral controllers in the subsystem. For more information,
see Dual I2S Stereo Audio Codec MAX9880A .

Note The audio codec is controlled by the I2S controllers inside the subsystem, and this
functionality is therefore only available when I2S auxiliary based controller is present in
the build configuration of the subsystem.

The I2S ports operate in master mode, which means that the I2S IPs inside the ARC EM SDP
initialize and drive the I2S word select and a serial clock signal. The I2S serial clocks are
generated by integer dividers that run at a fixed audio reference clock frequency of
12.288 MHz.
In addition to the stereo audio jacks, the ARC EM SDP also features two PDM MEMs
microphones (left and right channel), which are controlled by the io_pdm_rx auxiliary based
PDM peripheral controller when configured in the subsystem. The PDM clock is also
generated by integer dividers that run on the audio reference clock of 12.288 MHz.

Note The PDM microphones are controlled by the PDM controller inside the subsystem, and
this functionality is therefore only available when the PDM auxiliary based controller is
present in the build configuration of the subsystem.

The ARC EM SDP supports the following sampling frequencies: 16 kHz, 32 kHz, 48 kHz, 96
kHz, and 192 kHz. Table 2 shows the divider settings for 16-bit stereo audio.

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Table 2 Audio Clock Divider Settings

Audio Sample Rate

16 kHz 32 kHz 48 kHz 96 kHz 192 kHz

24 12 8 4 2

2.12 On-Board I2C Control Bus

The ARC EM SDP offers an on-board I2C bus to control the following on-board devices:
 Audio codec
 9D motion sensor
Table 3 lists an overview of the I2C bus slave addresses. The on-board I2C bus is controlled
by the io_i2c_mst0 controller in the subsystem.

Note The on-board I2C bus is controlled by the I2C controller inside the subsystem, and this
functionality is therefore only available when the I2C auxiliary based controller is present
in the build configuration of the subsystem.

Table 3 ARC EM SDP On-board I2C Slave Addresses

Device Name Description 7-Bit I2C Address

MPU 9250 9D motion sensor 1101000 = 0x68

MAX 9880A Audio codec 0010000 = 0x10

2.13 ADC
The ARC EM SDP board includes the 8-input, 8-bit ADC088S022 from Texas Instruments.
The conversion rate ranges from 500 kSPS to 1 MSPS. The analog input range is 0 to 5 volts.
The analog input values are read using the io_spi_mst2 auxiliary peripheral. For more
information on 8-input 8-bit ADC088S022, see ADC088S022 Datasheet.

Note The ADC is controlled by the SPI controller inside the subsystem, and this functionality
is therefore only available when the SPI auxiliary based controller is present in the build
configuration of the subsystem.

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Table 4 lists the various ADC channels and their usage.

Table 4 ADC Channel Usage

ADC IN Usage
0 mikroBUS AN

1 Arduino AD0

2 Arduino AD1

3 Arduino AD2

4 Arduino AD3

5 Arduino AD4

6 Arduino AD5

7 Not Used

2.14 Redpine® WiFi, Bluetooth, Zigbee Interface

The ARC EM SDP board includes the Redpine Signals RS9113 module for communication
using Wi-Fi, Bluetooth, and Zigbee. For more information, see Redpine Signals RS9113-
WiseConnect-API-Guide-v1.7.1.
The SPI and UART host interfaces for running the embedded software stack are connected
to dedicated controllers (see APB Peripheral Address Map on page 50). By default, the
RS9113 is set in SPI host interface mode.

2.15 External Bus Interface

An external bus interface (EBI) controller provides access to external MMIO peripherals
through an SRAM-like interface with separate address and data bus plus the most commonly
used control signals (that is chip select, read/write strobes and optional signal for wait state
insertion. In the ARC EM SDP the main purpose of the EBI is to provide access to external
peripherals through the generic pin header.
Access to external peripherals is initiated using an AHB slave data port. The EBI controller
translates the AHB read//write requests into a sequence of memory read/writes. All critical
memory timing parameters are programmable for compatibility with different speed grades
and/or different vendors. The EBI controller provides an AHB slave configuration port for
access to the timing and control and status registers.

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Note The EBI controller FSM operates on the EBI reference clock (ebi_ref_clk). All the
memory timing parameters, such as read cycle wait time specified in the
EBI_CS_WCR1 register, are counted in ebi_ref_clk cycles.

Timing Diagrams
Figure 18 Normal Read (Without External Wait)

Figure 19 Normal Write (Without External Wait)

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2.16 Extension Interfaces

To bring your application context around the ARC EM SDP, the following peripheral module
standards are supported:
 Digilent Pmod™ (3x)
 MikroBUS (1x)
 Arduino (1x)

Figure 20 ARC EM SDP Peripheral Extension Interfaces

Furthermore, the ARC EM SDP features a single 50-pin generic pin header (42 IO pins, four
supply pins, and four ground pins).

Digilent Pmod™
The ARC EM SDP features three 12-pin Pmod connectors: Pmod_A, Pmod_B, and
Pmod_C.
The functionality of the Pmod connectors is programmable and includes GPIO, UART, SPI,
I2C, and PWM. Multiplexing is controlled by software using the PMOD_MUX_CTRL register
(see MUX Registers on page 74MUX ). After a reset, all ports are configured as GPIO
inputs.

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Figure 21 shows the location of the pins on the Pmod connectors. Detailed pin descriptions
depending on the pin multiplexer settings are provided in the subsequent sections.

Figure 21 Pinout Diagram of the Pmod_A, Pmod_B and Pmod_C Connectors

Note The Pmod is controlled by the controllers inside the subsystem, and this
functionality is therefore only available when the auxiliary based controllers are
present in the build configuration of the subsystem.
When the auxiliary based PWM IO peripherals are not available in the build
configuration of the subsystem, the PWM functionality of io_pwm0 is
implemented using dw_timer0 and the functionality of io_pwm1 is
implemented using dw_timer1.

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[Link] Pmod_A Connector

Table 5 lists the pin assignment of valid protocols that can be multiplexed on the Pmod_A connector. The GPIO
column is the default assignment after reset.

Table 5 Pin Description of the Pmod_A Connector

MUX Pin GPIO I2C SPI UART_1 UART_2 PWM_1 PWM_2

CFG0 A1 io_gpio1[0] io_gpio1[0] io_spi_mst1_cs[0] io_uart1_cts io_uart1_cts io_gpio1[0] io_gpio1[0]

A2 io_gpio1[1] io_gpio1[1] io_spi_mst1_mosi io_uart1_rts io_uart1_txd io_pwm1_ch[0] io_pwm1_ch[0]

A3 io_gpio1[2] io_i2c_mst2_scl io_spi_mst1_miso io_uart1_rxd io_uart1_rxd io_gpio1[2] io_gpio1[2]

A4 io_gpio1[3] io_i2c_mst2_sda io_spi_mst1_clk io_uart1_txd io_uart1_rts io_gpio1[2] io_pwm1_ch[1]

A5 GND GND GND GND GND GND GND

A6 3V3 3V3 3V3 3V3 3V3 3V3 3V3

CFG1 A7 io_gpio1[4] n.c. n.c. n.c. n.c. n.c. n.c.

A8 io_gpio1[5] n.c. n.c. n.c. n.c. n.c. n.c.

A9 io_gpio1[6] n.c. n.c. n.c. n.c. n.c. n.c.

A10 io_gpio1[7] n.c. n.c. n.c. n.c. n.c. n.c.

A11 GND GND GND GND GND GND GND

A12 3V3 3V3 3V3o 3V3 3V3 3V3 3V3

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[Link] Pmod_B Connector
Table 6 lists the pin assignment of valid protocols that can be multiplexed on the Pmod_B connector. The GPIO
column is the default assignment after reset.

Table 6 Pin Description of the Pmod_B Connector

MUX Pin GPIO I2C SPI UART_1 UART_2 PWM_1 PWM_2

CFG0 B1 io_gpio1[8] io_gpio1[8] io_spi_mst1_cs[1] io_uart2_cts io_uart2_cts io_gpio1[8] io_gpio1[8]

B2 io_gpio1[9] io_gpio1[9] io_spi_mst1_mosi io_uart2_rts io_uart2_txd io_pwm1_ch[2] io_pwm1_ch[2]

B3 io_gpio1[10] io_i2c_mst2_scl io_spi_mst1_miso io_uart2_rxd io_uart2_rxd io_gpio1[10] io_gpio1[10]

B4 io_gpio1[11] io_i2c_mst2_sda io_spi_mst1_clk io_uart2_txd io_uart2_rts io_gpio1[11] io_pwm1_ch[3]

B5 GND GND GND GND GND GND GND

B6 3V3 3V3 3V3 3V3 3V3 3V3 3V3

CFG1 B7 io_gpio1[12] n.c. n.c. n.c. n.c. n.c. n.c.

B8 io_gpio1[13] n.c. n.c. n.c. n.c. n.c. n.c.

B9 io_gpio1[14] n.c. n.c. n.c. n.c. n.c. n.c.

B10 io_gpio1[15] n.c. n.c. n.c. n.c. n.c. n.c.

B11 GND GND GND GND GND GND GND

B12 3V3 3V3 3V3 3V3 3V3 3V3 3V3

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[Link] Pmod_C Connector
Table 7 lists the pin assignment of valid protocols that can be multiplexed on the Pmod_C connector. The GPIO
column is the default assignment after reset.

Table 7 Pin Description of the Pmod_C Connector

MUX Pin GPIO I2C SPI UART_1 UART_2 PWM_1 PWM_2

CFG0 C1 io_gpio1[16] io_gpio1[16] io_spi_mst1_cs[2] io_uart3_cts io_uart3_cts io_gpio1[16] io_gpio1[16]

C2 io_gpio1[17] io_gpio1[17] io_spi_mst1_mosi io_uart3_rts io_uart3_txd io_pwm1_ch[4] io_pwm1_ch[4]

C3 io_gpio1[18] io_i2c_mst2_scl io_spi_mst1_miso io_uart3_rxd io_uart3_rxd io_gpio1[18] io_gpio1[18]

C4 io_gpio1[19] io_i2c_mst2_sda io_spi_mst1_clk io_uart3_txd io_uart3_rts io_gpio1[19] io_pwm1_ch[5]

C5 GND GND GND GND GND GND GND

C6 3V3 3V3 3V3 3V3 3V3 3V3 3V3

CFG1 C7 io_gpio1[20] n.c. n.c. n.c. n.c. n.c. n.c.

C8 io_gpio1[21] n.c. n.c. n.c. n.c. n.c. n.c.

C9 io_gpio1[22] n.c. n.c. n.c. n.c. n.c. n.c.

C10 io_gpio1[23] n.c. n.c. n.c. n.c. n.c. n.c.

C11 GND GND GND GND GND GND GND

C12 3V3 3V3 3V3 3V3 3V3 3V3 3V3

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Mikrobus
The ARC EM SDP features a set of MikroBUS headers. Figure 22 shows the relevant function
assignments, fully compatible with the MikroBUS standard. For more information, see the
MikroBUS standard specification.
The MikroBUS headers enable the addition of Click boards. Click boards are developed by
the company MikroElektronica ([Link]) and are a range of hundreds of add-on
boards for interfacing with peripheral sensors and transceivers. Click boards include wireless
and wired connectivity modules, sensor modules, display modules, interface modules, and
miscellaneous modules and accessories, See [Link]/click for a full list.
Multiplexing to get the right function assignment of the auxiliary based peripheral controllers
on the MikroBUS headers is controlled by software using the ARDUINO_MUX_CTRL register
(see MUX Registers on page 74).
Note that since the controllers that are mapped to the MikroBUS are shared with the Arduino
controllers, and therefore the MikroBUS functions are only available when the Arduino
multiplexer ARDUINO_MUX_CTRL is in the default mode (GPIO).

Note The MikroBUS is controlled by the controllers inside the subsystem, and this
functionality is therefore only available when auxiliary based controllers are present in
the build configuration of the subsystem.

Figure 22 MikroBus Headers

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Table 8 shows the pin assignment on the I/O multiplexer.

Table 8 Pin Description of the MikroBUS Connectors

Pin I/O Pin I/O

AN ADC VIN0* PWM io_pwm0_ch[0]

RST io_gpio0[20] INT io_gpio0[21]

CS io_spi_mst0_cs[0] RX io_uart0_rxd

SCK io_spi_mst0_clk TX io_uart0_txd

MISO io_spi_mst0_rxd SCL io_i2c_mst1_scl

MOSI io_spi_mst0_txd SDA io_i2c_mst1_sda

*: *ADC VIN0 is available through the on-board ADC and is read though io_spi_mst2.

Arduino
The ARC EM SDP provides an Arduino shield interface. Figure 23 shows the pin assignments.
The Arduino shield interface is compatible with the Arduino UNO Rev3 with the following
exceptions:
 5-volt shields are not supported.
 The IOREF voltage on the ARC EM SDP board is fixed to 3.3 volts.

Note The ICSP header is not available. Most shields do not require this ICSP header as the
SPI master interface on this ICSP header is also available on the IO10 to IO13 pins.

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Figure 23 Arduino Shield Interface

Table 9 shows the pin assignment on the I/O multiplexer. Multiplexing is controlled by software
using the ARDUINO_MUX_CTRL register (see MUX Registers on page 74). After a reset, all
the ports are configured as GPIO inputs.

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Table 9 Pin Description of the Arduino Shield Interface

MUX Pin I/O-1 I/O-2 I/O-3 I/O-4 I/O-5

x AD0 io_gpio0[14] - -

AD1 io_gpio0[15] - -

AD2 io_gpio0[16] - -

AD3 io_gpio0[17] - -

CFG6 AD4 io_gpio0[18] io_i2c_mst1_sda -

AD5 io_gpio0[19] io_i2c_mst1_scl -

CFG0 IO0 io_gpio0[0] io_uart0_rxd -

IO1 io_gpio0[1] io_uart0_txd -

CFG1 IO2 io_gpio0[2] io_gpio[2] -

IO3 io_gpio0[3] io_pwm0_ch[0] -

CFG2 IO4 io_gpio0[4] io_gpio[4] -

IO5 io_gpio0[5] io_pwm0_ch[1] -

CFG3 IO6 io_gpio0[6] io_pwm0_ch[2] -

IO7 io_gpio0[7] io_gpio[7] -

CFG4 IO8 io_gpio0[8] io_gpio[8] -

IO9 io_gpio0[9] io_pwm0_ch[3] -

CFG5 IO10 io_gpio0[10] io_spi_mst0_cs[0] io_pwm0_ch[4] io_gpio[10] io_pwm0_ch[4]

IO11 io_gpio0[11] io_spi_mst0_mosi io_pwm0_ch[5] io_pwm0_ch[5] io_gpio[11]

IO12 io_gpio0[12] io_spi_mst0_miso io_gpio[12] io_gpio[12] io_gpio[12]

IO13 io_gpio0[13] io_spi_mst0_clk io_gpio[13] io_gpio[13] io_gpio[13]

The analog input pins AD0 – 5 are also directly connected to the on-board ADC and are read
through io_spi_mst2. The assignment is shown in Table 10.

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Table 10 ADC Input

Pin I/O-1

AD0 ADC VIN1

AD1 ADC VIN2

AD2 ADC VIN3

AD3 ADC VIN4

AD4 ADC VIN5

AD5 ADC VIN6

Generic Header
In addition to the standard interfaces, the ARC EM SDP also features a generic pin header.
Figure 24 shows the pin assignments. The pin header can be used as an EBI interface
towards an external peripheral device or as a host interface.

Figure 24 Generic Pin Header Interface

Multiplexing is controlled by software using the GENERIC_MUX_CTRL register (see

MUX Registers on page 74).

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Table 11 Pin Description of the Generic Pin Interface

Pin GPIO EBI Host-IF DBG Pin GPIO EBI Host-IF DBG
IO0_P - - - IO0_N - - -

IO1_P io_gpio2 CSn spi_slv0_sclk - IO1_N io_gpio2 A0 - -

[0] [4]

IO2_P io_gpio2 WAIT spi_slv0_miso - IO2_N io_gpio2[5] A1 - -

[1]

IO3_P io_gpio2 RDn spi_slv0_mosi - IO3_N io_gpio2[6] A2 - -

[2]

IO4_P io_gpio2 WRn spi_slv0_csn - IO4_N io_gpio2[7] A3 - -

[3]

IO5_P io_gpio2 D0 - - IO5_N io_gpio2[8] A4 i2c_slv0_sda -

[24]

IO6_P io_gpio2 D1 - - IO6_N io_gpio2[9] A5 i2c_slv0_scl -

[25]

IO7_P io_gpio2 D2 - - IO7_N io_gpio2 A6 - -

[26] [10]

IO8_P io_gpio2 D3 - - IO8_N io_gpio2 A7 - -

[27] [11]

IO9_P io_gpio2 D4 - - IO9_N io_gpio2 A8 - -

[28] [12]

IO10_P io_gpio2 D5 - - IO10_N io_gpio2 A8 - -

[29] [13]

IO11_P io_gpio2 D6 - - IO11_N io_gpio2 A10 - -

[30] [14]

IO12_P io_gpio2 D7 - - IO12_N io_gpio2 A11 - -

[31] [15]

IO13_P - - - IO13_N io_gpio2 A12 - -

[16]

IO14_P - - - IO14_N io_gpio2 A13 - -

[17]

IO15_P - - - IO15_N io_gpio2 A14 - -

[18]

IO16_P - - - IO16_N io_gpio2 A15 - -

[19]

IO17_P - - - IO17_N io_gpio2 A16 - redpine_uart_cts

[20]

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Pin GPIO EBI Host-IF DBG Pin GPIO EBI Host-IF DBG
IO18_P - - - IO18_N io_gpio2 A17 - redpine_uart_txd
[21]

IO19_P - - - IO19_N io_gpio2 A18 - redpine_uart_rxd

[22]

IO20_P - - - IO20_N io_gpio2 A19 - redpine_uart_rts

[23]

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Programmer’s Reference

3.1 Memory Map

Table 12 shows the memory map overview of the ARC EM SDP.

Table 12 ARC EM SDP Memory Map

Address Start Offset Aperture Slave

0xF000_0000 256 MB AHB2APB bridge

0xE000_0000 RESERVED

0xD000_0000 RESERVED

0xC000_0000 RESERVED

0xB000_0000 RESERVED

0xA000_0000 16 KB YCCM1

0x9000_0000 16 KB XCCM1

0x8000_0000 128 KB DCCM

0x7000_0000 128 KB ICCM12

0x6000_0000 128 KB ICCM0

0x5000_0000 RESERVED

0x4000_0000 16 MB EBI data read/ write

0x3000_0000 RESERVED

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Address Start Offset Aperture Slave

0x2000_0000 256 KB SRAM

0x1000_0000 16 MB PSRAM

0x0000_0000 256 KB ROM

1. Only available if X/Y memory is present in the configuration.

2. Only available if ICCM1 memory is present in the configuration.

APB Peripheral Address Map

Table 13 lists all the APB peripherals that are accessible through the AHB2APB bridge 1.
The total reserved address space for the AHB2APB bridge is 256 MB. Accessing a non-
existing APB peripheral results in an AHB error response.

Table 13 APB Peripheral Address Map

Peripheral Name Base Size Description

dw_cru 0xF000_0000 4 KB Clock and Reset control. See

Clock Registers on page 53 for
register details.

dw_creg 0xF000_1000 4 KB Configuration register. See

Control Registers on page 71 for
register details.

dw_gpio 0xF000_2000 4 KB LED and switch control. For

more information on the register
details, see DesignWare
DW_apb_gpio Databook.

dw_nist_trng 0xF000_3000 1 KB True Random Number

Generator. For more information
on the register details, see
DesignWare DWC_trng_nist
Databook.

dw_dbg_uart 0xF000_4000 4 KB UART for FTDI terminal. For

more information on the register
details, see DesignWare
DW_apb_uart Databook.

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Peripheral Name Base Size Description

dw_wdt 0xF000_5000 4 KB Watchdog Timer. For more

information on the register
details, see DesignWare
DW_apb_wdt Databook.

dw_timers0 0xF000_6000 4 KB Timers 0. For more information

on the register details, see
DesignWare DW_apb_timers
Databook.

dw_timers1 0xF000_7000 4 KB Timers 1. For more information

on the register details, see
DesignWare DW_apb_timers
Databook.

dw_spi_mst0 0xF000_8000 4 KB Redpine SPI host interface. For

more information on the register
details, see DesignWare
DW_apb_ssi Databook.

dw_uart 0xF000_9000 4 KB Redpine UART host interface.

For more information on the
register details, see DesignWare
DW_apb_uart Databook.

Reserved 0xF000_A000 4 KB

dw_sdio 0xF001_0000 4 KB SD-card controller. For more

information on the register
details, see DesignWare DWC
Mobile Storage Host Databook.

Reserved 0xF001_1000

dw_spi_mst1 0xF100_0000 16 MB Quad-SPI flash controller. For

more information on the register
details, see DesignWare
DW_apb_ssi Databook.

dw_ebi 0xF200_0000 4 KB External Bus Interface

Controller. See EBI Registers on
page 80 for register details.

xilinx_axi_emc 0xF200_1000 4 KB PSRAM controller. For more

information on the register
details, see Xilinx AXI EMC.

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Auxilary Based Peripherals

Depending on the selected build configuration of the subsystem, a set of auxiliary based IO
peripherals is available. The peripherals are not controlled over a bus but are directly
controlled using the core’s internal auxiliary registers. Table 14 shows the list of auxiliary
based IO peripherals.
For more information about the individual IO peripherals see:
 DesignWare ARC Data Fusion IP Subsystem I/O Databook
 DesignWare Smart Sensor and Control IP Subsystem I/O Databook.

Table 14 Auxiliary Based IO Peripherals

Peripheral Name AUX Base Size Description

io_spi_mst0 0x8001_0000 256 byte SPI master for

Arduino and
MikroBUS

io_spi_mst1 0x8001_0100 256 byte SPI master for

Pmod_A, Pmod_B,
Pmod_C

io_spi_mst2 0x8001_0200 256 byte SPI master for on-

board ADC

io_spi_slv0 0x8001_1000 256 byte SPI slave for

Generic Pin Header

io_i2c_mst0 0x8001_2000 256 byte I2C master for on-

board I2C bus
(Codec, 9D sensor)

io_i2c_mst1 0x8001_2100 256 byte I2C master for

Arduino

io_i2c_mst2 0x8001_2200 256 byte I2C master for Pmod

io_i2c_slv0 0x8001_3000 256 byte I2C slave host

interface for generic
pin Header

io_uart0 0x8001_4000 256 byte UART for Arduino

and MikroBUS

io_uart1 0x8001_4100 256 byte UART for Pmod_A

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Peripheral Name AUX Base Size Description

io_uart2 0x8001_4200 256 byte UART for Pmod_B

io_uart3 0x8001_4300 256 byte UART for Pmod_C

io_gpio0 0x8001_7000 256 byte GPIO for Arduino

io_gpio1 0x8001_7100 256 byte GPIO for Pmod_A,

Pmod_B and
Pmod_C

io_gpio2 0x8001_7200 256 byte GPIO for Generic

Pin Header

io_i2s_tx 0x8001_9000 256 byte I2S TX for on-board

audio CODEC

io_i2s_rx 0x8001_a000 256 byte I2S RX for on-board

audio CODEC

io_pdm_rx 0x8001_b000 256 byte PDM for on-board

MEMs microphones

io_pwm0 0x8001_d000 256 byte PWM for Arduino

and MikroBUS

io_pwm1 0x8001_d100 256 byte PWM for Pmod_A,

Pmod_B and
Pmod_C

3.2 Software Interfaces

This section describes the software interfaces for the custom IP inside the ARC EM Software
Development Platform. For more information on the software interfaces for the DesignWare
IP and the DesignWare ARC subsystems, see the Databooks listed in References on page
87.

Clock Registers
The clock registers and the associated clock circuitry (that is, the PLLs plus clock dividers)
inside the ARC EM SDP are implemented by the Clock and Reset Unit (CRU) module. The
clock registers are used to program the PLLs and clock dividers. The CRU implements the
following PLLs:

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 ARC PLL:
 Used to generate the clock for the ARC HS

 SYS PLL:
 Used to generate all the other clocks in the system (for example, AHB, APB, and
IP core clocks)

 REF PLL:
 Used to generate reference clocks

In addition to the PLLs, the CRU module includes integer dividers for generating audio
reference clocks based on a fixed 12.288 MHz audio input clock.
Additionally, the CRU module implements a measurement logic that can be used to verify that
PLL and dividers have been programmed correctly. Guidelines for programming the PLL can
be found in PLL Programming on page 59, and for clock measurements in Frequency
Measurement on page 60
Table 15 lists the registers for the CRU module including a brief description and their offset
to the base address of the CRU (0xF000_0000). All registers are 32-bit wide. Read/write
access to undefined registers is ignored, and an APB error response is generated. All unused
bits within a register are non-writable and return zero when read.

Table 15 CGU Clock Register Overview

Name Address Access Description

Offset[1]

PLL Control and Status Registers

- ARC PLL

ARC PLL input

CGU_ARC_PLL_IDIV_CTRL 0x0000 RW divider control
register

ARC PLL status

CGU_ARC_PLL_STATUS 0x0004 R
register

ARC PLL
frequency
CGU_ARC_PLL_FMEAS 0x0008 RW
measurement
register

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Name Address Access Description

Offset[1]

ARC PLL
CGU_ARC_PLL_FBDIV_CTRL 0x000C RW feedback divider
control register

- SYS PLL

SYS PLL input

CGU_SYS_PLL_IDIV_CTRL 0x0010 RW divider control
register

SYS PLL status

CGU_SYS_PLL_STATUS 0x0014 R
register

SYS PLL
frequency
CGU_SYS_PLL_FMEAS 0x0018 RW
measurement
register

SYS PLL
CGU_SYS_PLL_FBDIV_CTRL 0x001C RW feedback divider
control register

- REF PLL

REF PLL input

CGU_REF_PLL_IDIV_CTRL 0x0020 RW divider control
register

REF PLL status

CGU_REF_PLL_STATUS 0x0024 R
register

REF PLL
frequency
CGU_REF_PLL_FMEAS 0x0028 RW
measurement
register

REF PLL
CGU_REF_PLL_FBDIV_CTRL 0x002C RW feedback divider
control register

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Name Address Access Description

Offset[1]

Clock Control and Status Registers

ARC PLL

Clock output
CGU_ARC_ODIV_ARC 0x0080 RW divider register for
ARC EM clock

Clock
measurement
CGU_ARC_FMEAS_ARC 0x0084 RW
register for ARC
EM clock

SYS PLL

Clock output
CGU_SYS_ODIV_AHB 0x00E0 RW divider register for
AHB clock

Clock
measurement
CGU_SYS_FMEAS_AHB 0x00E4 RW
register for AHB
clock

Clock output
CGU_SYS_ODIV_APB 0x00F0 RW divider register for
APB clock

Clock
measurement
CGU_SYS_FMEAS_APB 0x00F4 RW
register for APB
clock

REF PLL

Clock output
CGU_REF_ODIV_SDIO 0x0140 RW divider register for
SDIO clock

Clock
measurement
CGU_REF_FMEAS_SDIO 0x0144 RW
register for SDIO
clock

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Name Address Access Description

Offset[1]

Clock output
CGU_REF_ODIV_SPI 0x0150 RW divider register for
SPI clock

Clock
measurement
CGU_REF_FMEAS_SPI 0x0154 RW
register for SPI
clock

Clock output
CGU_REF_ODIV_TIMER 0x0160 RW divider register for
timer clock

Clock
measurement
CGU_REF_FMEAS_TIMER 0x0164 RW
register for timer
clock

Clock output
CGU_REF_ODIV_UART 0x0170 RW divider register for
UART clock

Clock
measurement
CGU_REF_FMEAS_UART 0x0174 RW
register for UART
clock

Clock output
CGU_REF_ODIV_EBI 0x0180 RW divider register for
EBI clock

Clock
measurement
CGU_REF_FMEAS_EBI 0x0184 RW
register for EBI
clock

Clock output
CGU_REF_ODIV_I2C 0x0190 RW divider register for
I2C clock

Clock
measurement
CGU_REF_FMEAS_I2C 0x0194 RW
register for I2C
clock

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Name Address Access Description

Offset[1]

AUDIO

Clock
measurement
CGU_AUDIO_FMEAS_I2S 0x01A4 RW
register for I2S
clock

Clock integer
CGU_AUDIO_IDIV_I2S 0x01A8 RW divider register for
I2S clock

Clock
measurement
CGU_AUDIO_FMEAS_PDM 0x01B4 RW
register for PDM
clock

Clock integer
CGU_AUDIO_IDIV_PDM 0x01B8 RW divider register for
PDM clock

Reset Control Registers

Reset control
CGU_ARC_RST_CTRL 0x0380 RW1C register for ARC
clock

Reset control
CGU_SYS_RST_CTRL 0x0384 RW1C register for system
clocks

Reset control
CGU_REF_RST_CTRL 0x0388 RW1C register for
reference clocks

Reset control
CGU_AUDIO_RST_CTRL 0x038C RW1C register for audio
clocks

Reset control
CGU_SYS_RST_OUT_CTRL 0x03A0 RW1C register for system
reset output

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Name Address Access Description

Offset[1]

Standard Registers

CGU IP software
CGU_IP_SW_RESET 0x0FF0 RW1C
reset register

CGU IP version
CGU_IP_VERSION 0x0FF8 R
register

CGU IP type
CGU_IP_TYPE 0x0FFC R
register

[1]: The following access types are defined:

 RW
Read/Write register

 R
Read-only register

 W
Write-only register

 RW1C
Read-only, Write-1-to-Clear register

[Link] PLL Programming

The Clock and Reset Unit (CRU) implements logic (FSM plus a clock switch) that allows
glitchless reprogramming of the PLLs with minimal software interaction. The PLLs are
implemented using the Xilinx MMCM primitive, which allows for dynamic reconfiguration.
Software must program the desired PLL output frequency using a set of three counter dividers.
Each PLL clock input has a programmable counter divider (D). Each PLL clock output has a
programmable counter divider (O). In addition, the feedback clock has a fractional counter
divider (M).
The divider settings for a certain PLL output clock frequency, Fout, can be calculated as
follows:
Fvco = Fclkin* (M/D)
Fout = Fclkin * M / (D*O)
where:
 D = input divider value
 M = feedback divider value
 O = output divider value

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The input clock frequency Fclkin of the ARC EM SDP is fixed to 100 MHz. The VCO
frequency Fvco needs to be between 600 MHz and 1440 MHz in accordance with the Xilinx
datasheet.
To detect completion of the PLL reprogramming sequence, software polls the
CGU_*_PLL_STATUS register.

[Link] Frequency Measurement

The frequency measurement module measures the frequency of a clock relative to the
100 MHz input-reference clock. The frequency measurement modules can be controlled
through the CRU_ *_FMEAS registers.
When the START bit in the CRU_*_FMEAS register is set to 1, a 15-bit counter FCNT starts
counting the number of cycles of the clock to be measured and simultaneously a second 15-
bit counter RCNT starts counting the number of cycles of the reference clock.
When either counter reaches its maximum count, both counters are disabled, and the DONE
bit in the CRU_*_FMEAS register is set to 1.
The current values of the counters can then be read, and the measured frequency can be
obtained by the following equation:

fmeas = (FCNT / RCNT) * fref

Note  By default, both counters start counting from zero. However, the
frequency calculation RCNT can be initialized with a non-zero
value. When RCNT is initialized with a value equal to 215 –
reference clock frequency in MHz and reaches its maximum count
before the FCNT counter saturates, the value stored in FCNT
would then show the measured clock’s frequency in MHz without
the need for any further calculation.
 The measured clock frequency can only be as known to the level
of precision of the reference clock frequency.
 Quantization error is noticeable if the ratio between the two clocks
is large (for example 1000 MHz versus 1 kHz) because one
counter saturates while the other counter only has a small count
value.
 Due to synchronization, the counters are not started and stopped
at the same time. This affects the accuracy of the frequency
measurement. This effect can be minimized by running the
counters as long as possible.

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[Link] Register Descriptions

[Link].1 PLL Control and Status Registers

CGU_m_PLL_IDIV_CTRL – PLL Control Register (Address Offset = 0x0000 + p*0x10)

Bit Name Access Value Description

0 BYPASS RW 1* Bypass PLL input

divider counter

1 HIGHEDGE RW 0* Force high time

counter to transition
on a falling edge (add
half a VCO cycle)

3:2 Reserved

9:4 HIGHTIME RW see below** Set number of VCO

cycles that the clock
remains high (DHIGH)

11:10 Reserved

17:12 LOWTIME RW see below** Set number of VCO

cycles that the clock
remains low (DLOW)

30:18 Reserved *

31 UPDATE RW1C 0* Update the PLL with

the configured values
*: Reset value
**: The values of m and p are:
p=0 m =ARC DHIGH=NA DLOW=NA MHIGH=5 MLOW=5 FVCO=1000 MHz
p=1 m =SYS DHIGH=NA DLOW=NA MHIGH=5 MLOW=5 FVCO=1000 MHz
p=2 m =REF DHIGH=NA DLOW=NA MHIGH=5 MLOW=5 FVCO=1000 MHz

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CGU_m_PLL_STATUS – PLL Status Register (Address Offset = 0x0004 + p*0x10)

Bit Name Access Value Description

0 LOCK R 1* PLL lock indication

1 ERROR R 0* PLL error indication

Asserted high to indicate that the PLL was
programmed with an illegal value. The PLL can be re-
programmed after the ERROR status bit is reset to 0

*: Reset value
The values of m and p are:
p=0 m =ARC
p=1 m =SYS
p=2 m =REF

CGU_m_PLL_FMEAS – PLL Measurement Register (Address Offset = 0x0008 + p*0x10)

Bit Name Access Value Description

14:0 RCNT RW 0* Value of the reference counter.

29:15 FCNT R 0* Value of the frequency counter

30 DONE R 0* Asserted high to indicate that the frequency

measurement has completed.

31 START RW1C 0* Writing a 1 to the START bit starts a frequency

measurement.
 Measured frequency = (FCNT / RCNT) * fref
*: Reset value
The values of m and p are:
p=0 m =ARC
p=1 m =SYS
p=2 m =REF

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CGU_m_FB_DIV_CTRL – PLL FB Control Register (Address Offset = 0x000C + p*0x10)

Bit Name Access Value Description

0 BYPASS RW 1* Bypass PLL input divider counter

1 HIGHEDGE RW 0* Force high time counter to transition on a falling edge

(add half a VCO cycle)

3:2 Reserved

9:4 HIGHTIME RW See Set number of VCO cycles that the clock remains high
below** (MHIGH)

11:10 Reserved

17:12 LOWTIME RW See Set number of VCO cycles that the clock remains low
below** (MLOW)

30:18 Reserved *

31 UPDATE RW1C 0* Update the PLL with the configured values

*: Reset value
**: The values of m and p are:
p=0 m =ARC DHIGH=NA DLOW=NA MHIGH=5 MLOW=5 FVCO=1000 MHz
p=1 m =SYS DHIGH=NA DLOW=NA MHIGH=5 MLOW=5 FVCO=1000 MHz
p=2 m =REF DHIGH=NA DLOW=NA MHIGH=5 MLOW=5 FVCO=1000 MHz

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[Link].2 Clock Control and Status Registers

CGU_m_ODIV_c – Clock Divider Register (Address Offset = 0x0080 + p*0x60 + n*0x10)

Bit Name Access Value Description

0 BYPASS RW 0* Bypass PLL input divider counter

1 HIGHEDGE RW 0* Force high time counter to transition on a falling

edge (add half a VCO cycle)

3:2 Reserved

9:4 HIGHTIME RW See below** Set number of VCO cycles that the clock remains
high (OHIGH)

11:10 Reserved

17:12 LOWTIME RW See below** Set number of VCO cycles that the clock remains
low (OLOW)

30:18 Reserved *

31 UPDATE RW1C 0* Update the PLL with the configured values

*: Reset value
**: The values of c, m, n, and p are:
m = ARC p=0 c = ARC ARC HS clock n=0 OHIGH=10 OLOW=10 Fout=50 MHz

c = AHB AHB clock n=0 OHIGH=10 OLOW=10 Fout=50 MHz

m = SYS p=1
c = APB APB clock n=1 OHIGH=10 OLOW=10 Fout=50 MHz

c = SDIO SDIO clock n=0 OHIGH=2 OLOW=3 Fout=200 MHz

c = SPI SPI clock n=1 OHIGH=25 OLOW=25 Fout=20 MHz

c = TIMER TIMER core clock n=2 OHIGH=5 OLOW=5 Fout=100 MHz

m = REF p=2
c = UART UART core clock n=3 OHIGH=5 OLOW=5 Fout=100 MHz

c = EBI EBI core clock n=4 OHIGH=5 OLOW=5 Fout=100 MHz

c = I2C I2C core clock n=5 OHIGH=5 OLOW=5 Fout=100 MHz

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CGU_m_FMEAS_c – Clock Measurement Register (Address Offset = 0x0084 + p*0x60 + n*0x10)

Bit Name Access Value Description

14:0 RCNT RW 0* Value of the reference counter.

29:15 FCNT R 0* Value of the frequency counter

30 DONE R 0* Asserted high to indicate that the frequency

measurement is complete.

31 START W 0* Writing a 1 to the START bit starts a frequency

measurement. The START bit resets to 0 when the
frequency measurement completes:
 Measured frequency = (FCNT / RCNT) * fref

*: Reset value
The values of c, m, and p are:
m = ARC p=0 c = ARC ARC HS clock n=0
c = AHB AHB clock n=0
m = SYS p=1
c = APB APB clock n=1
c = SDIO SDIO clock n=0
c = SPI SPI clock n=1
m = REF p=2 c = TIMER TIMER core clock n=2
c = UART UART core clock n=3
c = EBI EBI core clock n=4

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CGU_AUDIO_FMEAS_c – Clock Measurement Register (Address Offset = 0x01A4 + p*0x10)

Bit Name Access Value Description

14:0 RCNT RW 0* Value of the reference counter

29:15 FCNT R 0* Value of the frequency counter

30 DONE R 0* Asserted high to indicate that the frequency

measurement is complete.

31 START W 0* Writing a 1 to the START bit starts a frequency

measurement. The START bit resets to 0 when the
frequency measurement completes:
 Measured frequency = (FCNT / RCNT) * fref

*: Reset value
The values of c and p are:
p=0 c = I2S I2S audio reference clock
p=1 c = PDM PDM audio reference clock

CGU_AUDIO_IDIV_c – Clock Measurement Register (Address Offset = 0x01A8 + n*0x10)

Bit Name Access Value Description

See below** Integer divide-by-N value

0 Disabled

1 Divide-by-1
7:0 N RW
2 Divide-by-2

… …

255 Divide-by-255
*: Reset value
** The values of c and p are:
p=0 c = I2S I2S audio reference clock
p=1 c = PDM PDM audio reference clock

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[Link].3 Reset Control Registers

CGU_ARC_RST_CTRL – ARC Reset Control Register (Address Offset = 0x380)

Bit Name Access Description

0 ARC_RST RW Reset the ARC clock domain

Value:
 0*: No
 1: Yes
31:1 - RW Reserved; must be written as 0
Value: 0*

*: Reset value

CGU_SYS_RST_CTRL – ARC Reset Control Register (Address Offset = 0x384)

Bit Name Access Description

0 AHB_RST RW Reset the AHB clock domain

Value:
 0*: No
 1: Yes
1 APB_RST RW Reset the APB clock domain
Value:
 0*: No
 1: Yes
31:2 - RW Reserved; must be written as 0
Value: 0*

*: Reset value

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CGU_REF_RST_CTRL – ARC Reset Control Register (Address Offset = 0x388)

Bit Name Access Description

0 SDIO_RST RW Reset the SDIO clock domain

Value:
 0*: No
 1: Yes
1 SPI_RST RW Reset the SPI clock domain
Value:
 0*: No
 1: Yes
2 TIMER_RST RW Reset the timers clock domain
Value:
 0*: No
 1: Yes
3 UART_RST RW Reset the UART clock domain
Value:
 0*: No
 1: Yes
4 EBI_RST RW Reset the EBI clock domain
Value:
 0*: No
 1: Yes
5 I2C_RST RW Reset the I2C clock domain
Value:
 0*: No
 1: Yes
31:6 Reserved RW Reserved; must be written as 0
Value: 0*

*: Reset value

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CGU_SYS_RST_OUT_CTRL – System Reset Output Control Register (Address Offset = 0x3A0)

Bit Name Access Description

0 SYS_RST_OUT RW Toggle external reset output

Value:
 0*: No
 1: Yes
31:1 - RW Reserved; must be written as 0
Value: 0*

*: Reset value

[Link].4 Standard Registers

CGU_IP_SW_RESET – CGU Software Reset Register (Address Offset = 0xFF0)

Bit Name Access Description

0 SW_RESET RW1C Writing a 1 to this bit initiates a software reset of the full
ARC EM Software Development Platform system.

31:16 SW_RESET_DELAY RW Delay between software reset command and reset

assertion.
Value: 0x0000*

*: Reset value

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CGU_ IP_VERSION – CGU Version Register (Address Offset = 0xFF8)

Bit Name Access Description

15:0 MINOR_REV R Minor version of the CGU IP

Value: 0x0000*

31:16 MAJOR_REV R Major version of the CGU IP

Value: 0x0001*

*: Reset value

CGU_ IP_TYPE – CGU Type Register (Address Offset = 0xFFC)

Bit Name Access Description

15:0 ID R IP code
 0x0100 = CGU
Value: 0x1*

31:16 DW R Hex code for the two ASCII letters AD (ARC

Development)
Value: 0x4144*

*: Reset value

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Control Registers
The global control registers inside the ARC EM SDP are implemented by the CREG module.
The global control registers control configuration settings for sub-modules that do not have a
software interface (for example: the GPIO mux). Additionally, the CREG module implements
the following functionality:
 Logic to sample boot mode configuration values from BOOT pins during power-on-
reset
 Logic to generate cpu_start signal for ARC cores
 Logic to generate the software interrupts
 Identification registers for the ARC EM SDP

Table 16 lists the registers for the CREG module, including a brief description and their offset
to the base address of the CREG (0xF000_1000). All the registers are 32 bits wide.
Read/write access to undefined registers is ignored, and an APB error response is generated.
All unused bits within a register are non-writable and return zero when read.

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Table 16 CREG Control Register Overview

Name Address Offset Access [1] Description

Boot Registers

CREG_BOOT 0x0 RW Boot register

CREG_START 0x10 RW Start register

Multiplexer Registers

Arduino MUX
PMOD_MUX_CTRL 0x30 RW
register

ARDUINO_MUX_CTRL 0x34 RW Pmod MUX register

Generic pin header

GENERIC_MUX_CTRL 0x38 RW
MUX register

Standard Registers

CREG IP software
CREG_IP_SW_RESET 0xFF0 RW1C
reset register

CREG IP product
CREG_IP_PRODUCT 0xFF4 R
register

CREG IP version
CREG_IP_VERSION 0xFF8 R
register

CREG IP type
CREG_IP_TYPE 0xFFC R
register
[1] The following access types are defined:

RW Read/Write register
R Read-only register
W Write-only register
RW1C Read-only, Write-1-to-Clear Register

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[Link] Boot Registers

CREG_BOOT – Boot Register (Address Offset = 0x0)

Bit Name Access Description

3:0 Reserved RW

5:4 IMAGE[1] RW Bootloader image location

Value:
 0*: ROM
 1: SPI flash
 2: EBI

6 REDPINE_HOST_IF RW Redpine host interface selection

Value:
 0*: ROM
 1: SPI flash

7 XIP_EN RW Control the XIP_EN pin of the dw_spi_mst1

 0*: XIP not asserted
 1: XIP asserted

8 WP RW Write protect for ROM

 0: No write protect, ROM operates as
RAM
 1*: Write protect enabled

*: Reset value
[1]: Do not attempt to write to EBI_CS_MOD register while access to CS area is in progress.

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CREG_CPU_START – CPU Start Register (Address Offset = 0x10)

Bit Name Access Description

0 START RW1C Writing a 1 to this bit generates a

cpu_start pulse for ARC EM.
Value: 0x0*

3:1 Reserved

4 START_MODE RW Boot start mode

 0x0[1]: Start ARC core manually
(CREG, external start button or
debugger).
 0x1: Start ARC core autonomously
after reset.

8 POL RW Polarity of cpu_start pulse.

Value:
 0x0: Active low
 0x1*: Active high

31:9 Reserved

*: Reset value
[1]: Reset value for START_MODE is sampled from boot_start_mode pin during power-on-reset.

[Link] MUX Registers

PMOD_MUX_CTRL – Pmod Mux Register (Address Offset = 0x30)

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Bit Name Access Description

3:0 PMOD_A_CFG1 RW  GPIO

Value: 0x0*
 I2C
Value: 0x1
 SPI
Value: 0x2
 UART1
Value: 0x3
 UART2
Value: 0x4
 PWM1
Value: 0x5
 PWM2
Value: 0x6
 Reserved
Value: 0x7
7:4 PMOD_A_CFG2 RW  GPIO
Value: 0x0*

11:8 PMOD_B_CFG1 RW  GPIO

Value: 0x0*
 I2C
Value: 0x1
 SPI
Value: 0x2
 UART1
Value: 0x3
 UART2
Value: 0x4
 PWM1
Value: 0x5
 PWM2
Value: 0x6
 Reserved
Value: 0x7

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Bit Name Access Description

15:12 PMOD_B_CFG2 RW  GPIO

Value: 0x0*

19:16 PMOD_C_CFG1 RW  GPIO

Value: 0x0*
 I2C
Value: 0x1
 SPI
Value: 0x2
 UART1
Value: 0x3
 UART2
Value: 0x4
 PWM1
Value: 0x5
 PWM2
Value: 0x6
 Reserved
Value: 0x7
23:20 PMOD_C_CFG2 RW  GPIO
Value: 0x0*

*: Reset value

ARDUINO_MUX_CTRL – ARDUINO Mux Register (Address Offset = 0x34)

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Bit Name Access Description

3:0 ARDUINO_CFG0 RW  I/O-1

Value: 0x0*
 I/O-2
Value: 0x1

7:4 ARDUINO_CFG1 RW  I/O-1

Value: 0x0*
 I/O-2
Value: 0x1

11:8 ARDUINO_CFG2 RW  I/O-1

Value: 0x0*
 I/O-2
Value: 0x1

15:12 ARDUINO_CFG3 RW  I/O-1

Value: 0x0*
 I/O-2
Value: 0x1

19:16 ARDUINO_CFG4 RW  I/O-1

Value: 0x0*
 I/O-2
Value: 0x1

23:20 ARDUINO_CFG5 RW  I/O-1

Value: 0x0
 I/O-2
Value: 0x1
 I/O-3
Value: 0x2
 I/O-4
Value: 0x3
 I/O-5
Value: 0x4

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Bit Name Access Description

27:24 ARDUINO_CFG6 RW  I/O-1

Value: 0x0*
 I/O-2
Value: 0x1
*: Reset value

GENERIC_MUX_CTRL – Generic Mux Register (Address Offset = 0x38)

Bit Name Access Description

3:0 GENERIC_CFG0 RW  GPIO

Value: 0x0*
 EBI
Value: 0x1
 HOST-IF
Value: 0x2
 DBG
Value: 0x3
*: Reset value

[Link] Standard Registers

CREG_IP_SW_RESET – CREG Software Reset Register (Address Offset = 0xFF0)

Bit Name Access Description

0 RESET RW1C Software reset.

Writing a 1 to this bit initiates a software
reset of all IP. After initiating the software
reset, software can read the software reset
register and when the read completes,
software can determine that the IP has
been reset.

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CREG_ IP_PRODUCT – CREG Product Register (Address Offset = 0xFF4)

Bit Name Access Description

31:0 PRODUCT NAME R Hex code for the two ASCII letters ARC EM
Software Development Platform (ESDP)
Value: 0x45534450

CREG_ IP_VERSION – CREG Version Register (Address Offset = 0xFF8)

Bit Name Access Description

15:0 MINOR_REV R Minor version of the ARC EM SDP

Value: 0x0000*
31:16 MAJOR_REV R Major version of the ARC EM SDP
Value: 0x0001*
*: Reset value

CREG_ IP_TYPE – CREG Type Register (Address Offset = 0xFFC)

Bit Name Access Description

15:0 ID R IP code
 0x0200 = CREG
Value: 0x0200*

31:16 DW R Hex code for the two ASCII letters ARC

Development (AD)
Value: 0x4144*

*: Reset value

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EBI Registers

Name Address Offset Access[1] Description

EBI_CS_MOD 0x002 RW CS mode register

EBI_CS_WCR1 0x004 RW CS wait control register 1

EBI_CS_WCR2 0x008 RW CS wait control register 2

EBI_CS_CR 0x802 RW CS control register

EBI_CS_REC 0x80A RW CS recovery cycle register

CS recovery cycle insertion

EBI_CS_RECEN 0x880 RW
enable register

[1]: The following access types are defined:

RW Read/Write register
R Read-only register
W Write-only register
RW1C Read-only, Write-1-to-Clear Register

[Link] EBI Registers

EBI_CS_MOD – CS Mode Register (Address Offset = 0x002)

Bit Name Access Description

0 WRMOD RW Write access mode select

Value:
 0x0*: Byte strobe mode
 0x1: Single write strobe mode

3 EWENB RW External wait enable/disable

Value:
 0x0*: Disabled
 0x1: Enabled

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Bit Name Access Description

8 PRENB RW Page read access enable/disable

Value:
 0x0*: Disabled
 0x1: Enabled

9 PWENB RW Page write access enable/disable

Value:
 0x0*: Disabled
 0x1: Enabled

15 PRMOD RW Page read access mode select

Value:
 0x0*: Normal access compatible mode
 0x1: External data read continuous assertion
mode
*: Reset value
[1]: Do not attempt to write to EBI_CS_MOD register while access to CS area is in progress.

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EBI_CS_WCR1 – CS Wait Control Register 1 (Address Offset = 0x004)

Bit Name Access Description

2:0 CSPWWAIT RW Page write cycle wait time

[2]
Value:
 0x0: No wait is inserted
 0x1: Wait time is 1 EBI clock cycle
 …. ………………………………..
 0x7*: Wait time is 7 EBI clock cycles

10:8 CSPRWAIT RW Page read cycle wait time

[3]
Value:
 0x7*

20:16 CSWWAIT RW Normal write cycle wait time

Value:
 0x1F*

28:24 CSRWAIT RW Normal read cycle wait time

Value:
 0x1F*

*: Reset value
[1]: Do not attempt to write to the EBI_CS_WCR1 register while the external bus is being accessed.
[2]: The CSPWWAIT value is only valid when PWENB bit in EBI_CS_MOD is set to 1.
[3]: The CSPRWAIT value is only valid when PRENB bit in EBI_CS_MOD is set to 1.

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EBI_CS_WCR2 – CS Wait Control Register 2 (Address Offset = 0x008)

Bit Name Access Description

2:0 CSROFF RW Read access CS extension cycles

Value:
 0x0: No wait is inserted
 0x1: Wait duration is 1 EBI clock
cycle
 0x2: Wait duration is 2 EBI clock
cycles
 ….
…………………………………
…...
 0x7*: Wait duration is 7 EBI clock
cycles
6:4 CSWOFF RW Write access CS extension cycles
Value:
 0x0*
10:8 WDOFF RW Write data output extension cycles
Value:
 0x0*
13:12 AWAIT RW Address cycle wait time
Value:
 0x0*
18:16 RDON RW RD assert wait time
Value:
 0x7*
22:20 WRON RW WR assert wait time
Value:
 0x7*

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Bit Name Access Description

26:24 WDON RW Write data output wait time

Value:
 0x0*

30:28 CSON RW CS assert wait time

Value:
 0x0*

*: Reset value
[1]: Do not attempt to write to EBI_CS_WCR2 register while the external bus is being accessed.

EBI_CS_CR – CS Control Register (Address Offset = 0x802)

Bit Name Access Description

0 EXENB RW Operation enable / disable

Value:
 0x0: Disabled
 0x1*: Enabled

5:4 BSIZE R External bus width select

Value:
 0x2*: 8-Bit

8 EMODE RW Endian mode

Value:
 0x0*: Little endian
 0x1: Big endian

12 MPXEN R Address/data bus multiplex mode

Value:
 0x0*: Separate address/data bus

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Bit Name Access Description

*: Reset value
[1]: Do not attempt to write to EBI_CS_CR register while the external bus is being accessed.

EBI_CS_REC – CS Recovery Control Register (Address Offset = 0x80A)

Bit Name Access Description

3:0 RRCV RW Read recovery cycles

Value:
 0x0*: No recovery cycle is inserted
 0x1: One recovery cycle
 0x2: Two recovery cycles
 …. ……………………………………...
 0x7: Seven recovery cycles

11:8 WRCV RW Write recovery cycles

Value:
 0x0*

*: Reset value
[1]: Do not attempt to write to EBI_CS_REC register while the external bus is being accessed.

EBI_CS_RECEN – CS Recovery Insertion Enable Register (Address Offset = 0x880)

Bit Name Access Description

0 RCVEN RW Separate bus recovery cycle insertion enable

Value:
 0x0*: Disabled
 0x1: Enabled

*: Reset value
[1]: Do not attempt to write to EBI_CS_RECEN register while the external bus is being accessed.

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 Glossary and References
This chapter contains a list of specific terms used in this document and references for
further reading.

Glossary
AHB
Advanced High Performance Bus
CRU
Clock Reset Unit
GPIO
General Purpose Input/Output
HW
Hardware
I 2S
Inter-IC Sound, serial bus interface standard for the transfer of audio data
JTAG
Joint Test Action Group
R
Read-only register
RW
Read-write register
RW1C
Read-write register; writing a one clears the corresponding bit
PSRAM
Pseudo Static Random Access Memory
SRAM
Static Random Access Memory
SW
Software

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References
1. Xilinx Kintex-7 data sheet:
[Link]
a_Sheet.pdf

2. MikroBUS Standard Specification:

[Link]
[Link]

3. 8-input 8-bit ADC088S022: [Link]

4. FTDI Chip FT2232H Data sheet:

[Link]

5. Dual I2S Stereo Audio Codec MAX9880A:

[Link]

6. DesignWare® MetaWare Debugger User’s Guide for ARC®:

[Link]
.pdf

7. DesignWare DW_apb_gpio Databook:

[Link]

8. DesignWare ARC EM Series Databook:

[Link]
C_EM_Databook.pdf

9. DesignWare ARCv2 ISA Programmer’s Reference Manual for ARC EM

Processors:
[Link]
C_V2_ProgrammersReference.pdf

10. DesignWare DWC Mobile Storage Host Databook:

[Link]

11. DesignWare DW_apb_uart Databook:

[Link]
_databook.pdf

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12. DesignWare DW_apb_ssi Databook:

[Link]
[Link]

13. DesignWare DW_apb_timers Databook:

[Link]
mers_databook.pdf

14. DesignWare DWC_trng_nist Databook:

[Link]
nist_sp800_90c_databook.pdf

15. DesignWare DW_apb_wdt Databook:

[Link]
_databook.pdf

16. DesignWare ARC Data Fusion IP Subsystem I/O Databook:

[Link]
c/DataFusionSubsystem_IO_Databook.pdf

17. DesignWare Smart Sensor and Control IP Subsystem I/O Databook:

[Link]
sorSubsystem_IO_Databook.pdf

18. Redpine Signals RS9113-WiseConnect-API-Guide-v1.7.1:

[Link]

19. Xilinx AXI EMC:

[Link]
[Link]

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