MULTITASKING

Multitasking
⚫ To provide efficient, protected multitasking, the 80386
employs several special data structures.
⚫ It does not, however, use special instructions to control
multitasking; instead, it interprets ordinary
control-transfer instructions differently when they
refer to the special data structures.
The registers and data structures that support multitasking
are:
Task state segment
Task state segment descriptor
Task register
Task gate descriptor
⚫ With these structures the 80386 can rapidly
switch execution from one task to another,
saving the context of the original task so that the
task can be restarted later.
In addition to the simple task switch, the 80386
offers two other task-management features:

1. Interrupts and exceptions can cause task switches (if

needed in the system design).
2. With each switch to another task, the 80386 can also
switch to another LDT and to another page
directory.
 TSS
All the information the processor
needs in order to manage a task is
stored in a special type of segment, a
task state segment (TSS)
The fields of a TSS belong to two
classes:
1. A dynamic set that the processor updates with each switch from the task. This set
includes the fields that store:
1. The general registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI).
2. The segment registers (ES, CS, SS, DS, FS, GS).
3. The flags register (EFLAGS).
4. The instruction pointer (EIP).
5. The selector of the TSS of the previously executing task (updated only when a
return is expected).
2. A static set that the processor reads but does not change. This set includes the fields
that store:
1. The selector of the task's LDT.
2. The register (PDBR) that contains the base address of the task's page directory
(read only when paging is enabled).
3. Pointers to the stacks for privilege levels 0-2.
4. The T-bit (debug trap bit) which causes the processor to raise a debug exception
when a task switch occurs
5. The I/O map base
 TSS Descriptor

The B-bit in the type field indicates whether the task is busy.
The BASE, LIMIT, and DPL fields and the G-bit and P-bit have
functions similar to their counterparts in data-segment
descriptors
 TASK Register
The task register (TR) identifies the currently executing task by pointing to the
TSS.
The processor uses
the invisible portion
to cache the base
and limit values
from the TSS
descriptor.

The selector in the visible

portion selects a TSS
descriptor in the GDT.
 TASK Register Instructions
⚫ LTR (Load task register)
⚫ loads the visible portion of the task register.
⚫ loads the invisible portion with information from the TSS
descriptor selected by the operand.
⚫ LTR is a privileged instruction; it may be executed only
when CPL is zero.
⚫ LTR is generally used during system initialization to give an
initial value to the task register; thereafter, the contents of
TR are changed by task switch operations.
⚫ STR (Store task register) stores the visible portion of
the task register in a general register or memory word.
STR is not privileged.
TASK GATE Descriptor
A task gate descriptor provides an indirect, protected reference to a TSS.
TASK GATE Descriptor
⚫ The SELECTOR field of a task gate must
refer to a TSS descriptor. The value of the
RPL in this selector is not used by the
processor.
⚫ The DPL field of a task gate controls the
right to use the descriptor to cause a task
switch.
 TASK GATE Descriptor
⚫ Condition to access gate: maximum of the
selector's RPL and the CPL of the procedure is
numerically less than or equal to the DPL of the
descriptor.
⚫ Note: when a task gate is used, the DPL of the
target TSS descriptor is not used for privilege
checking.
⚫ several task gates that select the single TSS
descriptor.
⚫ The need to provide selective access to tasks.
⚫ The need for an interrupt or exception to
cause a task switch.
 TASK Switching
⚫ Checking that the current task is allowed to switch to
the designated task.
DPL of TSS Decsriptor<= max(RPL of gate, CPL)
⚫ Checking that the TSS descriptor of the new task is
marked present and has a valid limit.
⚫ Saving the state of the current task.
⚫ Loading the task register with the selector of the
incoming task's TSS descriptor, marking the incoming
task's TSS descriptor as busy, and setting the TS (task
switched) bit of the MSW.
⚫ Loading the incoming task's state from its TSS and
resuming execution.
Note It…..
⚫ Every task switch sets the TS (task switched)
bit in the MSW (machine status word).

⚫ The new task begins executing at the privilege

level indicated by the RPL of the CS selector
value that is loaded from the TSS.
 TASK Linking
⚫ The back-link field of the TSS and the NT (nested task)
bit of the flag word together allow the 80386 to
automatically return to a task that CALLed another task or
was interrupted by another task.

⚫ The NT flag indicates whether the back-link field is valid.

⚫ If NT is set, the 80386 switches back to the task selected

by the back-link field.
 Busy Bit (Prevents Loop)
⚫ When switching to a task, the processor automatically
sets the busy bit of the new task.

⚫ When switching from a task, the processor automatically

clears the busy bit of the old task if that task is not to be
placed on the back-link chain , If the task is placed on the
back-link chain, its busy bit remains set.

⚫ When switching to a task, the processor signals an exception

if the busy bit of the new task is already set.
TASK Address Space
⚫ The LDT selector and PDBR fields of the TSS
give software systems designers flexibility in
utilization of segment and page mapping
features of the 80386.
⚫ Task Linear-to-Physical Space Mapping
Task Logical Address Space
To share data, tasks must also have a common
logical-to-linear space mapping; i.e., they must also have
access to descriptors that point into a shared linear
address space.
⚫ Via the GDT -All tasks have access to the descriptors in
the GDT. If those descriptors point into a linear-address
space that is mapped to a common physical-address space
for all tasks, then the tasks can share data and
instructions.
⚫ By sharing LDTs - Two or more tasks can use the same
LDT if the LDT selectors in their TSSs select the same
LDT segment.
⚫ By descriptor aliases in LDTs. - It is possible for
certain descriptors of different LDTs to point to the same
linear address space.
Virtual Mode – Features, Memory
management in Virtual Mode ,
Entering and leaving Virtual mode.
Virtual Mode
⚫ The 80386 supports execution of one or
more 8086, 8088, 80186, or 80188
programs in an 80386 protected-mode
environment
⚫ The purpose of a V86 task is to form a
"virtual machine" with which to execute
an 8086 program
⚫ V86 tasks take advantage of the hardware
support of multitasking offered by the
protected mode
 Virtual Mode
⚫ The hardware provides a virtual set of registers (via the TSS),
a virtual memory space (the first megabyte of the linear
address space of the task), and directly executes all
instructions that deal with these registers and with this
address space.

⚫ The software controls the external interfaces of the virtual

machine (I/O, interrupts, and exceptions) in a manner
consistent with the larger environment in which it executes.

⚫ In the case of I/O, software can choose either to emulate I/O

instructions or to let the hardware execute them directly
without software intervention.
Entering and Leaving V86
Mode
 Entering and Leaving V86
Mode
⚫ A task switch to an 80386 task loads the image of EFLAGS from the
new TSS.
⚫ The TSS of the new task must be an 80386 TSS, not an 80286 TSS,
because the 80286 TSS does not store the high-order word of
EFLAGS, which contains the VM flag.
⚫ A value of one in the VM bit of the new EFLAGS indicates that the
new task is executing 8086 instructions; therefore, while loading the
segment registers from the TSS, the processor forms base addresses
as the 8086 would.
⚫ An IRETAn IRET from a procedure of an 80386 task loads the image
of EFLAGS from the stack. A value of one in VM in this case indicates
that the procedure to which control is being returned is an 8086
procedure. The CPL at the time the IRET is executed must be zero,
else the processor does not change VM.