DLD Mockup Questions and Answer

Try the following questions by your own and then cross check yours with answers at the end

1. The term bit means

A. A small amount of data
B. A 1 or a 0
C. Binary digit
D. B and C
2. An inverter
A. Performs the NOT operation
B. Changes a LOW to a HIGH
C. Performs a complementation
D. All
3. The output of an OR gate is not HIGH when
A. Any input is HIGH
B. All inputs are HIGH
C. No inputs are HIGH
D. A and B
4. The device used to convert a binary number to a 7-segment display format
A. Multiplexer
B. Encoder
C. Decoder
D. Register
5. The decimal number -34 is expressed in the 2’s complement form as
A. 01011110
B. 10100010
C. 11011110
D. 01011101
6. A single-precision floating point binary numbers has a total of
A. 8 bits
B. 16 bits
C. 24 bits
D. 32 bits
7. The binary equivalent of the hexadecimal number 𝐹7𝐴916
A. 1111011110101001
B. 1110111110101001
C. 1111111010110001
D. 1111011010101001

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 DLD Mockup Questions and Answer

8. The Binary coded decimal(BCD) equivalent of the decimal number 473 is

A. 111011010
B. 110001110011
C. 010001110011
D. 01001111011
9. A pulse is applied to each input of an exclusive-OR gate. One pulse goes HIGH at t=0
and goes back LOW at t=1 millisecond. The other pulse goes HIGH at t= 0.8 millisecond
and goes back LOW at t=3 millisecond. The output pulse can be described as
A. It goes HIGH at t=0 and back LOW at t= 3 millisecond.
B. It goes HIGH at t=0 and back LOW at t= 0.8 millisecond.
C. It goes HIGH at t=1 millisecond and back LOW at t= 3 millisecond
D. B and C
10. A positive going pulse is applied to an inverter. The time interval from the leading edge
of the input to the leading edge of the output is 7 ns. This parameter is
A. Speed-power product
B. Propagation delay, 𝑡𝑃𝐻𝐿
C. Propagation delay, 𝑡𝑃𝐿𝐻
D. Pulse width
11. The domain of the expression ABCD + AB + CD + B is
A. A and D
B. B only
C. A, B, C and D
D. None
12. Which one of the following is not a valid rule of Boolean algebra?
A. A + 1 = 1
B. A’ = A
C. A A = A
D. A + 0 = A
13. Which of the following rules states that if one input of an AND gate is always 1, the
output is equal to the other input?
A. A + 1 = 1
B. A + A = A
C. A . A = A
D. A . 1 = A

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 DLD Mockup Questions and Answer

14. According to DeMorgan’s theorems, the following equality(s) is(are) correct:

A. (AB)’ = A’ + B’
B. (XYZ)’ = X’ + Y’ + Z’
C. (A + B + C)’ = A’ B’ C’
D. All
15. The Boolean expression X = AB + CD represents
A. Two ORs ANDed together
B. a 4- input AND gate
C. two ANDs ORed together
D. an exclusive- OR
16. In a 4- variable Karnaugh map, a 2-variable product term is produced by
A. a 2- cell group of 1𝑠
B. an 8- cell group of 1𝑠
C. a 4- cell group of 1𝑠
D. a 4- cell group of 0𝑠
17. on a Karnaugh map, grouping the 0𝑠 produces
A. a product –of- sums expression
B. a sum –of- products expression
C. a “don’t care” condition
D. AND-OR logic
18. A 5- variable Karnaugh map has
A. Sixteen cells
B. Thirty-two cells
C. Sixty-four cells
D. Eight cells
19. A logic circuit with an output X = A’ B C + A C’ consists of
A. Two AND gates and one OR gate
B. Two AND gates, one OR gate and two inverters
C. Two OR gates, one AND gate and two inverters
D. Two AND gates, one OR gate and one inverter
20. Select the work of Shift registers from the following?
A. Shifting
B. Rotating
C. adding
D. both A and B
21. All Boolean expressions can be implemented with
A. NAND gates only
B. NOR gates only
C. Combinations of NAND and NOR gates
D. Combinations of AND gates, OR gates and inverters
E. Any of these

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 DLD Mockup Questions and Answer

22. A full adder is characterized by

A. Two inputs and two outputs
B. Three inputs and two outputs
C. Two inputs and three outputs
D. Two inputs and one output
23. To expand a 4-bit parallel adder to an 8-bit parallel adder, you must
A. Use four 4-bit adders with no interconnections
B. Use two 4-bit adders and connect the sum outputs of one to the bit inputs of the
other
C. Use eight 4-bit adders with no interconnections
D. Use two 4-bit adders with the carry output of one connected to the carry input of
the other
24. A multiplexer has
A. One data input, several data outputs and selection inputs
B. One data input, one data output and one selection input
C. several data inputs, several data outputs and selection inputs
D. several data inputs, one data output and selection inputs
25. if an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to
0, the latch will be
A. set
B. reset
C. invalid
D. clear
26. The flip-flop belongs to a category of the logic circuits known as
A. Monostable multivibrator
B. Bistable multivibrators
C. Astable multivibrators
D. One-shots
27. The purpose of the clock inputs to a flip-flop is to
A. Clear the device
B. Set the device
C. Always cause the output to change states
D. Cause the output to assume a stable dependent on the controlling (S-R, J-K, or
D) inputs
28. A flip-flop is in the toggle condition when
A. J = 1, K = 0
B. J = 1, K = 1
C. J = 0, K = 0
D. J = 0, K = 1

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 DLD Mockup Questions and Answer

29. A J-K flip-flop with J = 1 and K = 1 has a 10 kHz clock input. The Q output is
A. Constantly HIGH
B. Constantly LOW
C. A 10kHz square wave
D. A 5kHz square wave
30. A one-shot is a type of
A. Monostable multivibrator
B. Astable multivibrator
C. Timer
D. A and C
E. B and C
31. The output pulse width of a non-retriggerable one-shot depends on
A. The trigger interval
B. The supply voltage
C. a resistor and capacitor
D. the threshold voltage
32. An astable multivinrator
A. Requires a periodic trigger input
B. has no stable state
C. is an oscillator
D. produces a periodic pulse output
E. A, B, C and D
F. B, C and D
33. The decimal equivalent of an octal number 234.32 is
A. 156.15625
B. 156.15265
C. 156.2562
D. 156.1554
34. The initial state of MOD-16 down counter is 011. After 37 clock pulses, the state of the
counter will be
A. 1011
B. 0110
C. 0101
D. 0001

35. The basic logic gates are

A. AND, OR, NAND
B. NAND, NOR
C. AND, OR, NOT
D. AND, NOR, NAND

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 DLD Mockup Questions and Answer

36. The difference between a half-adder and a full-adder is

A. The half adder is having a carry input
B. The full adder is not having a carry input
C. The half added does not have a carry input
D. None
37. Edge triggered flip-flops are
A. Synchronous inputs
B. Bistable with synchronous inputs
C. Bistable with asynchronous inputs
D. None
38. A register capable of incrementing and/or decrementing its contents
A. Counter
B. Decoder
C. Multiplexer
D. Demultiplexer
39. Original ASCII coding scheme uses bits for coding 128 different characters.
A. 6 B. 7 C. 8 D. 16
40. Which coding scheme is used in computer to represent data internally
A. Decimal B. octal C. Binary D. hexadecimal
41. A device which converts BCD to seven segment is called
A. Encoder
B. Decoder
C. Multiplexer
D. none of these
42. A decade counter skips
A. binary states 1000 to 1111
B. binary states 0000 to 0011
C. binary states 1010 to 1111
D. binary states 1111 to higher

43. For the gate in the given figure 1 below the output will be

figure 1

A. 0 B. 1 C. A D. A’

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 DLD Mockup Questions and Answer

44. The circuit of the given figure 2 realizes the function

Figure 2

A. Y = (A’ + B’) C + (DE)’

B. Y = A’ + B’ + C’ + D’ + E’
C. Y = AB + C +DE
D. Y = AB + C (D + E)
45. In a ripple counter
A. whenever a flip flop sets to 1, the next higher Flip-Flop toggles
B. whenever a flip flop sets to 0, the next higher Flip-Flop remains unchanged
C. whenever a flip flop sets to 1, the next higher Flip-Flop faces race condition
D. whenever a flip flop sets to 0, the next higher Flip-Flop faces race condition
46. A full adder can be made out of
A. two half adders
B. two half adders and a OR gate
C. two half adders and a NOT gate
D. three half adders

47. The counter in the given figure 3 below is

Figure 3
A. Mod 3
B. Mod 6
C. Mod 7
D. Mod 8

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 DLD Mockup Questions and Answer

48. For the K map in the given table 1 below the simplified Boolean expression is

Table 1
A. A’C’ + A’D’ + ABC
B. AB’D + BC
C. AC’D + AC
D. AC’D + AC + BC
49. In a D latch
A. data bit D is fed to S input and D to R input
B. data bit D is fed to R input and D to S input
C. data bit D is fed to both R and S inputs
D. data bit D is not fed to any input
50. Which of these are universal gates?
A. Only NOR
B. Only NAND
C. Both NOR and NAND
D. NOR, NAND, OR
51. In a three input AND gate A = 1, B = 1, C = 0 The output Y =
A. ABC
B. A’BC
C. AB’C
D. ABC
52. As the number of flip flops are increased, the total propagation delay of
A. ripple counter increases but that of synchronous counter remains the same
B. both ripple and synchronous counters increase
C. both ripple and synchronous counters remain the same
D. ripple counter remains the same but that of synchronous counter increases
53. Which one of the following can be used as parallel to series converter?
A. Decoder
B. Digital counter
C. Multiplexer
D. DeMultiplexer

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 DLD Mockup Questions and Answer

54. The control logic for a binary multiplier is specified by a states diagram. The state diagram
has four states and two inputs. To implement it by the sequence register and decoder
method.
A. two flip-flop & 2 x 4 decoder are needed
B. four flip-flop & 2 x 4 decoder are needed
C. two flip-flop & 3 x 9 decoder are needed
D. four flip-flop & 3 x 9 decoder are needed

55. The total amount of memory is depending upon

A. The organization of memory

B. The size of the address bus of the microprocessor
C. The size of the decoding unit
D. The structure of memory

56. For every possible combination of logical states in the inputs, which table shows the
logical state of a digital circuit output?
A. Function table
B. ASCII table
C. Truth table
D. Routing table

57. Time delay device is memory element of

A. asynchronous circuits
B. synchronous circuits
C. clocked flip-flops
D. Unlocked flip-flops

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 DLD Mockup Questions and Answer

Answer
1. D
2. D
3. C
4. C
5. C
6. D
7. A
8. C
9. D
10. B
11. C
12. B
13. D
14. D
15. C
16. C
17. A
18. B
19. B
20. D
21. E
22. B
23. D
24. D
25. A
26. B
27. D
28. B
29. D
30. D
31. C
32. F
33. A
34. C
35. C
36. C
37. B
38. A
39. B
40. C
41. B
42. C

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 DLD Mockup Questions and Answer

43. D
44. A
45. A
46. B
47. B
48. A
49. A
50. C
51. D
52. A
53. C
54. A
55. B
56. C
57. A

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