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SystemVerilog Problems

The document presents a series of SystemVerilog snippet problems for practice, covering various topics such as FIFO module design, class creation with random constraints, interface connections, functional coverage with covergroups, class inheritance, scoreboard implementation, unique value constraints, transaction-level classes, handshake protocol assertions, and random array constraints. Each problem includes a task that challenges the reader to implement specific functionality or logic. This serves as a comprehensive guide for practicing SystemVerilog concepts and techniques.

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gona deepika
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68 views3 pages

SystemVerilog Problems

The document presents a series of SystemVerilog snippet problems for practice, covering various topics such as FIFO module design, class creation with random constraints, interface connections, functional coverage with covergroups, class inheritance, scoreboard implementation, unique value constraints, transaction-level classes, handshake protocol assertions, and random array constraints. Each problem includes a task that challenges the reader to implement specific functionality or logic. This serves as a comprehensive guide for practicing SystemVerilog concepts and techniques.

Uploaded by

gona deepika
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SystemVerilog Snippet Problems for Practice

1. Build a Parameterized FIFO Module


module fifo #(parameter DEPTH = 8, WIDTH = 8) (
input logic clk, rst_n,
input logic wr_en, rd_en,
input logic [WIDTH-1:0] din,
output logic [WIDTH-1:0] dout,
output logic full, empty
);
// Complete FIFO logic here
endmodule

Task: Implement write, read, full, and empty logic.

2. Create a Class with Random Constraints


class Packet;
rand bit [7:0] addr;
rand bit [7:0] data;

constraint valid_range {
addr inside {[8'h00:8'h7F]};
data % 2 == 0;
}
endclass

Task: Randomize 10 packets with valid constraints and print their contents.

3. Interface-based DUT Connection


interface bus_if(input bit clk);
logic [7:0] data;
logic valid, ready;
endinterface

Task: Connect the above interface to a DUT module and drive data using a testbench.

4. Use Covergroup for Functional Coverage


covergroup cg;
coverpoint data {
bins even = {[0:255]} with (item % 2 == 0);
bins odd = {[0:255]} with (item % 2 == 1);
}
endgroup

Task: Write a generator to stimulate both even and odd cases using randomized values.
SystemVerilog Snippet Problems for Practice

5. Class Inheritance with Virtual Methods


class Base;
virtual function void display(); endfunction
endclass

class Child extends Base;


function void display(); $display("In Child Class"); endfunction
endclass

Task: Create a polymorphic array of Base class objects calling display().

6. Build a Scoreboard to Compare Expected and Actual


class Scoreboard;
mailbox exp_mb, act_mb;

task compare();
forever begin
exp_mb.get(exp_pkt);
act_mb.get(act_pkt);
if (exp_pkt != act_pkt)
$display("Mismatch!");
else
$display("Match!");
end
endtask
endclass

Task: Complete the compare method for basic functional checking.

7. Write a Constraint to Avoid Duplicate Values


class UniqueGen;
rand bit [3:0] val1, val2, val3;

constraint unique_vals {
val1 != val2;
val2 != val3;
val1 != val3;
}
endclass

Task: Randomize and print values ensure they are all unique.

8. Build a Transaction-Level Class with Copy Method


class Transaction;
rand bit [7:0] addr, data;
SystemVerilog Snippet Problems for Practice

function Transaction copy();


Transaction t = new();
t.addr = this.addr;
t.data = this.data;
return t;
endfunction
endclass

Task: Create a transaction object, copy it, and show both contents.

9. Add Assertions to a Handshake Protocol


property handshake_check;
@(posedge clk) disable iff(!rst_n)
req |=> ##[1:3] ack;
endproperty

assert property (handshake_check);

Task: Add an assertion to ensure ack comes within 1 to 3 cycles after req.

10. Random Array with Sum Constraint


class SumArray;
rand bit [7:0] arr[5];

constraint total_sum {
(arr.sum() with (int'(item))) inside {[50:100]};
}
endclass

Task: Randomize the array multiple times and ensure sum is within range.

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