Master Clock Time Slave Clock Time

t1 SYNC message
Data at
Slave Clock

FOLLOW_UP message t2 (t1), t2

containing true value of t1

t1, t2
 DELAY_REQ message
t3 t1, t2, t3

DELAY_RESP message
t4 containing value of t4

time t1, t2, t3, t4

 Figure 1: PTP Message Exchange


  

Time Interval Error

0
Time

 

 


0.1

Time Error

Max|TE|
0.01
dTE
Observation interval [s]
cTE
0
Time
 


 


switch/routers
containing a PTP BC

PTP PTP
GM Slave
Full Timing Support (G.8275.1):
Every switch/router on the path between GM
and slave contains a PTP Boundary Clock

PTP Slave (ordinary clock) PDV Accumulation

ordinary switch/routers

PTP PTP
GM Slave
PTP with Boundary Clocks Partial Timing Support (G.8275.2):
Not all switch/routers on the path between GM
and slave contain a PTP Boundary Clock

Figure 5: Full and Partial Timing Support

BCs recover and regenerate the PTP clocking

– minimizing PDV accumulation at the Slave

PTP with Transparent Clocks

PDV is written by
each TC into
correctionField and
this accumulates,
so correctionField = End Slave removes
PDV accumulation PDV accumulation
at the End Slave using correctionField
 

G.8271.1 Network Reference Points

±100ns A, B C D
(PRTC/T-GM)
±200ns dTE
(random network
variation) ±250ns cTE
±550ns cTE (link asymmetry
(node asymmetry, ±50ns per node) compensation)

Class A T-BCs:

±250ns
Class B T-BCs:
(short term holdover)
±420ns cTE ±380ns cTE ±150ns
(21 nodes, ±20ns per node) (link asymmetry (end application)
compensation)

±1.1µs network equipment budget

±1.5µs end-to-end budget
  

Master Port Slave Port

Higher layers Higher layers

MAC layer MAC layer

MAC/PHY Interface
(MII, GMII, SGMII etc.)

PHY PHY
Medium Dependent
Interface (MDI)

Medium (Cu, fiber)

Master Test
REF
Port Port

A T1
MS
B
2
3
C
SM

D T4

 

 




 

 