ENGR-5396EL-03: Quality Planning and Analysis

QUALITY IMPROVEMENT IN ELECTRONICS

MANUFACTURING: Reducing Cost of Poor Quality
(COPQ) Using DMAIC

Submitted to: Seyma P. Uslu

ENGR-5396EL-03: Quality Planning and Analysis

Presented by:

Meet Ghadiyali (0460623)

Hiren Savani (0445095)

Trunalkumar Patel (0462218)

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ENGR-5396EL-03: Quality Planning and Analysis

1. Introduction

In the competitive field of electronics manufacturing, product reliability and consistency

are critical. This case study focuses on a German company producing printed circuit
boards (PCBs), which encountered high Cost of Poor Quality (COPQ) due to internal
process inefficiencies and supplier defects. Key issues included cold solder joints,
incorrect placements, and poor incoming material quality.

To address these concerns, the Six Sigma DMAIC framework (Define, Measure,
Analyze, Improve, Control) was applied. Using tools like FMEA and Design of
Experiments (DOE), the team identified root causes, optimized soldering parameters,
and improved supplier collaboration—resulting in measurable cost savings and improved
product quality.

2. Define Phase

Objective:
To reduce monthly COPQ by minimizing rework, scrap, warranty returns, and inspection
failures. The primary drivers of poor quality were traced to supplier component defects,
inconsistent soldering practices, and inadequate inspection coverage.

Problem Statement:
Defect rates had reached 8%, leading to monthly losses exceeding $80,000. Quality-
related delays were also compromising delivery schedules.

Scope of Work:
The study covered the entire production process—from incoming material inspection,
soldering, functional testing, to packaging—excluding R&D and marketing.

Voice of the Customer (VOC):

• “We expect defect-free boards ready for integration.”

• “Field failures cost us time and brand reputation.”
• “Please reduce the number of DOA (dead on arrival) units.”

Critical-to-Quality (CTQ) Characteristics:

• No soldering defects (bridging, cold joints)

• On-time delivery
• Board flatness and correct dimensions
• Zero customer returns within 30 days

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ENGR-5396EL-03: Quality Planning and Analysis

3. Measure Phase

Purpose:
To establish a baseline of current performance, quantify COPQ, and understand the scale
of the problem using data from internal audits, production logs, and customer returns.

Collected Data (Monthly):

• Units produced: 20,000 PCBs

• Rework cases: 1,200 (6%) × $15 = $18,000
• Scrap units: 400 (2%) × $50 = $20,000
• Customer returns: 400 (2%) × $70 = $28,000
• Inspection & testing: $8,000
• Prevention training programs: $5,000

COPQ Summary:

Total COPQ=$18,000+$20,000+$28,000+$8,000+$5,000=$79,000/month

Process Metrics Recorded:

• Defect per million opportunities (DPMO)

• First pass yield (FPY)
• Mean time between failures (MTBF)
• Rework rate over time

Insight:
The majority of defects originated from poor incoming materials and manual soldering
operations. The lack of standardized inspection and inconsistent operator techniques also
contributed to internal failures.

4. Analyze Phase

Objective:
To determine the root causes of high defect rates using FMEA, Pareto analysis, and
cause-effect diagrams.

Failure Mode and Effects Analysis (FMEA):

Process Step Failure Mode Cause S O D RPN

Material Receiving Wrong part/specs Supplier mislabeling 7 6 7 294
Soldering Cold joints Low temp, poor training 8 6 6 288
Testing False negatives Incomplete coverage 6 5 5 150

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ENGR-5396EL-03: Quality Planning and Analysis

Process Step Failure Mode Cause S O D RPN

Assembly Wrong placement Manual error 7 4 5 140

Analysis Summary:

• Highest RPNs were linked to incoming material and manual soldering.

• Root causes: unverified components, no temperature standards, lack of operator
training.

Corrective Action Priorities:

• Introduce supplier evaluation system

• Implement automatic solder paste inspection (SPI)
• Develop soldering SOPs and training

5. Improve Phase
Objective:

To minimize soldering defects (cold joints, poor connections) by optimizing process

parameters using Taguchi’s Design of Experiments (DOE) approach.

We aim to find the optimal combination of soldering temperature, time, and solder
paste type that leads to maximum defect-free boards and minimum variation.

Step 1: Identify Factors and Levels

Factor Level 1 Level 2 Level 3
A: Solder Temp (°C) 250 260 270
B: Solder Time (sec) 2 3 4
C: Paste Type A B C

This is a 3-factor, 3-level experiment. A full factorial design would require 3^3 = 27runs.
Using Taguchi L9 (3³) orthogonal array, only 9 runs are needed.

Step 2: Taguchi L9 Orthogonal Array Design

Run A (Temp) B (Time) C (Paste)
1 250 2 A
2 250 3 B
3 250 4 C

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ENGR-5396EL-03: Quality Planning and Analysis

Run A (Temp) B (Time) C (Paste)

4 260 2 B
5 260 3 C
6 260 4 A
7 270 2 C
8 270 3 A
9 270 4 B

Step 3: Experimental Results

Each run is tested on 3 samples. Results are percentage of defect-free boards (the higher,
the better):

Run Results (%) per sample Mean (%) S/N Ratio (HB)
1 90, 88, 89 89.0 20log10(89) =38.98
2 87, 85, 86 86.0 20log10(86) =38.69
3 82, 84, 83 83.0 20log10(83) =38.38
4 92, 90, 91 91.0 20log10(91) =39.18
5 94, 93, 92 93.0 20log10(93) =39.38
6 95, 96, 94 95.0 20log10(95) =39.55
7 85, 83, 84 84.0 20log10(84) =38.48
8 87, 89, 88 88.0 20log10(88) =38.89
9 89, 91, 90 90.0 20log10(90) =39.08

Step 4: Main Effect Analysis

Let’s compute average S/N ratios for each factor level:

Factor A: Temperature
Level Runs Avg S/N
250°C 1, 2, 3 (38.98 + 38.69 + 38.38)/3 = 38.68
260°C 4, 5, 6 (39.18 + 39.38 + 39.55)/3 = 39.37
270°C 7, 8, 9 (38.48 + 38.89 + 39.08)/3 = 38.82

Best Level: 260°C (highest S/N)

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ENGR-5396EL-03: Quality Planning and Analysis

Factor B: Time
Level Runs Avg S/N
2 sec 1, 4, 7 (38.98 + 39.18 + 38.48)/3 = 38.88
3 sec 2, 5, 8 (38.69 + 39.38 + 38.89)/3 = 38.99
4 sec 3, 6, 9 (38.38 + 39.55 + 39.08)/3 = 38.99

Best Level: 3 or 4 seconds (equal S/N)

Factor C: Paste Type

Level Runs Avg S/N
A 1, 6, 8 (38.98 + 39.55 + 38.89)/3 = 39.14
B 2, 4, 9 (38.69 + 39.18 + 39.08)/3 = 38.98
C 3, 5, 7 (38.38 + 39.38 + 38.48)/3 = 38.75

Best Level: Paste A

Step 5: Optimal Settings

Based on highest S/N Ratios:

• Solder Temp: 260°C

• Time: 3 or 4 sec
• Paste Type: A

Let’s validate these values with Run 6, which is close to this setting:

• Temp = 260°C
• Time = 4 sec
• Paste = A
• Mean = 95% defect-free
• S/N = 39.55 dB (highest of all)

This confirms optimal condition.

Step 6: Conclusion from DOE

The DOE helped isolate the best combination of process settings that reduced soldering
defects. This led to:

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ENGR-5396EL-03: Quality Planning and Analysis

• Reduced rework (from 6% to ~2%)

• Increased yield (~95% first pass)
• Higher customer satisfaction (fewer returns)

This experiment demonstrates the power of Taguchi methods in quality improvement

with minimal experimentation.

6. Control Phase

Objective:
To sustain improvements, prevent recurrence of failures, and maintain low COPQ over
the long term.

Control Measures Implemented:

1. Standard Operating Procedures (SOPs):

o Documented optimal solder temp/time
o Incoming inspection checklists introduced
2. Supplier Audits:
o Quarterly evaluation based on defect rate, lead time, response time
o “Preferred supplier” status linked to consistent quality
3. Training Programs:
o Operator recertification every 6 months
o Visual guides and defect samples added to workstations
4. Statistical Process Control (SPC):
o X̄ and R charts to monitor solder quality and board defects
o Alerts set for upper/lower control limits
5. Feedback & Reporting:
o Weekly quality review meetings
o Internal “Quality Alert System” for frontline employees

KPI Improvements Tracked:

• Rework Rate: Reduced from 6% to 2%

• First Pass Yield: Improved from 88% to 96%
• Customer Returns: Cut by 40% in 3 months

7. Conclusion

This case study illustrates how structured application of the DMAIC methodology can
drive significant reductions in the Cost of Poor Quality (COPQ). Starting from
$79,000/month, COPQ was reduced by nearly 50% through:

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ENGR-5396EL-03: Quality Planning and Analysis

• Process optimization using DOE

• Supplier accountability and audit systems
• Training and SOP standardization
• Statistical control implementation

These improvements not only resulted in cost savings but also enhanced customer
satisfaction and production reliability. The approach taken here—rooted in data and
collaboration—can serve as a blueprint for similar initiatives in other manufacturing
sectors.

8. Acknowledgments

This report was completed as part of a graduate quality engineering project focused on
Lean Six Sigma application in gear manufacturing. The author wishes to acknowledge
the following:

• Class lectures and lab content, which served as the primary foundation for
applying tools such as FMEA, VSM, SPC, and SMED in this simulated factory
setting (Uslu, 2025).
• ChatGPT (OpenAI), for providing technical support in structuring academic
sections, verifying calculations, and polishing the document’s language and
formatting.
• All classmates who shared ideas, participated in simulated walkthroughs, and
provided feedback during mock reviews.

9. References

[1] R. Medina Serrano, M. R. González Ramírez, and J. L. Gascó Gascó, Applying Six
Sigma for Reduction Supplier Cost of Poor Quality: A Case Study from a German
Electronics Firm. Proceedings of the 5th International Conference on Opportunities and
Challenges in Management, Economics and Accounting, 2019.

[2] D. C. Montgomery, Design and Analysis of Experiments, 9th ed. Hoboken, NJ, USA:
Wiley, 2017.

[3] D. H. Stamatis, Failure Mode and Effect Analysis: FMEA from Theory to Execution,
2nd ed. Milwaukee, WI, USA: ASQ Quality Press, 2003.