DIGITAL IC DESIGN - Ph.

D ECE (Course Code: 24CECE0DT)

UNIT I: MOS DESIGN PSEUDO NMOS LOGIC

This unit introduces the foundational principles of MOS logic, particularly focusing on pseudo NMOS logic

design.

- Inverter: A basic logic gate that outputs the opposite logic level to its input. Analysis includes threshold

voltage (Vth), which determines switching point.

- Inverter Threshold Voltage: Voltage at which the inverter output switches; influenced by transistor sizes and

supply voltage.

- Output High/Low Voltage: Determined by transistor characteristics; defines logical '1' and '0' levels.

- Gain at Gate Threshold Voltage: Defined by the slope of VTC curve at Vth; indicates noise immunity.

- Transient Response: Describes how quickly a gate responds to input changes. Rise time (0 -> 1 transition)

and fall time (1 -> 0 transition) are crucial for speed.

- Pseudo NMOS Logic: A logic family using a single pull-up transistor (always ON PMOS) with NMOS

pull-down network. Offers area and speed benefits at cost of static power.

- Transistor Equivalency: Concept of replacing complex gates with equivalent simpler transistor models for

analysis.

- CMOS Inverter Logic: Combines PMOS and NMOS in complementary fashion for full voltage swing, low

static power, and high noise margins.

UNIT II: COMBINATIONAL MOS LOGIC CIRCUITS

This unit deals with designing logic circuits using MOS technology.
 DIGITAL IC DESIGN - Ph.D ECE (Course Code: 24CECE0DT)

- NMOS Load Circuits: Use of depletion/enhancement-mode NMOS for implementing logic gates with

resistive or active loads.

- CMOS NOR and NAND Gates: Constructed using pull-up and pull-down networks; preferred for their speed,

noise immunity, and full logic swing.

- Complex Logic Gates: Boolean logic implemented with fewer transistors using combination of NAND/NOR

and inverters.

- AOI & OAI Gates: Optimized designs combining AND, OR, and Inversion in one gate for speed and area

efficiency.

- CMOS Full Adder: A fundamental arithmetic unit built using logic gates; designed using minimum transistor

count for power efficiency.

- Transmission Gates: CMOS switches using parallel NMOS and PMOS controlled by complementary

signals; useful for multiplexers and latches.

UNIT III: SEQUENTIAL MOS LOGIC CIRCUITS

Sequential circuits store state information and respond to clock signals.

- Bi-stable Elements: Circuits with two stable states, forming the basis of memory and storage elements.

- SR Latch: Basic storage element with Set and Reset inputs; implemented using cross-coupled NOR or

NAND gates.

- Clocked Latch: Enabled storage element that stores data when clock is high or low depending on design.

- Flip-Flops: Edge-triggered devices (like D flip-flop) that store data on rising/falling edge of clock.

- CMOS D Latch and Flip-Flop: Built using transmission gates and inverters; optimize power and area while

ensuring robust data storage.

UNIT IV: DYNAMIC LOGIC CIRCUITS

Dynamic logic enhances speed and area but is more sensitive to noise and charge sharing.

- Basic Principle: Uses clocked precharge and evaluation phases to reduce transistor count and increase

speed.

- Voltage Bootstrapping: Technique to boost gate voltages for faster switching and reduced delay.

- Synchronous Pass Transistor Logic: Controlled switching using pass transistors synchronized with clock;

improves performance.

- Dynamic CMOS Transmission Gate Logic: Combines benefits of dynamic logic and transmission gates.

- High Performance Dynamic Logic: Techniques like Domino logic and np-CMOS enable fast pipelined

operation in processors.

UNIT V: SEMICONDUCTOR MEMORIES

Memory systems form the backbone of digital computing.

- Memory Types: ROM, RAM (volatile), DRAM (high density), SRAM (high speed), and Flash (non-volatile).

- RAM Array Architecture: Includes row/column decoding, sense amplifiers, and write circuitry.

- DRAM: Uses capacitors to store charge; refresh needed due to leakage. Types include

asynchronous/synchronous DRAM.

- SRAM: Uses bistable latch for storage; faster and less dense than DRAM.

- Flash Memory: Non-volatile memory with NOR (faster read) and NAND (higher density, cheaper) flash

types.
 DIGITAL IC DESIGN - Ph.D ECE (Course Code: 24CECE0DT)

- Leakage Current: Affects both DRAM and SRAM; impacts retention and power efficiency.

PRESCRIBED TEXT BOOKS

1. John P. Uyemura, Introduction to VLSI Circuits and Systems, Wiley, 2002.

2. Kamran Eshraghian, David A. Pucknell, Essentials of VLSI Circuits and Systems, Prentice-Hall, 2005.

3. R. Jacob Baker, CMOS Circuit Design, Layout, and Simulation, 3rd Edition, Wiley, 2010.

REFERENCE BOOKS

1. Morris Mano, Digital Design, 5th Edition, Pearson, 2013.

2. Weste, Neil H.E., and David Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 4th Edition,

Pearson Education, 2011.

3. Douglas A. Pucknell, Kamran Eshraghian, Basic VLSI Design: Systems and Circuits, 3rd Edition,

Prentice-Hall, 2022.