Specification Document for Packet Decoder
RTL Design
1. Overview
The purpose of this document is to outline the specifications for an RTL (Register Transfer
Level) design of a packet decoder. The decoder will extract and process packets generated by
the encoder, splitting them into their original components:
1. Header: Contains metadata about the packet.
2. Payload: Contains the actual data transmitted.
3. CRC/Parity: Ensures data integrity.
The decoder will validate the packet, route the payload to the appropriate destination, and
signal the validity of the output.
2. Packet Structure
Each packet processed by the decoder will follow the structure defined by the encoder:
Field Size Description
Header 2 Bytes Contains the destination address and payload size.
Payload Variable Contains the transmitted data.
CRC/Parity 1 Byte Error-checking information for data integrity.
2.1 Header Structure
Sub-field Size Description
Destination Address 1 Byte Identifies the target recipient (AA, BB, CC, DD).
Payload Byte Count 1 Byte Specifies the number of bytes in the payload.
2.2 Payload
The payload carries the actual transmitted data.
Its size is variable and specified in the header.
2.3 CRC/Parity
An 8-bit CRC or parity field is appended to the packet for error detection.
3. Functional Requirements
3.1 Input Ports
Signal Name Width Description
clk 1 Clock signal for synchronous operation.
reset 1 Active-high reset signal. Clears all states.
data_in 8 Packet input data stream.
valid_in 1 Indicates when the input data is valid.
3.2 Output Ports
Signal Name Width Description
aa 8 Output data for destination address aa.
bb 8 Output data for destination address bb.
cc 8 Output data for destination address cc.
dd 8 Output data for destination address dd.
valid_port Indicates the validity of the data routed to a port. 00
2
is for aa, 01 is for bb, 10 is for cc and 11 for dd.
valid_out 1 Indicates when the output data is valid.
4. Block Diagram
5. Functional Description
1. Packet Parsing:
o The decoder reads the incoming packet from data_in.
o The first 2 bytes are parsed as the header to extract the destination address and
payload size respectively.
2. Payload Routing:
o The payload is routed to one of the four output ports (aa, bb, cc, dd)
based on the destination address.
3. CRC/Parity Validation:
o The decoder calculates a CRC/Parity for the received data and compares it
with the transmitted CRC/Parity.
o If the CRC/Parity matches, the data will be sent by asserting
valid_out and it’s respective valid_port value is set.
4. Error Handling:
o If the CRC does not match, no output is asserted, and the decoder waits for the
next valid packet.
6. Timing Requirements
The decoder operates on the rising edge of clk.
The valid_out and valid_port signals will remain asserted until a valid packet
is processed.
7. Reset Behavior
When reset is asserted, all internal states and outputs are cleared.
The decoder will not process any data until the reset signal is deasserted and valid
data is received on data_in.
8. Error Scenarios
CRC/Parity Failure: If the CRC/Parity does not match, the packet is discarded, and no
output is asserted.
Incomplete Packet: If the packet is incomplete or corrupted, the decoder waits for the
next valid input.
