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Verilog

The document describes various digital circuit modules implemented in Verilog, including a 4-bit binary adder/subtractor, a 4-bit up counter, a 2:1 multiplexer, and different types of shift registers (SISO, SIPO, PISO, PIPO). Each module is defined with input and output specifications, along with the logic for their operations. The code snippets illustrate how these components function in a hardware description language.

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32 views7 pages

Verilog

The document describes various digital circuit modules implemented in Verilog, including a 4-bit binary adder/subtractor, a 4-bit up counter, a 2:1 multiplexer, and different types of shift registers (SISO, SIPO, PISO, PIPO). Each module is defined with input and output specifications, along with the logic for their operations. The code snippets illustrate how these components function in a hardware description language.

Uploaded by

sit21cs042
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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4 BIT BINARY ADDER AND SUBTRACTOR

module addsub( y, a, b, addnsub);

output [4:0] y;
input addnsub;
input [3:0] a;
input [3:0] b;

reg [4:0] y;

always@ (a or b or addnsub)
begin
if(addnsub)
y = a + b;
else
y = a - b;
end

endmodule
4 BIT UP COUNTER

module counter(clk, reset, ena, q);


input clk;
input reset;
input ena;
output [3:0] q;

reg [3:0] q;

always@(posedge clk or posedge ena)


begin
if(ena)
q = q+1;
else if(reset)
q = 0;
end

endmodule
2:1 MULTIPLEXER

module mux21(y, sel, a, b);


output y;
input sel;
input a;
input b;

wire a1, a2, selbar;

not (selbar, sel);


and (a1, a, selbar);
and (a2, b, sel);
or(y, a1, a2);
endmodule
SHIFT REGISTER

SERIAL IN SERIAL OUT

module siso(so, si, clk);


output so;
input si;
input clk;

reg [3:0] tmp;

always@(posedge clk)
begin
tmp = tmp >> 1;
tmp[3] = si;
end
assign so = tmp[0];
endmodule
SERIAL IN PARALLEL OUT

module sipo(po, si, clk);


output [3:0] po;
input si;
input clk;

reg [3:0] tmp;

always@(posedge clk)
begin
tmp = tmp >> 1;
tmp[3] = si;
end
assign po = tmp;
endmodule
PARALLEL IN SERIAL OUT

module piso(so, pi, clk);


output so;
input [3:0] pi;
input clk;

reg [3:0] tmp;

always@(posedge clk)
begin
tmp = tmp >> 1;
tmp = pi;
end
assign so = tmp[0];
endmodule
PARALLEL IN PARALLEL OUT

module pipo(po, pi, clk);


output [3:0] po;
input [3:0] pi;
input clk;

reg [3:0] tmp;

always@(posedge clk)
begin
tmp = pi;
end
assign po = tmp;
endmodule

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