System verilog
In SystemVerilog,
module.sv typically refers to a file containing a module definition — which is the
basic building block of hardware design (as opposed to classes used in test
benches).
A module describes hardware logic. It contains:
Ports (input/output/inout)
Internal logic (wires, regs, logic, always blocks, assign, etc.)
Instances of other modules
Optionally, interfaces, parameters, and generics
The module.sv file typically contains the DUT (Design Under Test), which is
instantiated and tested in the test-bench. The test-bench interacts with the
module using:
Interfaces
Driver/monitor classes
Clock/reset generation
Example: module.sv
module <module_name> #(parameter ...) (
input logic ...,
output logic ...
);
// Internal declarations
// Behavioral or structural code
Endmodule
· module.sv is just a filename convention — it usually holds one or more module
definitions.
· Modules are synthesizable and used to describe RTL logic.
· Modules are instantiated in testbenches or other modules.
System verilog
A program block is like a module, but:
It executes in a reactive way (always after the DUT).
The code responds to the outputs or behavior of the
DUT, rather than running independently or concurrently.
It ensures race-free synchronization between test-bench and DUT.
Race-free synchronization means avoiding situations where multiple parts of
the test-bench and DUT try to read or write the same signals at the same time,
leading to unpredictable or incorrect simulation results.
It is non-synthesize — used only in simulation.
What is a Race Condition?
A race condition happens when:
Two or more processes compete to access or change the same
data,
And the result depends on the order of execution — which is not
guaranteed.
In testbenches, race conditions often occur between:
The DUT (module) and
The test logic (initial, always, or program block)
System verilog
What is a test class?
In System Verilog, particularly in UVM, the test class is the top-level control class
that:
Creates the test environment
Starts stimulus sequences
Controls simulation phases
Optionally configures components via a factory or configuration database
Basic Structure of a test Class
class my_test extends uvm_test;
`uvm_component_utils(my_test)
// Constructor
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
// Build phase: create environment
function void build_phase(uvm_phase phase);
super.build_phase(phase);
// Create env, set configs
endfunction
// Run phase: run main test logic
task run_phase(uvm_phase phase);
super.run_phase(phase);
phase.raise_objection(this);
// Start sequences, wait, etc.
System verilog
#100ns;
phase.drop_objection(this);
endtask
endclass
What is an Environment Class in System Verilog
the environment class, usually called env, is a container for all major verification
components such as:
Agents (which include driver, monitor, sequencer)
Scoreboards
Coverage collectors
Possibly virtual sequencers
It acts as the glue between your test and the rest of your test-bench components.
Basic Structure of an env Class
class my_env extends uvm_env;
`uvm_component_utils(my_env)
// Component handles
my_agent agent_h;
my_scoreboard sb_h;
// Constructor
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
// Build phase: create components
function void build_phase(uvm_phase phase);
System verilog
super.build_phase(phase);
agent_h = my_agent::type_id::create("agent_h", this);
sb_h = my_scoreboard::type_id::create("sb_h", this);
endfunction
// Connect phase: connect TLM ports
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
// Example: connect monitor to scoreboard
agent_h.monitor.analysis_port.connect(sb_h.analysis_export);
endfunction
Endclass
What is an Agent in SystemVerilog
An Agent in SystemVerilog UVM is a reusable, encapsulated verification
component that groups together:
A driver (sends transactions to DUT)
A monitor (observes DUT activity)
A sequencer (provides transaction sequences to the driver)
It represents one interface or protocol — like AXI, UART, SPI, etc.
System verilog
Agent Class Structure
class my_agent extends uvm_agent;
`uvm_component_utils(my_agent)
my_driver driver_h;
my_sequencer sequencer_h;
my_monitor monitor_h;
function new(string name, uvm_component parent);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
monitor_h = my_monitor::type_id::create("monitor_h", this);
if (get_is_active() == UVM_ACTIVE) begin
driver_h = my_driver::type_id::create("driver_h", this);
sequencer_h = my_sequencer::type_id::create("sequencer_h", this);
end
endfunction
function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
System verilog
if (get_is_active() == UVM_ACTIVE)
driver_h.seq_item_port.connect(sequencer_h.seq_item_export);
endfunction
endclass
