1. How many states a 6-bit ripple counter can have?
(a) 6
(b) 12
(c) 32
(d) 64
2. How many flip-flops are needed to divide the input frequency by 40? (a) 4
(a)4
(b) 5
(c) 6
(d) 40
3. The number of flip-flops required for decade counter is
(a) 3
(b) 4
(c)5
(d) 10
4. In sequential circuits the present input depends on
(a) past inputs only
(b) present inputs only
(c) present as well as past inputs
(d) past outputs
5. The minimum number of flip-flops required for a mod-12 ripple counter is
(a)3
(b) 4
(c) 6
(d) 12
6. The maximum number that can be obtained by a ripple counter using five flip-flops is
(a) 32
(b) 5
(c) 16
(d) 31
7. A mod-5 synchronous counter is designed using J-K flip-flops. The number of counts it will skip is
(a) 2
(b) 3
(c) 5
(d) 10
8. The number of flip-flops required for a mod-16 ring counter is
(a) 4
(b) 8
(c) 15
(d) 16
9. The number of flip-flops required for a mod-12 Johnson counter is
(a) 4
(b) 6
(c) 12
(d) 24
10. In a counter circuit consisting of four J-K flip-flops, all the flip-flops get triggered simultaneously.
This counter circuit
(a) is a combinational circuit
(b) is an asynchronous circuit
(c) is a synchronous circuit
(d) may be a combinational or a sequential circuit
11. In a 4-bit binary ripple counter, for every input clock pulse
(a) all the flip-flops get clocked simultaneously
(b) only one flip-flop gets clocked at a time
(c) two of the flip-flops get clocked at a time
(d) all the above statements are false
12. A 4-bit binary ripple counter uses flip-flops with propagation delay time of 25 ns each. The
maximum possible time required for change of state will be
(a) 25 ns
(b) 50 ns
(c) 75 ns
(d) 100 ns
13. A 4-bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The
maximum possible time required for change of state will be
(a) 25 ns
(b) 50 ns
(c) 75 ns
(d) 100 ns
14. A mod-2 counter followed by a mod-5 counter is
(a) the same as a mod-5 counter followed by a mod-2 counter
(b) a decade counter
(c) a mod-7 counter
(d) none of the above
15. A symmetrical squarewave of time period 100 µs can be obtained from a squarewave of time
period 10 us by using a
(a) divide-by-5 circuit
(b) BCD counter
(c) divide-by-5 circuit followed by a divide-by-2 circuit
(d) 4-bit binary counter
16. A 4-bit presettable up-counter has present input 0101. The presetting operation takes place as
soon as the counter becomes maximum, i.e. 1111. The modulus of this counter is
(a) 5
(b) 10
(c) 11
(d) 15
17. In general, a sequential logic circuit consists of
(a) only flip-flops
(b) only gates
(c) flip-flops and combinational logic circuits
(d) only combinational logic circuits
18. The output frequency of a mod-16 counter, clocked from a 20-kHz clock input signal is
(a) 20 kHz
(b) 52 kHz
(c) 625 Hz
(d) 1250 Hz
19. The output frequency of a mod-12 counter is 6 kHz. Its input frequency is
(a) 6 kHz
(b) 500 Hz
(c) 24 kHz
(d)72kHz
20. A 3-bit Johnson counter has how many unique states?
(a) 3
(b) 6
(c) 8
(d) 16
21. A mod-24 counter requires a minimum of how many flip-flops?
(a) 4
(b) 5
(c) 6
(d) 24
22. In a 4-bit ring counter, the initial state is 1000. After 4 clock pulses, the state will be:
(a) 0001
(b) 1000
(c) 0100
(d) 1111
23. The minimum number of flip-flops needed for a mod-10 asynchronous counter is:
(a) 2
(b) 3
(c) 4
(d) 10
24. A synchronous counter is preferred over an asynchronous counter because it:
(a) Uses fewer flip-flops
(b) Has no propagation delay issues
(c) Operates at higher clock frequencies
(d) All of the above
25. A BCD counter resets when it reaches:
(a) 1010 (10 in decimal)
(b) 1001 (9 in decimal)
(c) 1111 (15 in decimal)
(d) 1100 (12 in decimal)
26. The output of a 4-bit binary counter after 15 pulses is 1111. What is the output after 16 pulses?
(a) 0000
(b) 1111
(c) 1000
(d) 0111
27. A 3-bit up/down counter in "down" mode starts at 111 (7). After 3 pulses, the output is:
(a) 100 (4)
(b) 000 (0)
(c) 110 (6)
(d) 111 (7)
28. A mod-7 counter skips how many states in a 3-bit configuration?
(a) 1
(b) 2
(c) 3
(d) 7
29. The resolution of an 8-bit counter is:
(a) 1/8
(b) 1/64
(c) 1/256
(d) 1/512
30. To design a mod-60 counter, the minimum number of flip-flops required is:
(a) 5
(b) 6
(c) 8
(d) 60
31. In a 4-bit synchronous up-counter, the flip-flops are clocked:
(a) One after another in sequence
(b) Simultaneously by a common clock
(c) Only when the output is 1111
(d) By an external pulse generator
32. A mod-10 counter is also known as a:
(a) Decade counter
(b) BCD counter
(c) Both (a) and (b)
(d) Ripple counter
33. The primary disadvantage of a ripple counter compared to a synchronous counter is:
(a) Higher power consumption
(b) Cumulative propagation delay
(c) Limited to mod-16 operation
(d) Requires more flip-flops
34. A 3-bit binary up-counter is currently at state 101 (5). After 3 clock pulses, its state will be:
(a) 000 (0)
(b) 111 (7)
(c) 010 (2)
(d) 100 (4)
35. To design a mod-20 counter, the minimum number of flip-flops required is:
(a) 4
(b) 5
(c) 6
(d) 20
36. In a ring counter with 6 flip-flops, how many states are valid in one complete cycle?
(a) 6
(b) 12
(c) 32
(d) 64
37. A down-counter counts from 111 (7) to 000 (0). What is its state after 9 clock pulses?
(a) 000 (0)
(b) 001 (1)
(c) 110 (6)
(d) 111 (7)
38. The maximum frequency of operation for a counter is determined by:
(a) The number of flip-flops
(b) The propagation delay of each flip-flop
(c) The clock pulse width
(d) The power supply voltage
39. A mod-8 counter is cascaded with a mod-4 counter. The overall modulus is:
(a) 12
(b) 32
(c) 8
(d) 4
40. A 4-bit Johnson counter is initialized to 0000. After 6 clock pulses, its state is:
(a) 0000
(b) 1111
(c) 0110
(d) 1001
