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Plate 7

The document outlines a project for a combination circuit design with three inputs and six outputs, where the output is the square of the input binary number. It includes a truth table, Boolean functions for each output, and specifies the use of multilevel NAND and NOR gates with specific ICs. The project is submitted by a student to their instructor at the University of Southern Mindanao.

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Rejean Faith Mallari
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10 views4 pages

Plate 7

The document outlines a project for a combination circuit design with three inputs and six outputs, where the output is the square of the input binary number. It includes a truth table, Boolean functions for each output, and specifies the use of multilevel NAND and NOR gates with specific ICs. The project is submitted by a student to their instructor at the University of Southern Mindanao.

Uploaded by

Rejean Faith Mallari
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

University of Southern Mindanao

Kabacan, Cotabato
College of Engineering and Information Technology

PLATE NO. 7
Square of Input
CpE 311 – Logic Circuits and Design

Submitted by:

Alexis B. Banicio
3-BSCpE-A

Submitted to:

Jeannalen P. Lunod, ME-CpE


Instructor

November 22, 2023


A. Problem:

Design a combination circuit with three inputs and six outputs. The output binary
number should be the square of the input binary number.

Implement the circuit using:

a. multilevel NAND gates (use only 74LS00 IC)


b. multilevel NOR gates (use only 74LS02 IC)

B. Truth Table

# X Y Z F1 F2 F3 F4 F5 F6
0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 0 0 1
2 0 1 0 0 0 0 1 0 0
3 0 1 1 0 0 1 0 0 1
4 1 0 0 0 1 0 0 0 0
5 1 0 1 0 1 1 0 0 1
6 1 1 0 1 0 0 1 0 0
7 1 1 1 1 1 0 0 0 1
C. Boolean Functions

XY XY
Z Z 00 01 11 10
00 01 11 10

1 0
1
0

1 1 1 1 1

F1 : xy F2 : xy’ + xz
x (y’ + z)

XY XY

Z Z 00 01 11 10
00 01 11 10
1 1
0
0

1
1 1 1

F3 : x’yz + xy’z F4 : yz’


z (x’y + xy’)

XY XY
Z 00 01 11 10 Z 00 01 11 10

0 0

1 1 1 1 1 1

F5 : 0 F6 : z
D. Logic Diagram

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