Department of Electronics and Communication Engineering
Regulation 2021
II Year – IV Semester
EC3492- DIGITAL SIGNAL PROCESSING
Unit – V: Dsp Applications
Multirate signal processing: Decimation, Interpolation, Sampling rate conversion by a rational
factor – Adaptive Filters: Introduction, Applications of adaptive filtering to equalization-DSP
Architecture Fixed and Floating point architecture principles.
Multi-rate signal processing:
The process of converting a signal from a given rate to a different rate is called
sampling rate conversion. Systems that employ multiple sampling rates in the
processing of digital signals are called multi rate digital signal processing.
Down-sampling:
The process of reducing the sampling rate by an integer factor(D) is called decimation
of the sampling rate. It is also called down sampling by factor(D).Decimator consists of
decimation filter to band limit the signal and down sampler to decrease the sampling
rate by an integer factor (D).
Decimation
– Reduce the sampling rate of a discrete-time signal.
– Low sampling rate reduces storage and computation requirements.
up-sampling:
Increasing sampling rate of a signal by an integer factor I is known as Interpolation or
up-sampling. An increase in the sampling rate by an integer factor I may be done by
interpolating (I-1) new samples between successive values of the signals.
• Interpolation
– Increase the sampling rate of a discrete-time signal.
– Higher sampling rate preserves fidelity
Sampling Rate Conversion
Having discussed the special cases of decimation (down sampling by a factor D) and
interpolation (upsampling by a factor I), we now consider the general case of sampling
rate conversion by a rational factor I/D. Basically, we can achieve this sampling rate
conversion by first performing interpolation by the factor I and then decimating the
output of the interpolator by the factor D. In other words, a sampling rate conversion by
the rational factor I/D is accomplished by cascading an interpolator with a decimator.
We emphasize that the importance of performing the interpolation first and the
decimation second is to preserve the desired spectral characteristics of x(n).
Sample-rate conversion is the process of changing the sampling rate of a discrete signal
to obtain a new discrete representation of the underlying continuous signal. Application
areas include image scaling and audio/visual systems, where different sampling rates
may be used for engineering, economic, or historical reasons.
Fig: Sampling-rate conversion by expansion, filtering, and decimation
An example of sampling-rate conversion would take place when data from a CD is
transferred onto a DAT. Here the sampling-rate is increased from 44.1 kHz to 48 kHz.
To enable this process the non-integer factor has to be approximated by a rational
number:
Hence, the sampling-rate conversion is achieved by interpolating by L i.e. from 44.1
kHz to [44.1x160] = 7056 kHz.
Then decimating by M i.e. from 7056 kHz to [7056/147] = 48 kHz.
Multistage Approach
When the sampling-rate changes are large, it is often better to perform the operation in
multiple stages, where Mi(Li), an integer, is the factor for the stage i.
An example of the multistage approach for decimation is shown in Figure 9.8. The multistage
approach allows a significant relaxation of the anti-alias and anti-imaging filters, with a
consequent reduction in the filter complexity. The optimum number of stages is one that
leads to the least computational effort in terms of either the multiplications per second
(MPS), or the total storage requirement (TSR).
Fig: Multistage approach for the decimation process.
The meth to avoid aliasing:
(i) Pre alias filter must be used to limit band of frequencies of the signal to
fmHz.
(ii) Sampling frequency ‘fs’ must be selected such that fs> 2 fm
The need for anti aliasing filter prior to down sampling:
Anti aliasing filter is used to avoid aliasing caused by down sampling the signal x(n).
The need for anti imaging filter after up sampling a signal?
Anti imaging filter removes the unwanted images that are that are yielded by up
sampling.
Applications of multi rate signal processing.
Multirate systems are used in a CD player when the music signal is converted from digital
into analogue (DAC). Digital data (16-bit words) are read from the disk at a sampling rate of
44.1 kHz. If this data were converted directly into an analogue signal, image frequency bands
centred on multiples of the sampling-rate would occur, causing amplifier overload, and
distortion in the music signal. To protect against this, a common technique called
oversampling is often implemented nowadays in all CD players and in most digital
processing systems of music signals. Fig.3 below illustrates a basic block diagram of a CD
player and how oversampling is utilised. It is customary to oversample (or expand) the digital
signal by a factor of x8, followed by an interpolation filter to remove the image frequencies.
The sampling rate of the resulting signal is now increased up to 352.8 kHz. The digital signal
is then converted into an analogue waveform by passing it through a 14-bit DAC. Then the
output from this device is passed through an analogue low-pass filter before it is sent to the
speakers.
Fig. 3: Digital to analogue conversion for a CD player using x8 oversampling.
Fig. 4 illustrates the procedure of converting a digital waveform into an analogue signal in a
CD player using x8 oversampling. As an example, Figure (a) illustrates a 20 kHz sinusoidal
signal sampled at 44.1 kHz, denoted by x[n]. The six samples of the signal represent the
waveform over two periods. If the signal x[n] was converted directly into an analogue
waveform, it would be very hard to exactly reconstruct the 20 kHz signal from this diagram.
Now, Figure (b) shows x[n] with an x8 interpolation, denoted by y[n]. Figure (c) shows the
analogue signal y(t), reconstructed from the digital signal y[n] by passing it through a DAC.
Finally, Figure (d) shows the waveform of z(t), which is obtained by passing the signal y(t)
through an analogue low-pass filter.
Fig 4: Illustration of oversampling in CD music signal reconstruction.
The effect of oversampling also has some other desirable features. Firstly, it causes the image
frequencies to be much higher and therefore easier to filter out. The anti-alias filter
specification can therefore be very much relaxed i.e. the cutoff frequency of the filter for the
previous example increases from [44.1 / 2] = 22.05 kHz to [44.1x8 / 2] = 176.4 kHz after the
interpolation.
1. Design of phase shifters
2. Interfacing of digital systems with different sampling rates
3. Implementation of narrow band LPF & implementation of Digital Filter Bank
4. Sub band coding of speech signals & Quadrature mirror filter
5. Trans multiplexers & Over sampling of A/D and D/A conversion
Mention the applications of speech coding.
Digital transmission like telephony, narrow band cellular radio, military
communications and secrecy missions, voice mail sent on telephone networks, voice
encryption, integrated voice and data transmission over packet networks.
Sub-band coding:
The speech signal is applied to an analysis filter bank consisting of a set of Q band pass
filters. This digital filtration divides the speech signal into a non overlapping frequency
bands. These filter banks are contiguous in frequency. Hence, by additive
recombination of the set of sub band signals, one can approximately generate the
original speech signal.
Decimation By A Factor D:
Interpolation By A Factor I:
Sampling Rate Conversion By A Rational Factor I/D:
Sampling rate conversion of band pass signals:
Advantages of BP Sampling:
Unit – V: Dsp Applications
Multirate signal processing: Decimation, Interpolation, Sampling rate conversion by a rational factor –
Adaptive Filters: Introduction, Applications of adaptive filtering to equalization-DSP Architecture
Fixed and Floating point architecture principles.
Introduction
In general, DSP processors can be classified into two broad categories as general purpose and special
purpose. Fixed-point devices such as Texas Instruments TMS320C54x, and Motorola DSP563x
processors, and floating- point processors such as Texas Instruments TMS320C4x and Analog Devices
ADSP21xxx SHARC processors are included in DSP Processors.
Special purpose hardware are divided into two categories,
1. One type of special- purpose hardware is sometimes called an algorithm-specific digital signal
processor. Hardware designed for efficient execution of specific DSP algorithms such as digital filters,
Fast Fourier Transform comes under this category.
2. Another type of hardware is sometimes called an application-specific digital signal processor.
Hardware designed for specific applications: for example telecommunications, digital audio, or control
applications comes under this category.
In most cases application-specific digital signal processors execute specific algorithms, such as PCM
encoding/decoding, but they are also required to perform other application-specific operations.
Examples of special-purpose DSP processors are Cirrus’s processor for digital audio sampling rate
converters (CS8420), Intel’s multi- channel telephony voice echo canceller (MT9300), FFT processor
(PDSPI65I5A) and programmable FIR filter (VPDSP 16256).
Both general-purpose and special-purpose processors can be designed with single chips or with
individual blocks of multipliers, ALUs, memories, and so on. First, let us discuss the architectural
features of digital signal processors that have made real-time DSP in many possible areas.
Figure 1. A simplified architecture for standard microprocessor
Figure 2. Basic generic hardware architecture for signal processing
Figure 2 shows generic hardware architecture suitable for real time DSP It is characterized by the
multiple bus structure with separate memory space for data and program instructions. The data
memories hold input data, intermediate data values and output samples, as well as fixed coefficients for
example, digital filters or FFTs. The program instructions are stored in the program memory.
The I/O port provides a means of passing data to and from external devices such as the ADC and DAC
or for passing digital data to other processors. Direct memory access (DMA), if available,
allows for rapid transfer of blocks of data directly to or from data RAM, typically under external control.
Arithmetic units for logical and arithmetic operations include an ALU, a hardware multiplier and shifters
(or multiplier--accumulator)
The main necessary of this architecture is that most DSP algorithms (such as filtering correlation and
fast Fourier transform) involve repetitive arithmetic operations such as multiply, add, memory accesses,
and heavy data flow through the CPU. The architecture of standard microprocessors is not suited for
this type of activities. So an important goal in DSP hardware design is to optimize both the hardware
architecture and the instruction set for DSP operations. In digital signal processors, this is achieved by
making use of the concepts of parallelism. In particular, the following techniques are used:
1. Harvard architecture;
2. pipe-lining;
3. fast, dedicated hardware multiplier/accumulator;
4. special instructions dedicated to DSP;
5. replication;
6. on-chip memory/cache;
7. Extended parallelism — SIMD, VLIW and static superscalar processing.
For successful DSP design, it is important to understand these key architectural features.
Harvard architecture:
The principal feature of the Harvard architecture is that the program and data memories lie in two
separate spaces, permitting a full overlap of instruction fetch and execution. Standard microprocessors,
such as the Intel 6502, are characterized by a single bus structure for both data and instructions, as
shown in Figure 1.
Suppose that in a standard microprocessor if a value op I at address ADR 1 in memory into the
accumulator is to be read and then to be stored at two other addresses, ADR2 and ADR3. The instructions
could be
LDA ADRI load the operand op1 into the accumulator from ADRI STA
ADR2 store op1 in address ADR2
STA ADR3 store op1 in address ADR3
Typically, each of these instructions would involve three distinct steps:
• instruction fetch;
• instruction decode;
• instruction execute.
In our case, the instruction fetch involves fetching the next instruction from memory, and instruction
execute involves either reading or writing data into memory. In a standard processor, without Harvard
architecture, the program instructions (that is, the program code) and the data (operands) are held in one
memory space; see Figure 3. Thus the fetching of the next instruction while the current one is executing
is not allowed, because the fetch and execution phases each require memory access.
Figure 3. An illustration of instructions fetch, decode, and execute in a Non-Harward architecture with
single memory space. (a) instruction fetch from memory (b) timing diagram
In a Harvard architecture (Figure 4), since the program instructions and data lie in separate memory
spaces, the fetching of the next instruction can overlap the execution of the current instruction as shown
in Figure 5. Normally, the program memory holds the program code, while the data memory stores
variables such as the input data samples.
Figure 4. Basic Harvard architecture with separate data and program memory spaces
It may be seen from Figure 4 that data and program instruction fetches can be overlapped as two
independent memories are used in the architecture. This is explained with the help of the timing diagram
as shown in Figure 5 below.
Figure 5. An illustration of instruction overlap made possible by the Harvard architecture
Strict Harvard architecture is used by some digital signal processors (for example Motorola D5P56000),
but most use a modified Harvard architecture (for example, the TMS32O family of processors). For
example in the modified architecture used by the TMS32O, separate program and data memory spaces
are still maintained. But unlike the strict Harvard architecture, communication between the two memory
spaces is permitted here.
