CE 2704 - Digital Logic Design

Dr. Ehsan Ali

Assumption University of Thailand
[email protected]

Semester 2/2024
Contents

1 Module 9 - Memory 2
1.0.1 Learning Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Memory Architecture and Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Memory Map Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.2 Volatile Versus Non-volatile Memory . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.3 Read-Only Versus Read/Write Memory . . . . . . . . . . . . . . . . . . . . . . 3
1.1.4 Random Access Versus Sequential Access . . . . . . . . . . . . . . . . . . . . . 3
1.2 Non-volatile Memory Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1 ROM Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.2 Mask Read-Only Memory (MROM) . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.3 Programmable Read-Only Memory (PROM) . . . . . . . . . . . . . . . . . . . 8
1.2.4 Erasable Programmable Read-Only Memory (EPROM) . . . . . . . . . . . . . . 10
1.2.5 Electrically Erasable Programmable Read-Only Memory (EEPROM) . . . . . . 12
1.2.6 FLASH Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.2.6.1 Flash Memory Cell: Floating-Gate MOSFET Transistor . . . . . . . . 14
1.2.6.2 NOR Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
1.2.6.3 NAND Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.2.6.4 NOR vs NAND Flash Memory . . . . . . . . . . . . . . . . . . . . . 20
1.3 Volatile Memory Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.3.1 Static Random-Access Memory (SRAM) . . . . . . . . . . . . . . . . . . . . . 21
1.3.1.1 Differential amplifier [Will not be included in final exam] . . . . . . . 23
1.3.2 Dynamic Random-Access Memory (DRAM) . . . . . . . . . . . . . . . . . . . 27
1.3.2.1 Charge Pump [Will not be included in final exam] . . . . . . . . . . . 29
1.4 Modeling Memory with Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.4.1 Read-Only Memory in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.4.2 Read/Write Memory in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.5 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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Chapter 1

Module 9 - Memory

This week introduces the basic concepts, terminology, and roles of memory in digital systems. The ma-
terial presented here will not delve into the details of the device physics or low-level theory of operation.
Instead, the intent of this week lecture notes is to give a general overview of memory technology and
its use in computer systems in addition to how to model memory in Verilog. The goal is to give an
understanding of the basic principles of semiconductor-based memory systems.

1.0.1 Learning Outcomes

• Describe the basic architecture and terminology for semiconductor-based memory systems.

• Describe the basic architecture of non-volatile memory systems.

• Describe the basic architecture of volatile memory systems.

• Design a Verilog behavioral model of a memory system.

1.1 Memory Architecture and Terminology

The term memory is used to describe a system with the ability to store digital information. The term
semiconductor memory refers to systems that are implemented using integrated circuit technology.
These types of systems store the digital information using transistors, fuses, and/or capacitors on a single
semiconductor substrate. Memory can also be implemented using technology other than semiconduc-
tors. Disk drives store information by altering the polarity of magnetic fields on a circular substrate. The
two magnetic polarities (north and south) are used to represent different logic values (i.e., 0 or 1). Opti-
cal disks use lasers to burn pits into reflective substrates. The binary information is represented by light
either being reflected (no pit) or not reflected (pit present). Semiconductor memory does not have any
moving parts, so it is called solid-state memory and can hold more information per unit area than disk
memory. Regardless of the technology used to store the binary data, all memory has common attributes
and terminology that are discussed in this week.

1.1.1 Memory Map Model

The information stored in memory is called the data. When information is placed into memory, it is
called a write. When information is retrieved from memory, it is called a read. In order to access data
in memory, an address is used. While data can be accessed as individual bits, in order to reduce the
number of address locations needed, data is typically grouped into N-bit words. If a memory system

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has N = 8, this means that 8-bits of data are stored at each address. The number of address locations is
described using the variable M. The overall size of the memory is typically stated by saying "M × N". For
example, if we had a 16 × 8 memory system, that means that there are 16 address locations, each capable
of storing a byte of data. This memory would have a capacity of 16 × 8 = 128 bits. Since the address
is implemented as a binary code, the number of lines in the address bus (n) will dictate the number of
address locations that the memory system will have (M=2n ). Fig. 1.1 shows a graphical depiction of
how data resides in memory. This type of graphic is called a memory map model.

Figure 1.1: Memory map model.

1.1.2 Volatile Versus Non-volatile Memory

Memory is classified into two categories depending on whether it can store information when power is
removed or not. The term non-volatile is used to describe memory that holds information when the
power is removed, while the term volatile is used to describe memory that loses its information when
power is removed. Historically, volatile memory is able to run at faster speeds compared to non-volatile
memory, so it is used as the primary storage mechanism while a digital system is running. Non-volatile
memory is necessary in order to hold critical operation information for a digital system such as start-up
instructions, operations systems, and applications.

1.1.3 Read-Only Versus Read/Write Memory

Memory can also be classified into two categories with respect to how data is accessed. Read-only
memory (ROM) is a device that cannot be written to during normal operation. This type of memory is
useful for holding critical system information or programs that should not be altered while the system is
running. Read/write memory refers to memory that can be read and written to during normal operation
and is used to hold temporary data and variables.

1.1.4 Random Access Versus Sequential Access

Random-access memory (RAM) describes memory in which any location in the system can be ac-
cessed at any time. The opposite of this is sequential access memory, in which not all address locations
are immediately available. An example of a sequential access memory system is a tape drive. In order
to access the desired address in this system, the tape spool must be spun until the address is in a position
that can be observed. Most semiconductor memory in modern systems is random access. The terms
RAM and ROM have been adopted, somewhat inaccurately, to also describe groups of memory with
particular behavior. While the term ROM technically describes a system that cannot be written to, it has
taken on the additional association of being the term to describe non-volatile memory. While the term
RAM technically describes how data is accessed, it has taken on the additional association of being the

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term to describe volatile memory. When describing modern memory systems, the terms RAM and ROM
are used most commonly to describe the characteristics of the memory being used; however, modern
memory systems can be both read/write and non-volatile, and the majority of memory is random access.
In-class Question 1: An 8-bit wide memory has eight address lines. What is its capacity in bits?

A) 64

B) 256

C) 1024

D) 2048

1.2 Non-volatile Memory Technology

1.2.1 ROM Architecture
This section describes some of the most common non-volatile memory technologies used to store digital
information. An address decoder is used to access individual data words within the memory system.
The address decoder asserts one and only one word line (WL) for each unique binary address that is
present on its input. This operation is identical to a binary-to-one-hot decoder. For an n-bit address,
the decoder can access 2n , or M words in memory. The word lines historically run horizontally across
the memory array; thus they are often called row lines, and the word line decoder is often called the
row decoder. Bit lines (BL) run perpendicular to the word lines in order to provide individual bit
storage access at the intersection of the bit and word lines. These lines typically run vertically through
the memory array; thus they are often called column lines. The output of the memory system (i.e.,
Data_Out) is obtained by providing an address and then reading the word from buffered versions of
the bit lines. When a system provides individual bit access to a row, or access to multiple data words
sharing a row line, a column decoder is used to route the appropriate bit line(s) to the data out port.
In a traditional ROM array, each bit line contains a pull-up network to VCC . This provides the ability
to store a logic 1 at all locations within the array. If a logic 0 is desired at a particular location, an NMOS
pull-down transistor is inserted. The gate of the NMOS is connected to the appropriate word line, and
the drain of the NMOS is connected to the bit line. When reading, the word line is asserted and turns
on the NMOS transistor. This pulls the bit line to GND and produces a logic 0 on the output. When the
NMOS transistor is excluded, the bit line remains at a logic 1 due to the pull-up network. Fig. 1.2 shows
the basic architecture of a ROM.

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 Figure 1.2: Basic architecture of read-only memory (ROM).

Figure 10.3 shows the operation of a ROM when information is being read.

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 Figure 1.3: ROM operation during a read.

Memory can be designed to be either asynchronous or synchronous. Asynchronous memory up-

dates its data outputs immediately upon receiving an address. Synchronous memory only updates its
data outputs on the rising edge of a clock. The term latency is used to describe the delay between when a
signal is sent to the memory (either the address in an asynchronous system or the clock in a synchronous
system) and when the data is available. Fig. 1.4 shows a comparison of the timing diagrams between
asynchronous and synchronous ROM systems during a read cycle.

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 Figure 1.4: Asynchronous vs. synchronous ROM operation during a read cycle.

1.2.2 Mask Read-Only Memory (MROM)

A mask read-only memory (MROM) is a non-volatile device that is programmed during fabrication.
The term mask refers to a transparent plate that contains patterns to create the features of the devices
on an integrated circuit using a process called photolithography. An MROM is fabricated with all of
the features necessary for the memory device with the exception of the final connections between the
NMOS transistors and the word and bit lines. This allows the majority of the device to be created prior to
knowing what the final information to be stored is. Once the desired information to be stored is provided
by the customer, the fabrication process is completed by adding connections between certain NMOS
transistors and the word/bit lines in order to create logic 0’s. Fig. 1.5 shows an overview of the MROM
programming process.

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 Figure 1.5: MROM overview.

1.2.3 Programmable Read-Only Memory (PROM)

A programmable read-only memory (PROM) is created in a similar manner as an MROM except that
the programming is accomplished post-fabrication through the use of fuses or anti-fuses. A fuse is an
electrical connection that is normally conductive. When a certain amount of current is passed through the
fuse, it will melt, or blow, and create an open circuit. The amount of current necessary to open the fuse
is much larger than the current the fuse would conduct during normal operation. An anti-fuse operates
in the opposite manner as a fuse. An anti-fuse is normally an open circuit. When a certain amount of
current is forced into the anti-fuse, the insulating material breaks down and creates a conduction path.
This turns the anti-fuse from an open circuit into a wire. Again, the amount of current necessary to close
the anti-fuse is much larger than the current the anti-fuse would experience during normal operation. A
PROM uses fuses or anti-fuses in order to connect/disconnect the NMOS transistors in the ROM array
to the word/bit lines. A PROM programmer is used to burn the fuses or anti-fuses. A PROM can only
be programmed once in this manner; thus it is a read-only memory and non-volatile. A PROM has the
advantage that programming can take place quickly as opposed to an MROM that must be programmed
through device fabrication. Fig. 1.6 shows an example PROM device based on fuses.

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 Figure 1.6: PROM overview.

Fig. 1.7 shows a PROM programmer and also a PROM memory device.

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 Figure 1.7: Data IO 29B Universal PROM Programmer.

1.2.4 Erasable Programmable Read-Only Memory (EPROM)

As an improvement to the one-time programming characteristic of PROMs, an electrically programmable
ROM with the ability to be erased with ultraviolet (UV) light was created. The erasable programmable
read-only memory (EPROM) is based on a floating-gate transistor. In a floating-gate transistor, an
additional metal-oxide structure is added to the gate of an NMOS. This has the effect of increasing the
threshold voltage. The geometry of the second metal-oxide is designed such that the threshold voltage
is high enough that normal CMOS logic levels are not able to turn the transistor on (i.e., VT1 ≥ VCC ).
This threshold can be changed by applying a large electric field across the two metal structures in the
gate. This causes charge to tunnel into the secondary oxide, ultimately changing it into a conductor. This
phenomenon is called Fowler-Nordheim tunneling. The new threshold voltage is low enough that normal
CMOS logic levels are not able to turn the transistors off (i.e., VT2 ≤ GND). This process is how the
device is programmed. This process is accomplished using a dedicated programmer; thus the EPROM
must be removed from its system to program. Fig. 1.8 shows an overview of a floating-gate transistor
and how it is programmed.

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 Figure 1.8: Floating-gate transistor - Programming.

In order to change the floating-gate transistor back into its normal state, the device is exposed to a
strong ultraviolet light source. When the UV light strikes the trapped charge in the secondary oxide, it
transfers enough energy to the charge particles that they can move back into the metal plates in the gate.
This, in effect, erases the device and restores it back to a state with a high threshold voltage. EPROMs
contain a transparent window on the top of their package that allows the UV light to strike the devices.
The EPROM must be removed from its system to perform the erase procedure. When the UV light
erase procedure is performed, every device in the memory array is erased. EPROMs are a significant
improvement over PROMs because they can be programmed multiple times; however, the programming
and erase procedures are manually intensive and require an external programmer and external eraser.
Fig. 1.9 shows the erase procedure for a floating-gate transistor using UV light.

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 Figure 1.9: Floating-gate transistor - Erasing with UV light.

An EPROM array is created in the exact same manner as in a PROM array with the exception that ad-
ditional programming circuitry is placed on the IC and a transparent window is included on the package
to facilitate erasing. An EPROM is non-volatile and read-only since the programming procedure takes
place outside of its destination system.
Fig. 1.10 shows an EPROM IC.

Figure 1.10: An example of an FEPROM IC.

1.2.5 Electrically Erasable Programmable Read-Only Memory (EEPROM)

In order to address the inconvenient programming and erasing procedures associated with EPROMs, the
electrically erasable programmable ROM (EEPROM) was created. In this type of circuit, the float-
ing-gate transistor is erased by applying a large electric field across the secondary oxide. This electric
field provides the energy to move the trapped charge from the secondary oxide back into the metal plates
of the gate. The advantage of this approach is that the circuitry to provide the large electric field can be
generated using circuitry on the same substrate as the memory array, thus eliminating the need for an
external UV light eraser. In addition, since the circuitry exists to generate large on-chip voltages, the
device can also be programmed without the need for an external programmer. This allows an EEPROM
to be programmed and erased while it resides in its target environment. Fig. 1.11 shows the procedure
for erasing a floating-gate transistor using an electric field.

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 Figure 1.11: Floating-gate transistor - Erasing with electricity.

Early EEPROMs were very slow and had a limited number of program/erase cycles; thus they were
classified into the category of non-volatile, read-only memory. Modern floating-gate transistors are now
capable of access times on scale with other volatile memory systems; thus they have evolved into one of
the few non-volatile, read/write memory technologies used in computer systems today.

1.2.6 FLASH Memory

One of the early drawbacks of EEPROM was that the circuitry that provided the capability to program
and erase individual bits also added to the size of each individual storage element.
In addition, customers were growing weary of the UV erase required to reprogram an EPROM. They
wanted the electrically erase capability of the new high-priced EEPROM technology at EPROM prices
(1980s).
In 1985, Toshiba was the first to announce a single transistor electrically erasable memory and coined
the name "Flash memory" as the new device erased in a "flash". Fujio Masuoka, while working for
Toshiba, proposed a new type of floating-gate memory that allowed entire sections of memory to be
erased quickly and easily, by applying a voltage to a single wire connected to a group of cells. This
led to Masuoka’s invention of flash memory at Toshiba. According to Toshiba, the name "flash" was
suggested by Masuoka’s colleague, Shōji Ariizumi, because the erasure process of the memory contents
reminded him of the flash of a camera.
By 1985, Intel had a working 64-kb Flash memory in the lab but refused to commercialize it due
to failure of Toshiba. Due to advancements in technology that allowed shrinking the transistor size
Intel could manufacture a 256-kb Flash memory as a replacement of EPROMs. In upcoming years, new
customer desired features were added to Flash memory such as the memory array was segmented into in-
dependently erasable blocks and all the control circuitry was placed on-chip for automated programming
and erase functions. Charge pumps were added to eliminate the need for a high-voltage program/erase
supply voltage. New innovative packaging such as Thin small outline package (TSOP), "bumped" bare
die, and memory cards (See Fig. 1.12) were utilized to enter the portable equipment market.

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 Figure 1.12: Flash memory packaging variations.

Flash memory technology has evolved in two major directions. In the early years of Flash, there
was only a single type of Flash, NOR Flash. NOR Flash has a random-access memory cell optimized
for high-speed applications such as the cell phone and other code storage applications. A serial-based
NAND Flash technology was created to meet the emerging needs of the low-cost file storage market
that can live with a slow serial read access time. The primary NAND Flash applications are the digital
camera and the portable MP3 music players.
To understand the flash memory we should first look at a single flash memory cell which is basically
a floating-gate MOSFET transistor.

1.2.6.1 Flash Memory Cell: Floating-Gate MOSFET Transistor

Fig. 1.13 shows a flash memory cell. In flash memory, each memory cell resembles a standard metal-
oxide-semiconductor field-effect transistor (MOSFET) except that the transistor has two gates instead of
one. The cells can be seen as an electrical switch in which current flows between two terminals (source
and drain) and is controlled by a floating gate (FG) and a control gate (CG). The CG is similar to the
gate in other MOS transistors, but below this, there is the FG insulated all around by an oxide layer. The
FG is interposed between the CG and the MOSFET channel. Because the FG is electrically isolated by
its insulating layer, electrons placed on it are trapped.
In a Floating-Gate MOSFET Transistor, information is stored in the cell by adjusting the threshold
voltage (VT or VTH ). When the FG is charged with electrons, this charge screens the electric field from
the CG, thus, increasing the threshold voltage (VT ) of the cell. This means that the VT of the cell can be
changed between the uncharged FG threshold voltage (VT1 ) and the higher charged FG threshold voltage
(VT2 ) by changing the FG charge.

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 Figure 1.13: A flash memory cell.

We can perform 3 operations to this cell:

1. Program the cell (Write value 0)

2. Read its value

3. Erase the cell (Write value 1)

A flash memory cell in its default uncharged state holds binary value 1. To program the cell means to
store binary value 0 into by charging it (put electric charges on FG) and to erase a cell means to perform
the opposite operation and remove the charges off the FG and set its stored value back to 1. Finally, to
read a cell value we need to sense current that can pass through it when we apply a certain voltage level
to CG.
In order to read a value from the cell, an intermediate voltage (VI ) between VT1 and VT2 is applied
to the CG. If the channel conducts at VI , the FG must be uncharged (if it were charged, there would not
be conduction because VI is less than VT2 ). If the channel does not conduct at the VI , it indicates that
the FG is charged. The binary value of the cell is sensed by determining whether there is current flowing
through the transistor when VI is asserted on the CG. In a multi-level cell device, which stores more than
one bit per cell, the amount of current flow is sensed (rather than simply its presence or absence), in
order to determine more precisely the level of charge on the FG.

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 In order to write value 0 to the cell we have to move electrons from the control gate into the floating
gate. This process is called Fowler–Nordheim tunneling, and it fundamentally changes the charac-
teristics of the cell by increasing the MOSFET’s threshold voltage (VTH ). This, in turn, changes the
drain-source current that flows through the transistor for a given gate voltage, which is ultimately used
to encode a binary value 0 (Or 1). The Fowler-Nordheim tunneling effect is reversible, so electrons can
be added to or removed from the floating gate, processes traditionally known as writing and erasing.
To recap: To write 0 we move electrons into FG, To write 1 we remove the electrons off FG (erasing)
and to read we sense the drain-source current.
After understanding the operation of a flash memory cell we can see that it only is able to store just
one bit of data 0 or 1. Therefore, we need put a group of these cells together to store string of bits. We
will briefly look into the architecture of NAND and NOR flash memories which are strings of array of
the floating-gate MOSFETs.
Fig. 1.14 shows schematic of NMOS and resistor NAND and NOR gates which is placed here to
remind us the transistor-level (NMOS + resistor) operation of these gates.

Figure 1.14: NMOS 2-Input NAND and NOR Gates Schematic.

1.2.6.2 NOR Flash Memory

Fig. 1.15 shows NOR flash memory wiring and structure on silicon. As can be seen in the figure,
transistors are connected in parallel similar to the 2-input NOR gate of Fig. 1.14. That is why they are
called NOR Flash memory.
In NOR flash memory, the source pin of each floating-gate MOSFET is connected to the Source Line
which is connected to the ground. The drain pin of each transistor is connected to Bit Line (BL).
We will discuss briefly how the three fundamental operations can be done in a NOR flash memory.
Let’s assume that we would like to access memory cell connected to Word Line 3 and perform the
following 3 operations:

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 1. Read (Sensing): Apply 0v to all Word lines except Word Line 3. Apply VI (e.g., +4v) to Word
Line 3. Connect Source Line to the ground. Apply VCC to BL, then Bit Line (BL) output will be a
function of the transistor state connected to Word Line 3:

• If FG is uncharged, then the channel conducts and the ground will be connected to the BL.
(Ground appearing on BL indicates a read binary value 1)
• If FG is charge (memory cell is programmed to hold binary value 0 by applying an elevated
on-voltage to the CG), then the channel does not conduct and VCC will be connected to the
BL. (VCC appearing on BL indicates a read binary value 0)

2. Programming (Storing 0): Apply programming voltage (is higher voltage level than binary 1,
e.g., +10v) to Word Line 3 CG. Connect Source Line to the ground. Apply programming drain
voltage to BL (e.g., +5v).

3. Erasing (Storing 1): Apply negative programming voltage (e.g., -10v) to Word Line 3 CG. Con-
nect Source Line to positive erase voltage (e.g., +3v). Leave the BL floating.

Figure 1.15: NOR flash memory wiring and structure on silicon.

1.2.6.3 NAND Flash Memory

Fig. 1.16 shows NAND flash memory wiring and structure on silicon. As can be seen in the figure,
transistors are connected in series similar to the 2-input NAND gate of Fig. 1.14. That is why they are
called NAND Flash memory.
The source pin of each floating-gate MOSFET is connected to the drain pin of another transistor in
series. The BL is pulled low only if all the word lines are pulled high (above the transistors’ VT ). The
Ground select transistor (GST) and Bit line transistor (BLT) are placed in series to switch on/off the
connection of NAND bits string to the source line (ground) and Bit line (BL).
We will discuss briefly how the three fundamental operations can be done in a NAND flash memory.
Let’s assume that we would like to access memory cell connected to Word Line 3 and perform the
following 3 operations:

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 1. Read (Sensing): Apply VCC to all Word lines except Word Line 3. Apply VI (e.g., +4v) to Word
Line 3. Apply VCC to GST to turn it on. Apply VCC to BLT to turn it on. Apply VCC to BL, then
Bit Line (BL) output will be a function of the transistor state connected to Word Line 3:

• If FG is uncharged, then the channel conducts and the ground will be connected to the BL.
(Ground appearing on BL indicates a read binary value 1)
• If FG is charge (memory cell is programmed to hold binary value 0 by applying an elevated
on-voltage to the CG), then the channel does not conduct and VCC will be connected to the
BL. (VCC appearing on BL indicates a read binary value 0)

2. Programming (Storing 0 or 1): Apply programming voltage (higher voltage level than binary
1 voltage or VCC , e.g., +19v) to Word Line 3’s CG. Apply programming deselect voltage (e.g.,
+12v) to other word lines’ CG. Apply VCC (e.g., +5v) to BLT to turn it on. Apply 0v to GST to
turn it off. Apply VCC (e.g., +5v) to Source Line. Apply 0v to P-well. The BL is at 0v if the data
to be programmed is logic 0 or at VCC if the data is logic 1.

3. Erasing (Storing 1): Apply 0V to all the word lines. Apply 0v to BLS and set GST and BL to
floating. Apply elevated erasing voltage to P-well (e.g. +20v). Not that as we can see here, NAND
string can be erased in bulk.

The structure in Fig. 1.16 can store 8 bits in eight separate floating gate transistors. This is a byte
array - it contains an eight bit byte spread across eight transistors. Basically, to read data, first the desired
group is selected (in the same way that a single transistor is selected from a NOR array). Next, most
of the word lines are pulled up above VT2 , while one of them is pulled up to VI . The series group will
conduct (and pull the bit line low) if the selected bit has not been programmed.

Figure 1.16: NAND flash memory wiring and structure on silicon.

A NAND flash chip (or "package") is divided into the following entities as can be seen in Fig. 1.17:
the die, the plane, the block and the page. Blocks are the smallest unit that can be erased, and pages are
the smallest unit that can be programmed.

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 Figure 1.17: NAND Flash Die Layout.

A page is a collection of Bit lines attached on a single Word line. One word-line can contain one or
more pages. One page typically consists of 256 or 512 bytes of memory (2048 or 4096 bits). Fig. 1.18
shows a group of Bit lines that form a page. if a page size has 32,768 NAND Cells (bits), this equates to
4096 bytes or 4K Page size.

Figure 1.18: NAND Page marked with yellow rectangle - The whole image is a NAND block.

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1.2.6.4 NOR vs NAND Flash Memory
Table 1.1 show the comparison of NOR versus NAND flash memories.

Table 1.1: NOR vs NAND flash memory comparison.

NOR Flash NAND Flash
Non-volatile memory Non-volatile memory
Larger cell area Smaller cell area
Lesser density Higher density
Capacities of 32Mb to 2Gb Capacities of 128Mb to 2Tb
Block size = 64KB to 256KB Block size = 8KB to 32KB
Higher cost ($) per bit Lower cost ($) per bit
Memory cells are in parallel Memory cells are in series
Very slow erase* Fast erase
Faster read speed Slower read speed
Slower write speed Slow write speed
Read access level: Page/Byte/Bit Read access level: Page
Write access level: Page/Byte/Bit Write access level: Page
Erase access level: Block Erase access level: Block
Used for storing variable data and code execu- Used for data storage
tion
Cell phones, Scientific Instruments and medical Set-top boxes (STBs), digital televisions, SSDs,
devices tablets, and USB drives
Higher power usage during boot/read Higher power usage during standby
*
NOR cells are larger and also they need "pre-program". The "pre-program" refers to the operation
of checking the existing data bits and programming any bits from the ’1’ (erase) state to the ’0’
(program) state. NOR flash needs a "pre-program" before the erase to avoid "over-erased" cells.

In both NOR and NAND Flash, the memory is organized into erase blocks. This architecture helps
maintain lower cost while maintaining performance. For example, a smaller block size enables faster
erase cycles. The downside of smaller blocks, however, is an increase in die area and memory cost.
NAND architecture enables placement of more cells in a smaller area compared to the NOR architec-
ture. For similar process technology, the physical design of NAND flash cells allows for approximately
40% less area coverage than NOR flash cells. The lower cost per bit also contributes to the higher density
of NAND memory devices.
NOR flash memory enables faster read operations because the cells are wired in parallel. Instead of
reading out an entire word line into a register and parsing it, an individual bit can be accessed as needed.
However, this makes NOR flash slower to write and erase than NAND because of its greater cell size; in
NOR flash, each bit must be written to a 0 before it can be erased.
The memory cells in a NAND are joined in series and arranged into pages, which are further divided
into blocks. NAND reads are slower, but NAND writes and erases are faster than NOR because large
groups of bits can be erased simultaneously.
NOR draws a higher current when turned on, but it uses less power when idle. While NAND has
a lower initial power consumption, its standby power consumption is higher. The instantaneous active
power of NOR and NAND flash memories is almost similar, so the total energy consumption will depend
on the amount of time the memory is actively being read or written.
The limitation of NAND FLASH was that reading and writing could only be accomplished in a
block-by-block basis. This characteristic precluded the use of NAND FLASH for run-time variables and

20
data storage but was well suited for streaming applications such as audio/video and program loading. As
NAND FLASH technology advanced, the block size began to shrink, and software adapted to accom-
modate the block-by-block data access. This expanded the applications that NAND FLASH could be
deployed in. Today, NAND FLASH memory is used in nearly all portable devices (e.g., smartphones,
tablets, etc.), and its use in solid-state hard drives (SSD) is on pace to replace hard disk drives and
optical disks as the primary non-volatile storage medium in modern computers.
NOR FLASH is considered random-access memory, while NAND FLASH is typically not; however,
as the block size of NAND FLASH is continually reduced, its use for variable storage is becoming more
attractive. All FLASH memory is non-volatile and read/write.
The chart in Fig. 1.19 shows various NOR and NAND density ranges to help identify the best solution
for your application requirements.

Figure 1.19: Various densities of NOR versus NAND Micron flash memories.

In-class Question 2: Which of the following is suitable for implementation in a read-only memory?

A) Variables that a computer program needs to continuously update

B) Information captured by a digital camera

C) A computer program on a spacecraft

D) Incoming digitized sound from a microphone

1.3 Volatile Memory Technology

This section describes some common volatile memory technologies used to store digital information.

1.3.1 Static Random-Access Memory (SRAM)

Static random-access memory (SRAM) is a semiconductor technology that stores information using
a cross-coupled inverter feedback loop. Fig. 1.20 shows the schematic for the basic SRAM storage

21
cell. In this configuration, two access transistors (M1 and M2) are used to read and write from the
storage cell. The cell has two complementary ports called bit line (BL) and bit line’ (BLn). Due to
the inverting functionality of the feedback loop, these two ports will always be the complement of each
other. This behavior is advantageous because the two lines can be compared to each other to determine
the data value. This allows the voltage levels used in the cell to be lowered while still being able to
detect the stored data value. Word lines are used to control the access transistors. This storage element
takes six CMOS transistors to implement and is often called a 6T configuration. The advantage of this
memory cell is that it has very fast performance compared to other sub-systems because of its underlying
technology being simple CMOS transistors. SRAM cells are commonly implemented on the same IC
substrate as the rest of the system, thus allowing a fully integrated system to be realized. SRAM cells
are used for cache memory in computer systems.

Figure 1.20: SRAM storage element (6T).

To build an SRAM memory system, cells are arranged in an array pattern. Fig. 1.21 shows a 4x4
SRAM array topology. In this configuration, word lines are shared horizontally across the array in order
to provide addressing capability. An address decoder is used to convert the binary-encoded address
into the appropriate word line assertions. N storage cells are attached to the word line to provide the
desired data word width. Bit lines are shared vertically across the array in order to provide data access
(either read or write). A data line controller handles whether data is read from or written to the cells
based on an external write enable (WE) signal. When WE is asserted (WE = 1), data will be written to the
cells. When WE is de-asserted (WE = 0), data will be read from the cells. The data line controller also
handles determining the correct logic value read from the cells by comparing BL to BLn. As more cells
are added to the bit lines, the signal magnitude being driven by the storage cells diminishes due to the
additional loading of the other cells. This is where having complementary data signals (BL and BLn) is
advantageous because this effectively doubles the magnitude of the storage cell outputs. The comparison
of BL to BLn is handled using a differential amplifier that produces a full logic level output even when
the incoming signals are very small.

22
 Figure 1.21: 4x4 SRAM array topology.

1.3.1.1 Differential amplifier [Will not be included in final exam]

A differential (or difference) amplifier is a two-input circuit that amplifies only the difference between
its two inputs. The symbol of an operational amplifier or op-amp is shown in Fig. 1.22. The formula
that describes the behavior of the circuit is:

Vout = A ∗ (Vin+ − Vin− ) (1.1)

Where A is amplification coefficient (gain of amplifier).

23
 Figure 1.22: Operational Amplifier Symbol.

We can use either the "inverting" or the "non-inverting" op-amp input terminals to amplify a single
input signal with the other input being connected to ground.
Differential amplifiers are useful in electrically noisy environments where a low amplitude electrical
signal can be easily corrupted by the effect of unwanted external noise. In this scenario, a single-ended
amplifier would be unsuitable since it would also amplify the unwanted noise signal as well as the
desired input signal. A differential amplifier works on the principle that unwanted electrical noise cou-
ples equally onto both input terminals of the amplifier and will therefore be rejected allowing only the
wanted signal to be amplified.
Fig. 1.23 shows the required resistors and how they should be connected to op-amp inputs and output.
The op-amp output equation is as follows:
R3
Vout = ∗ (V2 − V1 ) (1.2)
R1

Figure 1.23: Operational amplifier with required resistors circuit.

If all resistors in Fig. 1.23 are equal then we have a Unity Gain Differential Amplifier where
R1 = R2 = R3 = R4 and the op-amp equation will be the following:

Vout = (V2 − V1 ) (1.3)

Now, to understand how differential op-amp can get rid of noise, imagine a balanced microphone as
shown in Fig. 1.24 is connected to a differential op-amp.

24
 Figure 1.24: Balanced microphone (has 3 wires in contrast to unbalanced mic that has 2).

The output of differential op-amp is:

Vout = (V+ − V− ) (1.4)

= (V+ + V+ ) (1.5)
= 2 × V+ (1.6)

If we have noise added to the microphone output then it will be added to both inverting and non-
inverting inputs, therefore we the noise will be canceled out:

Voutn oise = (N+ − N+ ) (1.7)

=0 (1.8)

We can also have single-input, two-output differential op-amp. Fully differential op-amps add a
second output. The output is fully differential - the two outputs are called positive output and negative
output - similar terminology to the two inputs. Like the inputs, they are differential. The output voltages
are equal, but opposite in polarity.
As we understood the operation of op-amps, we shall continue the SRAM topic.

25
 SRAM is volatile memory because when the power is removed, the cross-coupled inverters are not
able to drive the feedback loop and the data is lost. SRAM is also read/write memory because the storage
cells can be easily read from or written to during normal operation. Let’s look at the operation of the
SRAM array when writing the 4-bit word "0111" to address "01"
Fig. 1.25 shows a graphical depiction of this operation. In this write cycle, the row address decoder
observes the address input "01" and asserts WL1. Asserting this word line enables all of the access
transistors (i.e., M1 and M2 in Fig. 1.20) of the storage cells in this row. The line drivers are designed to
have a stronger drive strength than the inverters in the storage cells so that they can override their values
during a write. The information "0111" is present on the Data_In bus, and the write enable control
line is asserted (WE = 1) to indicate a write. The data line controller passes the information to be stored
to the line drivers, which in turn converts each input into complementary signals (via differential two
output op-amps) and drives the bit lines. This overrides the information in each storage cell connected
to WL1. The address decoder then de-asserts WL1 and the information is stored.

Figure 1.25: SRAM operation during a write cycle – Storing "0111" to Address "01".

26
 Now let’s look at the operation of the SRAM array when reading a 4-bit word from address "10".
Let’s assume that this row was storing the value "1010". Figure 10.13 shows a graphical depiction of this
operation. In this read cycle, the row address decoder asserts WL2, which allows the SRAM cells to drive
their respective bit lines. Note that each cell drives a complementary version of its stored value. The
input control line is de-asserted (WE = 0), which indicates that the sense amplifiers will read the BL and
BLn lines in order to determine the full logic value stored in each cell. This logic value is then routed to
the Data_Out port of the array. In an SRAM array, reading from the cell does not impact the contents
of the cell. Once the read is complete, WL2 is de-asserted and the read cycle is complete.

Figure 1.26: SRAM operation during a read cycle – Reading "0101" from Address "10".

1.3.2 Dynamic Random-Access Memory (DRAM)

Dynamic random-access memory (DRAM) is a semiconductor technology that stores information us-
ing a capacitor. A capacitor is a fundamental electrical device that stores charge. Fig. 1.27 shows the

27
schematic for the basic DRAM storage cell. The capacitor is accessed through a transistor (M1). Since
this storage element takes one transistor and one capacitor, it is often referred to as a 1T1C configuration.
Just as in SRAM memory, word lines are used to access the storage elements. The term digit line is used
to describe the vertical connection to the storage cells. DRAM has an advantage over SRAM in that
the storage element requires less area to implement. This allows DRAM memory to have much higher
density compared to SRAM.

Figure 1.27: DRAM storage element (1T 1C).

There are a variety of considerations that must be accounted for when using DRAM. First, the charge
in the capacitor will slowly dissipate over time due to the capacitors being non-ideal. If left unchecked,
eventually the data held in the capacitor will be lost. In order to overcome this issue, DRAM has a
dedicated circuit to refresh the contents of the storage cell. A refresh cycle involves periodically reading
the value stored on the capacitor and then writing the same value back again at full signal strength. This
behavior also means that that DRAM is volatile because when the power is removed, and the refresh
cycle cannot be performed, the stored data is lost. DRAM is also considered read/write memory because
the storage cells can be easily read from or written to during normal operation.
Another consideration when using DRAM is that the voltage of the word line must be larger than
VCC in order to turn on the access transistor. In order to turn on an NMOS transistor, the gate terminal
must be larger than the source terminal by at least a threshold voltage (VT ). In traditional CMOS circuit
design, the source terminal is typically connected to ground (0v). This means the transistor can be easily
turned on by driving the gate with a logic 1 (i.e., VCC ) since this creates a VGS voltage much larger than
VT . This is not always the case in DRAM. In DRAM, the source terminal is not connected to ground but
rather to the storage capacitor. In the worst-case situation, the capacitor could be storing a logic 1 (i.e.,
VCC ). This means that in order for the word line to be able to turn on the access transistor, it must be
equal to or larger than (VCC + VT ). This is an issue because the highest voltage that the DRAM device
has access to is VCC . In DRAM, a charge pump is used to create a voltage larger than VCC + VT that
is driven on the word lines. Once this voltage is used, the charge is lost, so the line must be pumped
up again before its next use. The process of "pumping up" takes time that must be considered when
calculating the maximum speed of DRAM. Fig. 1.28 shows a graphical depiction of this consideration.

28
 Figure 1.28: DRAM charge pumping of word lines.

1.3.2.1 Charge Pump [Will not be included in final exam]

A charge pump is a kind of DC-to-DC converter that uses capacitors for energetic charge storage to raise
or lower voltage. Charge-pump circuits are capable of high efficiencies, sometimes as high as 90–95%,
while being electrically simple circuits.
The charge-pump circuit uses capacitors to achieve higher voltages. The simplest such circuit is a
voltage doubler. The circuit has two states, which it continually switches between. The first state (the
one depicted in Fig. 1.29) is the charging state. In this state capacitor C1 (sometimes referred to as the
flying capacitor) charges to VIN .

Figure 1.29: The voltage doubler - State 1: Charging state.

Figure 1.30: The voltage doubler - State 2: Charging transfer state.

29
 The second state, the charge transfer state, has the two switches in their opposite configuration (left
switch up, right switch down). What happens in that case? Fig. 1.30 depicts the circuit. Assume that
C2 is initially at 0 V. C1, which had VIN volts across it prior to the switch, transfers some of its charge
to capacitor C2. As a result, the voltage across C2 rises while the voltage across C1 falls. The output
voltage (the C2 voltage) rises to a value between VIN and 2xVIN .
The circuit is then commanded to revert to its charging state (Fig. 1.29) and the voltage across C1
is replenished to VIN (the voltage across C2 remains at its charged value, assuming no load). When it
is then commanded to the charge transfer state, C1 again transfers some of its charge to C2. After this
charge transfer, the voltage across C2 is higher than during the previous charge transfer state. As this
process continues, the output voltage gradually approaches its final value of 2VIN . Once the circuit gets
past the initial transient voltage buildup, this circuit maintains the 2VIN output value.
Of course, we assumed no load on VOUT - not a very practical assumption for a circuit intended to
provide a supply voltage to some load. Nevertheless, as long as the load is relatively light, the circuit
will maintain very nearly double the input voltage.
Charge-pumped circuits similar to the voltage doubler can be built to provide higher voltages, usually
integer-multiples of the input voltage (that is, 2x , 3x , etc.).
Another consideration when using DRAM is how the charge in the capacitor develops into an actual
voltage on the digital line when the access transistor is closed. Consider the simple 4x4 array of DRAM
cells shown in Fig. 1.31. In this topology, the DRAM cells are accessed using the same approach as in
the SRAM array from Fig. 1.21.

Figure 1.31: Simple 4x4 DRAM array topology.

One of the limitations of this simple configuration is that the charge stored in the capacitors cannot

30
develop a full voltage level across the digit line when the access transistor is closed. This is because
the digit line itself has capacitance that impacts how much voltage will be developed. In practice, the
capacitance of the digit line (CDL ) is much larger than the capacitance of the storage cell (CS ) due to
having significantly more area and being connected to numerous other storage cells. This becomes an
issue because when the storage capacitor is connected to the digit line, the resulting voltage on the digit
line (VDL ) is much less than the original voltage on the storage cell (VS ). This behavior is known as
charge sharing because when the access transistor is closed, the charge on both capacitors is distributed
across both devices and results in a final voltage that depends on the initial charge in the system and the
values of the two capacitors. Fig. 1.32 shows an example of how to calculate the final digit line voltage
when the storage cell is connected.

Figure 1.32: Calculating the final digit line voltage in a DRAM based on charge sharing.

31
 The issue with the charge sharing behavior of a DRAM cell is that the final voltage on the word line
is not large enough to be detected by a standard logic gate or latch. In order to overcome this issue,
modern DRAM arrays use complementary storage cells and sense amplifiers. The complementary cells
store the original data and its complement. Two digit lines (DL and DLn) are used to read the contents
of the storage cells. DL and DLn are initially pre-charged to exactly VCC /2. When the access transistors
are closed, the storage cells will share their charge with the digit lines and move them slightly away
from VCC / 2 in different directions. This allows twice the voltage difference to be developed during a
read. A sense amplifier is then used to boost this small voltage difference into a full logic level that can
be read by a standard logic gate or latch. Fig. 1.33 shows the modern DRAM array topology based on
complementary storage cells.

Figure 1.33: Modern DRAM array topology based on complementary storage cells.

The sense amplifier is designed to boost small voltage deviations from VCC /2 on DL and DLn to full
logic levels. The sense amplifier sits in-between DL and DLn and has two complementary networks, the
N-sense amplifier and the P-sense amplifier. The N-sense amplifier is used to pull a signal that is below
VCC /2 (either DL or DLn) down to GND. A control signal (N-Latch or NLATn) is used to turn on this

32
network. The P-sense amplifier is used to pull a signal that is above VCC /2 (either DL or DLn) up to
VCC . A control signal (Active Pull-Up or ACT) is used to turn on this network. The two networks are
activated in a sequence with the N-sense network activating first. Fig. 1.34 shows an overview of the
operation of a DRAM sense amplifier.

Figure 1.34: DRAM sense amplifier.

Let’s now put everything together and look at the operation of a DRAM system during a read op-
eration. Fig. 1.35 shows a simplified timing diagram of a DRAM read cycle. This diagram shows the
critical signals and their values when reading a logic 1. Notice that there is a sequence of steps that must
be accomplished before the information in the storage cells can be retrieved.

33
 Figure 1.35: DRAM operation during a read cycle – Reading a 1 from a storage cell.

A DRAM write operation is accomplished by opening the access transistors to the complementary
storage cells using WL, disabling the pre-charge drivers and then writing full logic level signals to the
storage cells using the Data_In line driver.
In-class Question 3: Which of the following is suitable for implementation in a read/write memory?

A) A look up table containing the values of sine function.

B) Information captured by a digital camera.

C) The boot up code for a computer.

D) A computer program on a spacecraft.

34
 1.4 Modeling Memory with Verilog
1.4.1 Read-Only Memory in Verilog
A read-only memory in Verilog can be defined in two ways. The first is to simply use a case statement
to define the contents of each location in memory based on the incoming address. A second approach
is to declare an array and then initialize its contents. When using an array, a separate procedural block
handles assigning the contents of the array to the output based on the incoming address. The array
can be initialized using either an initial block or through the file I/O system tasks $readmemb() or
$readmemh(). Fig. 1.36 shows the symbol of a 4x4 asynchronous read-only memory. Listing 1.1 and
listing 1.2 show two approaches for modeling a 4x4 ROM memory.
In those listings the memory is asynchronous, meaning that as soon as the address changes, the data
from the ROM will appear immediately. To model this asynchronous behavior, the procedural blocks are
sensitive to the incoming address. In the simulation (Fig. 1.37), each possible address is provided (i.e.,
"00", "01", "10", and "11") to verify that the ROM was initialized correctly. Fig. Fig. 1.37 shows that
data_out is updated immediately when the address is changed.

Figure 1.36: A 4x4 asynchronous read-only memory.

Listing 1.1: Behavioral models of a 4x4 asynchronous read-only memory in Verilog.

1 module r o m _ 4 x 4 _ a s y n c ( o u t p u t r e g [ 3 : 0 ] d a t a _ o u t ,
2 input wire [ 1 : 0 ] address )
3

4 always @ ( address )
5 case ( address )
6 0 : data_out = 4 ’ b1110 ;
7 1 : data_out = 4 ’ b0010 ;
8 2 : data_out = 4’ bl1l1 ;
9 3 : data out = 4 ’ b0100 ;
10 default : data_out = 4 ’bXXXX;
11 endcase
12

13 endmodule

Listing 1.2: Behavioral models of a 4x4 asynchronous read-only memory in Verilog (v2).
1 module r o m _ 4 x 4 _ a s y n c 2 ( o u t p u t r e g [ 3 : 0 ] d a t a _ o u t ,
2 input wire [ 1 : 0 ] address )
3

4 r e g [ 3 : 0 ] ROM[ 0 : 3 ] ; / / An MxN a r r a y i s d e c l a r e d
5

35
6 i n i t i a l begin
7 ROM[ 0 ] = 4 ’ b1110 ;
8 ROM[ 1 ] = 4 ’ b0010 ;
9 ROM[ 2 ] = 4 ’ b l 1 l 1 ;
10 ROM[ 3 ] = 4 ’ b0100 ;
11 end
12

13 always @ ( address )
14 d a t a _ o u t = ROM[ a d d r e s s ] ;
15

16 endmodule

Figure 1.37: 4x4 asynchronous read-only memory simulation.

A synchronous ROM as shown in Fig. 1.38 can be created in a similar manner as in the asynchronous
approach. The only difference is that in a synchronous ROM, a clock edge is used to trigger the pro-
cedural block that updates data_out. A sensitivity list is used that contains the clock to trigger the
assignment. Listing 1.3 and Listing 1.4 show two Verilog models for a synchronous ROM. Notice in
simulation waveform of Fig. 1.39 that prior to the first clock edge, the simulator does not know what to
assign to data_out, so it lists the value as unknown (X).

Figure 1.38: A 4x4 synchronous read-only memory.

Listing 1.3: Behavioral models of a 4x4 synchronous read-only memory in Verilog.

1 module rom_4x4_sync ( o u t p u t r e g [ 3 : 0 ] d a t a _ o u t ,
2 input wire [ 1 : 0 ] address ,
3 i n p u t wire Clock )
4

5 always @ ( posedge Clock )

6 case ( address )
7 0 : d a t a _ o u t = 4 ’ b1110 ;
8 1 : d a t a _ o u t = 4 ’ b0010 ;

36
9 2 : data_out = 4’ bl1l1 ;
10 3 : d a t a o u t = 4 ’ b0100 ;
11 d e f a u l t : d a t a _ o u t = 4 ’bXXXX;
12 endcase
13

14 endmodule

Listing 1.4: Behavioral models of a 4x4 synchronous read-only memory in Verilog (v2).
1 module rom_4x4_sync ( o u t p u t r e g [ 3 : 0 ] d a t a _ o u t ,
2 input wire [ 1 : 0 ] address ,
3 i n p u t wire Clock )
4

5 i n i t i a l begin
6 ROM[ 0 ] = 4 ’ b1110 ;
7 ROM[ 1 ] = 4 ’ b0010 ;
8 ROM[ 2 ] = 4 ’ b l 1 l 1 ;
9 ROM[ 3 ] = 4 ’ b0100 ;
10 end
11

12 always @ ( posedge Clock )

13 d a t a _ o u t = ROM[ a d d r e s s ] ;
14

15 endmodule

Figure 1.39: A 4x4 synchronous read-only memory simulation.

1.4.2 Read/Write Memory in Verilog

In a simple read/write memory model (Fig. 1.40), there is an output port that provides data when reading
(data_out) and an input port that receives data when writing (data_in). Within the module, an array
signal is declared with elements of type reg. To write to the array, signal assignments are made from
the data_in port to the element within the array corresponding to the incoming address. To read from
the array, the data_out port is assigned the element within the array corresponding to the incoming
address. A write enable (WE) signal tells the system when to write to the array (WE = 1) or when to read
from the array (WE = 0). In an asynchronous R/W memory, data is immediately written to the array when
WE = 1 and data is immediately read from the array when WE = 0. This is modeled using a procedural
block with a sensitivity list containing every input to the system.

37
 Figure 1.40: A 4x4 asynchronous read/write memory.

Listing 1.5 shows an asynchronous R/W 4x4 memory system and its functional simulation results in
Fig. 1.41. In the simulation, each address is initially read from to verify that it does not contain data.
The data_out port produces unknown (X) for the initial set of read operations. Each address in the
array is then written to. Finally, the array is read from verifying that the data that was written can be
successfully retrieved.
Listing 1.5: Behavioral models of a 4x4 asynchronous read-write memory in Verilog.
1 module r w _ 4 x 4 _ a s y n c ( o u t p u t r e g [ 3 : 0 ] d a t a _ o u t ,
2 input wire [ 1 : 0 ] address ,
3 i n p u t w i r e WE,
4 input wire [ 3 : 0 ] data_in )
5

6 r e g [ 3 : 0 ] RW[ 0 : 3 ] ; / / An MxN a r r a y i s d e c l a r e d
7

8 / / This provides asynchronous behavior

9 a l w a y s @ ( a d d r e s s o r WE o r d a t a _ i n )
10 i f (WE)
11 RW[ a d d r e s s ] = d a t a _ i n ; / / W r i t i n g t o t h e RW a r r a y when WE = 1
12 else
13 d a t a _ o u t = RW[ a d d r e s s ] ; / / R e a d i n g from t h e RW a r r a y when WE = 0
14

15 endmodule

Figure 1.41: Functional simulation waveform of a 4x4 asynchronous read/write memory.

38
 A synchronous read/write memory (Fig. 1.42) is made in a similar manner with the exception that a
clock is used to trigger the procedural block managing the signal assignments. In this case, the WE signal
acts as a synchronous control signal indicating whether assignments are read from or written to the RW
array.

Figure 1.42: A 4x4 synchronous read/write memory.

Listing 1.6 shows the Verilog model for a synchronous read/write memory and the simulation wave-
form in Fig. 1.43 shows both read and write cycles.
Listing 1.6: Behavioral models of a 4x4 synchronous read-write memory in Verilog.
1 module r w _ 4 x 4 _ s y n c ( o u t p u t r e g [ 3 : 0 ] d a t a _ o u t ,
2 input wire [ 1 : 0 ] address ,
3 i n p u t w i r e WE,
4 input wire [ 3 : 0 ] data_in ,
5 i n p u t wire Clock )
6

7 r e g [ 3 : 0 ] RW[ 0 : 3 ] ;
8

9 / / This provides synchronous behavior

10 always @ ( posedge Clock )
11 i f (WE)
12 RW[ a d d r e s s ] = d a t a _ i n ;
13 else
14 d a t a _ o u t = RW[ a d d r e s s ] ;
15

16 endmodule

39
 Figure 1.43: Functional simulation waveform of a 4x4 synchronous read/write memory.

In-class Question 4: Explain the advantage of modeling memory in Verilog without going into the
details of the storage cell operation.

A) It allows the details of the storage cell to be abstracted from the functional operation of the memory
system.

B) It is too difficult to model the analog behavior of the storage cell.

C) There are too many cells to model so the simulation would take too long.

D) It lets both ROM and R/W memory to be modeled in a similar manner.

40
1.5 Assignments
1. For a 512k x 32 memory system, how many unique address locations are there? Give the exact
number.

2. For a 512k x 32 memory system, what is the data width at each address location?

3. For a 512k x 32 memory system, what is the capacity in bits?

4. For a 512k x 32-bit memory system, what is the capacity in bytes?

5. For a 512k x 32 memory system, how wide does the incoming address bus need to be in order to
access every unique address location?

6. Name the type of memory with the following characteristic: when power is removed, the data is
lost.

7. Name the type of memory with the following characteristic: when power is removed, the memory
still holds its information.

8. Name the type of memory with the following characteristic: it can only be read from during normal
operation.

9. Name the type of memory with the following characteristic: during normal operation, it can be
read and written to.

10. Name the type of memory with the following characteristic: data can be accessed from any address
location at any time.

11. Name the type of memory with the following characteristic: data can only be accessed in consec-
utive order, thus not every location of memory is available instantaneously.

12. Name the type of memory with the following characteristic: this memory is non-volatile, read-
/write, and only provides data access in blocks.

13. Name the type of memory with the following characteristic: this memory uses a floating-gate
transistor, can be erased with electricity, and provides individual bit access.

14. Name the type of memory with the following characteristic: this memory is non-volatile, read-
/write, and provides word-level data access.

15. Name the type of memory with the following characteristic: this memory uses a floating-gate
transistor that is erased with UV light.

16. Name the type of memory with the following characteristic: this memory is programmed by blow-
ing fuses or anti-fuses.

17. Name the type of memory with the following characteristic: this memory is partially fabricated
prior to knowing the information to be stored.

18. How many transistors does it take to implement an SRAM cell?

19. Why doesn’t an SRAM cell require a refresh cycle?

41
20. Design a Verilog model for the SRAM system shown in Fig. 1.44. Your storage cell should be de-
signed such that its contents can be overwritten by the line driver. Consider using signal strengths
for this behavior (e.g., strong1 will overwrite a weak0). You will need to create a system for
the differential line driver with enable. This driver will need to contain a high impedance state
when disabled. Both your line driver (Din) and receiver (Dout) are differential. These systems
can be modeled using simple if-else statements. Create a test bench for your system that will write
a 0 to the cell, then read it back to verify the 0 was stored, and then repeat the write/read cycles for
a 1.

Figure 1.44: SRAM cell block diagram.

21. Why is a DRAM cell referred to as a 1T 1C configuration?

22. Why is a charge pump necessary on the word lines of a DRAM array?

23. Why does a DRAM cell require a refresh cycle?

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24. For the DRAM storage cell shown in Fig. 1.45, solve for the final voltage on the digit line after
the access transistor (M1) closes if initially VS = VCC (i.e., the cell is storing a 1). In this system,
CS = 5pF, CDL = 10pF, and VCC = +3.4v. Prior to the access transistor closing, the digit line is
pre-charged to VCC /2.

Figure 1.45: DRAM charge sharing exercise.

25. For the DRAM storage cell shown in Fig. 1.45, solve for the final voltage on the digit line after
the access transistor (M1) closes if initially VS = GND (i.e., the cell is storing a 0). In this system,
CS = 5pF, CDL = 10pF, and VCC = +3.4v. Prior to the access transistor closing, the digit line is
pre-charged to VCC /2.

26. Design a Verilog model for the 16x8, asynchronous, read-only memory system shown in Fig. 1.46.
The system should contain the information provided in the memory map. Create a test bench to
simulate your model by reading from each of the 16 unique addresses and observing data_out
to verify it contains the information in the memory map.

Figure 1.46: 16x8 asynchronous ROM block diagram.

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27. Design a Verilog model for the 16x8, synchronous, read-only memory system shown in Fig. 1.47.
The system should contain the information provided in the memory map. Create a test bench to
simulate your model by reading from each of the 16 unique addresses and observing data_out
to verify it contains the information in the memory map.

Figure 1.47: 16x8 synchronous ROM block diagram.

28. Design a Verilog model for the 16x8, asynchronous, read/write memory system shown in Fig. 1.48.
Create a test bench to simulate your model. Your test bench should first read from all of the address
locations to verify they are uninitialized. Next, your test bench should write unique information to
each of the address locations. Finally, your test bench should read from each address location to
verify that the information that was written was stored and can be successfully retrieved.

Figure 1.48: 16x8 asynchronous R/W memory block diagram.

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29. Design a Verilog model for the 16x8, synchronous, read/write memory system shown in Fig. 1.49.
Create a test bench to simulate your model. Your test bench should first read from all of the address
locations to verify they are uninitialized. Next, your test bench should write unique information to
each of the address locations. Finally, your test bench should read from each address location to
verify that the information that was written was stored and can be successfully retrieved

Figure 1.49: 16x8 synchronous R/W memory block diagram.

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