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CE 2704 - Digital Logic Design
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Dr. Ehsan Ali
Assumption University of Thailand
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ehsanali@[Link]
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Semester 2/2024
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Contents
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1 Module 6 - Assignments 28 to 39 Answers 2
1.1 Copyright Notice . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
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1.2 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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Chapter 1
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Module 6 - Assignments 28 to 39 Answers
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1.1 Copyright Notice
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This PDf file is generated by Dr. Ehsan Ali and contains the answers to Module 6 assignments 28
to 39 of CE2704 Digital Logic Design - academic semester 2/2024. The material in this PDF file is
copyrighted. and cannot be shared whatsoever to any third party or online websites, forums, etc.
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In case of violation, the issue will be brought to legal institutions and the leak will be traced until
the student who has released this document is identified. Serious disciplinary actions will be taken if
students share this document to any third-party or person, either to junior/senior students or classmates
of other faculties or departments, or the public.
The disciplinary actions include nulling all assignment scores and bringing the case to Assumption
University University Academic Affairs office to dispel the student from the university based on corrup-
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tion, untrustworthiness, and lack of personal integrity. An individual who lies or do not obey the rules of
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a society shall not be granted an academic degree as he/she will be a danger to society in the future.
I (Dr. Ehsan Ali) hereby promise that I will personally follow up the case until the student who has
violated the copyright is dispelled from the Assumption University of Thailand.
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1.2 Assignments
28. Design a /20 cent vending machine controller by hand. Your controller will take in nickels and
dimes and dispense a product anytime the customer has entered at least 20 cents. Your FSM has
two inputs, Nin and Din. Nin is asserted whenever the customer enters a nickel while Din
is asserted anytime the customer enters a dime. Your FSM has two outputs, Dispense and
Change. Dispense is asserted anytime the customer has entered at least 20 cents and Change
is asserted anytime the customer has entered more than 20 cents and needs a nickel in change.
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(a) Provide the state diagram for this FSM.
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(b) Encode your states using binary encoding. How many D-Flip-Flops does it take to implement
the state memory for this FSM?
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(c) Provide the state transition table for this FSM.
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(d) Synthesize the combinational logic expressions for the next state logic.
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(e) Synthesize the combinational logic expression for the output logic.
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(f) Is this machine a Mealy or Moore machine?
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(g) Draw the logic diagram for this FSM.
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29. Design a finite state machine by hand that controls a traffic light at the intersection of a busy
highway and a seldom used side road. You will be designing the control signals for just the red,
yellow, and green lights facing the highway. Under normal conditions, the highway has a green
light. The side road has a car detector that indicates when a car pulls up by asserting a signal
called CAR. When CAR is asserted, you will change the highway traffic light from green to yellow.
Once yellow, you will always go to red. Once in the red position, a built in timer will begin a
countdown and provide your controller a signal called TIMEOUT when 15 seconds has passed.
Once TIMEOUT is asserted, you will change the highway traffic light back to green. Your system
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will have three outputs GRN, YLW, and RED that control when the highway facing traffic lights are
on (1=ON, 0=OFF).
(a) Provide the state diagram for this FSM.
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(b) Encode your states using binary encoding. How many D-Flip-Flops does it take to implement
the state memory for this FSM?
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(c) Provide the state transition table for this FSM.
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(d) Synthesize the combinational logic expressions for the next state logic.
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(e) Synthesize the combinational logic expression for the output logic.
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(f) Is this machine a Mealy or Moore machine?
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(g) Draw the logic diagram for this FSM.
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30. Design a 3-bit binary up counter by hand. This state machine will need eight states and require
three bits for the state variable codes. Name the current state variables Q2_cur, Q1_cur, and
Q0_cur and the next state variables Q2_nxt, Q1_nxt, and Q0_nxt. The output of your counter
will be a 3-bit vector called Count.
(a) What is the next state logic expression for Q2_nxt?
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(b) What is the next state logic expression for Q1_nxt?
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(c) What is the next state logic expression for Q0_nxt?
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(d) What is the output logic expression for Count(2)?
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(e) What is the output logic expression for Count(1)?
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(f) What is the output logic expression for Count(0)?
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(g) Draw the logic diagram for this Counter.
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(h) Instantiate the D-Flip-Flop model provided to implement your state memory. Use whatever
continuous signal assignment modeling approach you wish to model the next state and output
logic. Use the module port definition provided. Include your simulation waveform.
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31. Design a 3-bit binary up/down counter by hand. This state machine will need eight states and
require three bits for the state variable codes. Name the current state variables Q2_cur, Q1_cur,
and Q0_cur and the next state variables Q2_nxt, Q1_nxt, and Q0_nxt. The output of your
counter will be a 3-bit vector called Count.
(a) What is the next state logic expression for Q2_nxt?
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(b) What is the next state logic expression for Q1_nxt?
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(c) What is the next state logic expression for Q0_nxt?
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(d) What is the output logic expression for Count(2)?
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(e) What is the output logic expression for Count(1)?
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(f) What is the output logic expression for Count(0)?
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(g) Draw the logic diagram for this Counter.
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(h) Instantiate the D-Flip-Flop model provided to implement your state memory. Use whatever
continuous signal assignment modeling approach you wish to model the next state and output
logic. Use the module port definition provided. Include your simulation waveform.
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32. Are resets typically synchronous or asynchronous?
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Answer: Asynchronous. It is typically desired to have a reset be the most important signal in a
system . It should override everything immediately and put every storage device into a known
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state. If a reset were synchronous, it wouldn’t take effect immediately when asserted. Instead, a
synchronous reset would need to wait until the next triggering edge of the clock. This would be
problematic in the case that there was a system failure that resulted in the clock stopping. In this
case, a synchronous reset would never be able to bring the system out of the failure mode .
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33. Why is it necessary to have a reset/preset condition in a finite state machine?
Answer: To be able to put the FSM into a known state when the system starts.
34. How does the reset/preset condition correspond to the behavior described in the state diagram?
Answer: The reset/preset condition puts the FSM into the state designated as the "start state" of
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35. When is it necessary to also use the preset line(s) of a D-flip-flop instead of just the reset line(s)
when implementing the state memory of a finite state machine?
Answer: When the "reset state" (or start state) of the FSM is encoded such that it contains both 1’s
and 0’s instead of all 0’s.
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36. If a finite state machine has eight unique states that are encoded in binary and all D-flip- flops used
for the state memory use their reset lines , what is the state code that the machine will go to upon
reset?
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Answer: It will go to the state code "000". This is because in this question all of the D-flip-flops
are using their "reset" lines. A reset line causes the Q outputs of the D-flip-flop to go to a zero.
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Also, this question states that there are eight states encoded in binary. This encoding scheme will
take three bits to encode the eight states (000, 001, ..., 110, 111).
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37. For the finite state machine logic diagram shown in Fig. 1.59, give the following expressions:
(a) Give the next state logic expression for Q_nxt.
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(b) Give the output logic expression for Tout.
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(c) Give the state transition table.
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(d) Give the state diagram.
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(e) Find the maximum clock frequency.
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38. For the finite state machine logic diagram shown in Fig. 1.60, give the following expressions:
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(a) Give the next state logic expression for Q_nxt.
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(b) Give the output logic expression for F.
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(c) Give the state transition table.
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(d) Give the state diagram.
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(e) Find the maximum clock frequency.
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39. For the finite state machine logic diagram shown in Fig. 1.61, give the following expressions:
(a) Give the next state logic expression for Q1_nxt and Q0_nxt.
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(b) Give the output logic expression for Return.
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(c) Give the state transition table.
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(d) Give the state diagram.
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(e) Find the maximum clock frequency.
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