CE 2704 - Digital Logic Design

Dr. Ehsan Ali

Assumption University of Thailand
[email protected]

Semester 2/2024
Contents

1 Module 2 - Digital Circuitry and Interfacing - Basic Gates - Logic Families - Driving Loads 3
1.1 Digital Circuitry and Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.1 Learning Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Basic Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Describing the Operation of a Logic Circuit . . . . . . . . . . . . . . . . . . . . 4
1.2.1.1 The Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1.2 The Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2.1.3 The Logic Function . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.1.4 The Logic Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2 The Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 The Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.4 The AND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.5 The NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.6 The OR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.7 The NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.8 The XOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2.9 The XNOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.3 Digital Circuit Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1 Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.2 Output DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.3 Input DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.4 Noise Margins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.5 Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.6 Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.3.7 Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.4 Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.1 Complementary Metal-Oxide Semiconductors (CMOS) . . . . . . . . . . . . . . 24
1.4.1.1 CMOS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.4.1.2 CMOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.4.1.3 CMOS NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
1.4.1.4 CMOS NOR Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.4.2 Transistor-Transistor Logic (TTL) . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.4.2.1 TTL Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
1.4.3 The 7400 Series Logic Families . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.4.3.1 Part-Numbering Scheme . . . . . . . . . . . . . . . . . . . . . . . . 35
1.4.3.2 DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . 37
1.4.3.3 Pin-Out Information for the DIP Packages . . . . . . . . . . . . . . . 37
1.5 Driving Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

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 1.5.1 Driving Other Gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.5.2 Driving Resistive Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.5.2.1 Primer on Ohm’s Law . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.5.3 Driving LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.6 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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Chapter 1

Module 2 - Digital Circuitry and Interfacing -

Basic Gates - Logic Families - Driving Loads

1.1 Digital Circuitry and Interfacing

Now we turn our attention to the physical circuitry and electrical quantities that are used to represent
and operate on the binary codes 1 and 0. This week we begin by looking at how logic circuits are
described and introduce the basic set of gates used for all digital logic operations. We then look at the
underlying circuitry that implements the basic gates including digital signaling and how voltages are
used to represent 1’s and 0’s. We then look at interfacing between two digital circuits and how to ensure
that when one circuit sends a binary code, the receiving circuit is able to determine which code was sent.
Logic families are then introduced, and the details of how basic gates are implemented at the switch level
are presented. Finally, interfacing considerations are covered for the most common types of digital loads
(i.e., other gates, resistors, and LEDs). The goal is to provide an understanding of the basic electrical
operation of digital circuits.

1.1.1 Learning Outcomes

• Describe the functional operation of a basic logic gate using truth tables, logic expressions, and
logic waveforms.

• Analyze the DC and AC behavior of a digital circuit to verify it is operating within specification.

• Describe the meaning of a logic family and the operation of the most common technologies used
today.

• Determine the operating conditions of a logic circuit when driving various types of loads.

1.2 Basic Gates

The term gate is used to describe a digital circuit that implements the most basic functions possible
within the binary system. When discussing the operation of a logic gate, we ignore the details of how the
1’s and 0’s are represented with voltages and manipulated using transistors. We instead treat the inputs
and output as simply ideal 1’s and 0’s. This allows us to design more complex logic circuits without
going into the details of the underlying physical hardware.

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1.2.1 Describing the Operation of a Logic Circuit
1.2.1.1 The Logic Symbol
A logic symbol is a graphical representation of the circuit that can be used in a schematic to show
how circuits in a system interface to one another. For the set of basic logic gates, there are uniquely
shaped symbols that graphically indicate their functionality. For more complex logic circuits that are
implemented with multiple basic gates, a simple rectangular symbol is used. Inputs of the logic circuit
are typically shown on the left of the symbol and outputs are on the right. Fig. 1.1 shows two example
logic symbols.

Figure 1.1: Example logic symbols.

1.2.1.2 The Truth Table

We formally define the functionality of a logic circuit using a truth table. In a truth table, each and
every possible input combination is listed, and the corresponding output of the logic circuit is given. If
a logic circuit has n inputs, then it will have 2n possible input codes. The binary codes are listed in
ascending order within the truth table mimicking a binary count starting at 0. By always listing the input
codes in this way, we can assign a row number to each input that is the decimal equivalent of the binary
input code. Row numbers can be used to simplify the notation for describing the functionality of larger
circuits. Fig. 1.2 shows the formation of an example 3-input truth table.

Figure 1.2: Example logic symbols.

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1.2.1.3 The Logic Function
A logic expression, (also called a logic function), is an equation that provides the functionality of each
output in the circuit as a function of the inputs. The logic operations for the basic gates are given a
symbolic set of operators (e.g., +, ., ⊕), the details of which will be given in the next sections. The logic
function describes the operations that are necessary to produce the outputs listed in the truth table. A
logic function is used to describe a single output that can take on only the values 1 and 0. If a circuit
contains multiple outputs, then a logic function is needed for each output. The input variables can be
included in the expression description just as in an analog function. For example, "F(A, B, C) = ..."
would state that "F is a function of the inputs A, B, and C". This can also be written as "FA,B,C =..."
The input variables can also be excluded for brevity as in "F = ...". Fig. 1.3 shows the formation of an
example 3-input logic expression.

Figure 1.3: Logic function formation.

1.2.1.4 The Logic Waveform

A logic waveform is a graphical depiction of the relationship of the output to the inputs with respect to
time. This is often a useful description of behavior since it mimics the format that is typically observed
when measuring a real digital circuit using test equipment such as an oscilloscope. In the waveform,
each signal can only take on a value of 1 or 0. It is useful to write the logic values of the signal at each
transition in the waveform for readability. Fig. 1.4 shows an example logic waveform.

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 Figure 1.4: Example logic waveform.

1.2.2 The Buffer

The first basic gate is the buffer. The output of a buffer is simply the input. The logic symbol, truth
table, logic function, and logic waveform for the buffer are given in Fig. 1.5.

Figure 1.5: Buffer symbol, truth table, logic function, and logic waveform.

1.2.3 The Inverter

The next basic gate is the inverter. The output of an inverter is the complement of the input. Inversion
is also often called the not operation. In spoken word, we might say "A is equal to not B;" thus this gate
is also often called a not gate. The symbol for the inverter is the same as the buffer with the exception
that an inversion bubble (i.e., a circle) is placed on the output. The inversion bubble is a common way to
show inversions in schematics and will be used by many of the basic gates. In the logic function, there
are two common ways to show this operation. The first way is by placing a prime (’) after the input
variable (e.g., Out = In0 ). This notation has the advantage that it is supported in all text editors but has
the drawback that it can sometimes be difficult to see. The second way to indicate inversion in a logic
function is by placing an inversion bar over the input variable (e.g., Out = In). The advantage of this
notation is that it is easy to see but has the drawback that it is not supported by many text editors. In
this course we use both conventions to provide exposure to each. The logic symbol, truth table, logic
function, and logic waveform for the inverter are given in Fig. 1.6.

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 Figure 1.6: Inverter symbol, truth table, logic function, and logic waveform.

1.2.4 The AND Gate

The next basic gate is the AND gate. The output of an AND gate will only be true (i.e., a logic 1) if all of
the inputs are true. This operation is also called a logical product because if the inputs were multiplied
together, the only time the output would be a 1 is if each and every input was a 1. As a result, the logic
operator is the dot (.). Another notation that is often seen is the ampersand (&). The logic symbol, truth
table, logic function, and logic waveform for a 2-input AND gate are given in Fig. 1.7.

Figure 1.7: 2-input AND gate symbol, truth table, logic function, and logic waveform.

Ideal AND gates (In reality we cannot build or it is not efficient to build very large input AND gates)
can have any number of inputs. The operation of an n-bit, AND gates still follows the rule that the output
will only be true when all of the inputs are true. Later we will discuss the limitations on expanding the
number of inputs of these basic gates indefinitely.

1.2.5 The NAND Gate

The NAND gate is identical to the AND gate with the exception that the output is inverted. The "N" in
NAND stands for "NOT", which represents the inversion. The symbol for a NAND gate is an AND gate
with an inversion bubble on the output. The logic expression for a NAND gate is the same as an AND
gate but with an inversion bar over the entire operation. The logic symbol, truth table, logic function,
and logic waveform for a 2-input NAND gate are given in Fig. 1.8. Ideal NAND gates can have any
number of inputs with the operation of an n-bit, NAND gate following the rule that the output is always
the inversion of an n-bit, AND operation.

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 Figure 1.8: 2-input NAND gate symbol, truth table, logic function, and logic waveform.

1.2.6 The OR Gate

The next basic gate is the OR gate. The output of an OR gate will be true when any of the inputs are
true. This operation is also called a logical sum because of its similarity to logical disjunction in which
the output is true if at least one of the inputs is true. As a result, the logic operator is the plus sign (+).
The logic symbol, truth table, logic function, and logic waveform for a 2-input OR gate are given in Fig.
1.9. Ideal OR gates can have any number of inputs. The operation of an n-bit, OR gates still follows the
rule that the output will be true if any of the inputs are true.

Figure 1.9: 2-input OR gate symbol, truth table, logic function, and logic waveform.

1.2.7 The NOR Gate

The NOR gate is identical to the OR gate with the exception that the output is inverted. The symbol for
a NOR gate is an OR gate with an inversion bubble on the output. The logic expression for a NOR gate
is the same as an OR gate but with an inversion bar over the entire operation. The logic symbol, truth
table, logic function, and logic waveform for a 2-input NOR gate are given in Fig. 1.10. Ideal NOR
gates can have any number of inputs with the operation of an n-bit, NOR gate following the rule that the
output is always the inversion of an n-bit, OR operation.

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 Figure 1.10: 2-input NOR gate symbol, truth table, logic function, and logic waveform.

1.2.8 The XOR Gate

The next basic gate is the exclusive-OR gate or XOR gate for short. This gate is also called a difference
gate because for the 2-input configuration, its output will be true when the input codes are different from
one another. The logic operator is a circle around a plus sign (⊕). The logic symbol, truth table, logic
function, and logic waveform for a 2-input XOR gate are given in Fig. 1.11.

Figure 1.11: 2-input XOR gate symbol, truth table, logic function, and logic waveform.

Using the formal definition of an XOR gate (i.e., the output is true if any of the input codes are
different from one another), an XOR gate with more than two inputs can be built. The truth table for
a 3-bit, XOR gate using this definition is shown in Fig. 1.12. In modern electronics, this type of gate
has found little use since it is much simpler to build this functionality using a combination of AND and
OR gates. As such, XOR gates with greater than two inputs do not implement the difference function.
Instead, a more useful functionality has been adopted in which the output of the n-bit, XOR gate is the
result of a cascade of 2-input XOR gates. This results in an ultimate output that is true when there is
an ODD number of 1’s on the inputs. This functionality is much more useful in modern electronics for
error correction codes and arithmetic. As such, this is the functionality that is seen in modern n-bit, XOR
gates. This functionality is also shown in Fig. 1.12.

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 Figure 1.12: 3-input XOR gate implementation.

1.2.9 The XNOR Gate

The exclusive-NOR gate is identical to the XOR gate with the exception that the output is inverted. This
gate is also called an equivalence gate because for the 2-input configuration, its output will be true when
the input codes are equivalent to one another. The symbol for an XNOR gate is an XOR gate with an
inversion bubble on the output. The logic expression for an XNOR gate is the same as an XOR gate but
with an inversion bar over the entire operation. The logic symbol, truth table, logic function, and logic
waveform for a 2-input XNOR gate are given in Fig. 1.13. XNOR gates can have any number of inputs
with the operation of an n-bit, XNOR gate following the rule that the output is always the inversion of
an n-bit, XOR operation (i.e., the output is true if there is an ODD number of 1’s on the inputs).

Figure 1.13: 2-input XNOR gate symbol, truth table, logic function, and logic waveform.

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 In-class Question 1: Given the following logic diagram, which is the correct logic expression for
logic function F? [5min]

1. F = (A.B)0 ⊕ C

2. F = (A0 .B 0 ) ⊕ C

3. F = (A0 .B 0 ⊕ C)

4. F = A.B 0 ⊕ C

1.3 Digital Circuit Operation

Now we turn our attention to the physical hardware that is used to build the basic gates just described and
how electrical quantities are used to represent and communicate the binary values 1 and 0. We begin by
looking at digital signaling. Digital signaling refers to how binary codes are generated and transmitted
successfully between two digital circuits using electrical quantities (e.g.,voltage and current). Consider
the digital system shown in Fig. 1.14. In this system, the sending circuit generates a binary code. The
sending circuit is called either the transmitter (Tx) or driver. The transmitter represents the binary
code using an electrical quantity such as voltage. The receiving circuit (Rx) observes this voltage and
is able to determine the value of the binary code. In this way, 1’s and 0’s can be communicated between
the two digital circuits. The transmitter and receiver are both designed to use the same digital signaling
scheme so that they are able to communicate with each other. It should be noted that all digital circuits
contain both inputs (Rx) and outputs (Tx) but are not shown in this figure for simplicity.

Figure 1.14: Generic digital transmitter/receiver circuit

1.3.1 Logic Levels

A logic level is the term to describe all possible states that a signal can have. We will focus explicitly
on circuits that represent binary values, so these will only have two finite states (1 and 0). To begin, we
define a simplistic model of how to represent the binary codes using an electrical quantity. This model

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uses a voltage threshold (Vth ) to represent the switching point between the binary codes. If the voltage
of the signal (Vsig ) is above this threshold, it is considered a logic HIGH. If the voltage is below this
threshold, it is considered a logic LOW. A graphical depiction of this is shown in Fig. 1.15. The terms
HIGH and LOW are used to describe which logic level corresponds to the higher or lower voltage.

Figure 1.15: Definition of logic HIGH and LOW.

It is straightforward to have the HIGH level correspond to the binary code 1 and the LOW level
correspond to the binary code 0; however, it is equally valid to have the HIGH level correspond to the bi-
nary code 0 and the LOW level correspond to the binary code 1. As such, we need to define how the logic
levels HIGH and LOW map to the binary codes 1 and 0. We define two types of digital assignments:
positive logic and negative logic. In positive logic, the logic HIGH level represents a binary 1, and the
logic LOW level represents a binary 0. In negative logic, the logic HIGH level represents a binary 0,
and the logic LOW level represents a binary 1. Fig. 1.16 shows the definition of positive and negative
logic. There are certain types of digital circuits that benefit from using negative logic; however, we will
focus specifically on systems that use positive logic since it is more intuitive when learning digital design
for the first time. The transformation between positive and negative logic is straightforward and will be
covered later.

Figure 1.16: Definition of positive and negative logic.

1.3.2 Output DC Specifications

Transmitting circuits provide specifications on the range of output voltages (VO ) that they are guaranteed
to provide when outputting a logic 1 or 0. These are called the DC output specifications. There are four
DC voltage specifications that specify this range:

1. VOH-max

2. VOH-min

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 3. VOL-max

4. VOL-min

The VOH-max and VOH-min specifications provide the range of voltages the transmitter is guaranteed to
provide when outputting a logic HIGH (or logic 1 when using positive logic). The VOL-max and VOL-min
specifications provide the range of voltages the transmitter is guaranteed to provide when outputting a
logic LOW (or logic 0 when using positive logic). In the subscripts for these specifications, the "O"
signifies "output" and the "L" or "H" signifies "LOW" or "HIGH", respectively.
The maximum amount of current that can flow through the transmitter’s output (IO ) is also specified.
The specification IOH-max is the maximum amount of current that can flow through the transmitter’s output
when sending a logic HIGH. The specification IOL-max is the maximum amount of current that can flow
through the transmitter’s output when sending a logic LOW. When the maximum output currents are
violated, it usually damages the part. Manufacturers will also provide a recommended amount of current
for IO that will guarantee the specified operating parameters throughout the life of the part. Fig. 1.17
shows a graphical depiction of these DC specifications. When the transmitter output is providing current
to the receiving circuit (aka, the load), it is said to be sourcing current. When the transmitter output is
drawing current from the receiving circuit, it is said to be sinking current. In most cases, the transmitter
sources current when driving a logic HIGH and sinks current when driving a logic LOW. Fig. 1.17
shows a graphical depiction of these specifications.

Figure 1.17: DC specifications of a digital circuit.

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1.3.3 Input DC Specifications
Receiving circuits provide specifications on the range of input voltages (VI ) that they will interpret as
either a logic HIGH or LOW. These are called the DC input specifications. There are four DC voltage
specifications that specify this range:

1. VIH-max

2. VIH-min

3. VIL-max

4. VIL-min

These specifications provide the range of voltages that the receiver will interpret as a logic HIGH (or
logic 1 when using positive logic). The VIL-max and VIL-min specifications provide the range of voltages
that the receiver will interpret as a logic LOW (or logic 0 when using positive logic). In the subscripts
for these specifications, the "I" signifies "input". The maximum amount of current that the receiver will
draw, or take in, when connected is also specified II ). The specification IIH-max is the maximum amount
of current that the receiver will draw when it is being driven with a logic HIGH. The specification IIL-max
is the maximum amount of current that the receiver will draw when it is being driven with a logic LOW.
Again, Fig. 1.17 shows a graphical depiction of these DC specifications.

1.3.4 Noise Margins

For digital circuits that are designed to operate with each other, the VOH-max and VIH-max specifications
have equal voltages. Similarly, the VOL-min and VIL-min specifications have equal voltages. The VOH-max
and VOL-min output specifications represent the best-case scenario for digital signaling as the transmitter
is sending the largest (or smallest) signal possible. If there is no loss in the interconnect between the
transmitter and receiver, the full voltage levels will arrive at the receiver and be interpreted as the correct
logic states (HIGH or LOW).
The worst-case scenario for digital signaling is when the transmitter outputs its levels at VOH-min and
VOL-max . These levels represent the furthest away from an ideal voltage level that the transmitter can send
to the receiver and are susceptible to loss and noise that may occur in the interconnect system. In order
to compensate for potential loss or noise, digital circuits have a predefined amount of margin built into
their worst-case specifications. Let’s take the worst-case example of a transmitter sending a logic HIGH
at the level VOH-min . If the receiver was designed to have VIH-min (i.e., the lowest voltage that would still
be interpreted as a logic 1) equal to VOH-min and then if even the smallest amount of the output signal
was attenuated as it traveled through the interconnect, it would arrive at the receiver below VIH-min and
would not be interpreted as a logic 1. Since there will always be some amount of loss in any interconnect
system, the specifications for VIH-min are always less than VOH-min . The difference between these two
quantities is called the noise margin. More specifically, it is called the noise margin HIGH (or N MH )
to signify how much margin is built into the Tx/Rx circuit when communicating a logic 1. Similarly, the
VIL-max specification is always higher than the VOL-max specification to account for any voltage added to
the signal in the interconnect. The difference between these two quantities is called the noise margin
LOW (or N ML ) to signify how much margin is built into the Tx/Rx circuit when communicating a
logic 0. Noise margins are always specified as positive quantities; thus the order of the subtrahend and
minuend in these differences.

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 N MH = VOH−min − VIH−min (1.1)
N ML = VIL−max − VOL−max (1.2)

Fig. 1.17 includes the graphical depiction of the noise margins. Notice in this figure that there is a
region of voltages that the receiver will not interpret as either a HIGH or LOW. This region lies between
the VIH-min and VIL-max specifications. This is the uncertainty region and should be avoided. Signals in
this region will cause the receiver’s output to go to an unknown voltage. Digital transmitters are designed
to transition between the LOW and HIGH states quickly enough so that the receiver does not have time
to react to the input being in the uncertainty region.

1.3.5 Power Supplies

All digital circuits require a power supply voltage and a ground. There are some types of digital circuits
that may require multiple power supplies. For simplicity, we will focus on digital circuits that only
require a single power supply voltage and ground. The power supply voltage is commonly given the
abbreviations of either VCC or VDD . The "CC" and "DD" have to do with how the terminals of the tran-
sistors inside of the digital circuit are connected (i.e., "collector to collector" or "drain to drain") (We will
discuss these in details later). Digital circuits will specify the required power supply voltage. Ground is
considered an ideal 0 v. Digital circuits will also specify the maximum amount of DC current that can
flow through the VCC (ICC ) and GND (IGND ) pins before damaging the part.
There are two components of power supply current. The first is the current that is required for the
functional operation of the device. This is called the quiescent current (Iq ) (Dictionary meaning of
’quiescent’: in a state or period of inactivity or dormancy, similar to the pronunciation of the word
’quite’). The second component of the power supply current is the output currents (IO ). Any current
that flows out of a digital circuit must also flow into it. When a transmitting circuit sources current to a
load on its output pin, it must bring in that same amount of current on another pin. This is accomplished
using the power supply pin (VCC ). Conversely, when a transmitting circuit sinks current from a load on
its output pin, an equal amount of current must exit the circuit on a different pin. This is accomplished
using the GND pin. This means that the amount of current flowing through the VCC and GND pins
will vary depending on the logic states that are being driven on the outputs. Since a digital circuit may
contain numerous output pins, the maximum amount of current flowing through the VCC and GND pins
can scale quickly and care must be taken not to damage the device.
The quiescent current is often specified using the term ICC . This should not be confused with the
specification for the maximum amount of current that can flow through the VCC pin, which is often
called ICC-max . It is easy to tell the difference because ICC (or Iq ) is much smaller than ICC-max for CMOS
parts. ICC (or Iq ) is specified in the uA to nA range, while the maximum current that can flow through
the VCC pin is specified in the mA range. The following example shows the process of calculating the
ICC and IGND currents when sourcing multiple loads.

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 Example 1: Calculating ICC and IGND when sourcing multiple loads:
Given: The driver is specified to have a quiescent current of 1 mA and is driving a logic HIGH
on two of its output pins. Each of the two loads on the output pins is being sourced with 4 mA of
current from the driver.

Find ICC and IGND .

Solution: The current into the device must equal the current out of the device. The quiescent current
of 1 mA is used for functional operation of the transistors within the transmitter and will flow into the
device through VCC pin and out of the device on the GND pin. The output currents that are being sourced
by the driver exit the circuit on the two output pins Vo(1) and Vo(2) . An equal amount of current must also
flow into the device Io(1) + Io(2) = 8mA, which enters the device on the VCC pin. This means the total
amount of current flowing into the circuit on the VCC pin is:

ICC = Iq + Io(1) + Io(2) = 1mA + 4mA + 4mA = 9mA (1.3)

The total amount of current flowing out of the circuit on the GND pin is simply the quiescent current
Iq .

IGN D = Iq = 1mA (1.4)

16
 Check: Does the total amount of current entering the circuit equal the total amount of current exiting
the circuit?
Answer: Yes, there is 9 mA entering the circuit through the VCC pin. There is also 9 mA exiting the
circuit using the Vo(1) , Vo(2) , and GND pins.

Example 2: Calculating ICC and IGND when both sourcing and sinking loads:
Given: The driver is specified to have a quiescent current of 0.5 mA and is driving a logic HIGH
on one of its output pins and a logic LOW on two of its output pins. The driver is sourcing 1 mA
when driving a HIGH and 2 mA when driving a LOW.

Find ICC and IGND .

Solution: The current into the device must be equal to the current out of the device. The quiescent
current of 0.5 mA enters the circuit on the VCC pin and exits on the GND pin. The output current for
Vo(1) enters the circuit on the VCC pin and exits the circuit on the Vo(1) pin. The output current for Vo(2)
and Vo(3) enters the circuit on the Vo(2) and Vo(3) pins and exits the circuit on the GND pin. This means
the total amount of current flowing into circuit on the VCC pin is:

ICC = Iq + IO(1) = 0.5 mA + 1 mA = 1.5 mA (1.5)

17
 The total amount of current flowing out of circuit on the GND pin is the quiescent current Iq plus the
current being sunk from the pins Vo(2) and Vo(3) :

IGN D = Iq + IO(2) + IO(3) = 0.5 mA + 2 mA + 2 mA = 4.5 mA (1.6)

1.3.6 Switching Characteristics

Switching characteristics refer to the transient (The word ’transient’ means lasting only for a short time)
behavior of the logic circuits. The first group of switching specifications characterize the propagation
delay of the gate. The propagation delay is the time it takes for the output to respond to a change on the
input. The propagation delay is formally defined as the time it takes from the point at which the input
has transitioned to 50% of its final value to the point at which the output has transitioned to 50% of its
final value. The initial and final voltages for the input are defined to be GND and VCC , while the output
initial and final voltages are defined to be VOL and VOH .
Specifications are given for the propagation delay when transitioning from a LOW to HIGH (tPLH )
and from a HIGH to LOW (tPHL ). When these specifications are equal, the values are often given as a
single specification of tpd . These specifications are shown graphically in Fig. 1.18.
The second group of switching specifications characterize how quickly the output switches between
states. The transition time is defined as the time it takes for the output to transition from 10% to 90%
of the output voltage range. The rise time (tr ) is the time it takes for this transition when going from
a LOW to HIGH, and the fall time (tf ) is the time it takes for this transition when going from a HIGH
to LOW. When these specifications are equal, the values are often given as a single specification of tt .
These specifications are shown graphically in Fig. 1.18.

18
 Figure 1.18: Switching characteristics of a digital circuit.

1.3.7 Data Sheets

The specifications for a particular part are given in its data sheet. The data sheet contains all of the
operating characteristics for a part, in addition to functional information such as package geometries
and pin assignments. The data sheet is usually the first place a designer will look when selecting a
part. Fig. 1.19, 1.20, and 1.21 show excerpts from an example data sheet highlighting some of the
specifications just covered. You can download the latest PDF version of this data sheet from here:
https://www.ti.com/lit/ds/symlink/sn74hc04.pdf

19
Figure 1.19: Example data sheet excerpt (1).

20
Figure 1.20: Example data sheet excerpt (2).

21
 Figure 1.21: Example data sheet excerpt (3).

In-class Question 2: Given the following DC specifications for a driver/receiver pair, in what situation
may a logic signal transmitted not be successfully received?

VOH-max = +3.4 v VIH-max = +3.4 v

VOH-min = +2.5 v VIH-min = +2.5 v
VOL-max = +1.5 v VIL-max = +2.0 v
VOL-min = 0 v VIL-min = 0 v

1. Driving a HIGH with Vo = +3.4 v

22
 2. Driving a HIGH with Vo = +2.5 v

3. Driving a LOW with Vo = +1.5 v

4. Driving a LOW with Vo = 0 v

In-class Question 3: For the following driver configuration, which of the following is a valid con-
straint that could be put in place to prevent a violation of the maximum power supply currents (ICC-max
and IGND-max )?

1. Modify the driver transistors so that they can’t provide more than 5 mA on any output.

2. Apply a cooling system (e.g., a heat sink or fan) to the driver chip.

3. Design the logic so that no more than half of the outputs are HIGH at any given time.

4. Drive multiple receivers with the same output pin.

In-class Question 4: Why is it desirable to have the output of a digital circuit transition quickly
between the logic LOW and logic HIGH levels?

1. So that the outputs are not able to respond as the input transitions through the uncertainty region.
This avoids unwanted transitions.

2. So that all signals look like square waves.

3. To reduce power by minimizing the time spent switching.

4. Because the system can only have two states, a LOW and a HIGH.

23
1.4 Logic Families
It is apparent from the prior discussion of operating conditions that digital circuits need to have compara-
ble input and output specifications in order to successfully communicate with each other. If a transmitter
outputs a logic HIGH as +3.4 v and the receiver needs a logic HIGH to be above +4 v to be successfully
interpreted as a logic HIGH, then these two circuits will not be able to communicate. In order to address
this interoperability issue, digital circuits are grouped into logic families. A logic family is a group
of parts that all adhere to a common set of specifications so that they work together. The logic family
is given a specific name, and once the specifications are agreed upon, different manufacturers produce
parts that work within the particular family. Within a logic family, parts will all have the same power
supply requirements and DC input/output specifications such that if connected directly, they will be able
to successfully communicate with each other. The phrase "connected directly" is emphasized because it
is very possible to insert an interconnect circuit between two circuits within the same logic family and
alter the output voltage enough so that the receiver will not be able to interpret the correct logic level.
Analyzing the effect of the interconnect circuit is part of the digital design process. There are many logic
families that exist (up to 100 different types!), and more emerge each year as improvements are made to
circuit fabrication processes that create smaller, faster, and lower power circuits.

1.4.1 Complementary Metal-Oxide Semiconductors (CMOS)

The first group of logic families we will discuss is called complementary metal-oxide semiconductors,
or CMOS. This is currently the most popular group of logic families for digital circuits implemented on
the same integrated circuit (IC). An integrated circuit is where the entire circuit is implemented on a
single piece of semiconductor material (or chip). The IC can contain transistors, resistors, capacitors,
inductors, wires, and insulators. Modern integrated circuits can contain billions of devices and meters
of interconnect. The opposite of implementing the circuit on an integrated circuit is to use discrete
components. Using discrete components refers to where every device (transistor, resistor, etc.) is its
own part and is wired together externally using either a printed circuit board (PCB) or jumper wires
as on a breadboard. The line between ICs and discrete parts has blurred in the past decades because
modern discrete parts are actually fabricated as an IC and regularly contain multiple devices (e.g., four
logic gates per chip). Regardless, the term discrete is still used to describe components that only contain
a few components where the term IC typically refers to a much larger system that is custom designed.
The term CMOS comes from the use of particular types of transistors to implement the digital cir-
cuits. The transistors are created using a metal-oxide semiconductor (MOS) structure. These transistors
are turned on or off based on an electric field, so they are given the name metal-oxide semiconductor
field-effect transistors, or MOSFETs. There are two transistors that can be built using this approach that
operate complementary to each other, thus the term complementary metal-oxide semiconductors. To un-
derstand the basic operation of CMOS logic, we begin by treating the MOSFETs as ideal switches. This
allows us to understand the basic functionality without diving into the detailed electronic analysis of the
transistors.

1.4.1.1 CMOS Operation

In CMOS, there is a single power supply (VCC or VDD ) and a single ground (GND). The ground signal is
sometimes called VSS . The maximum input and output DC specifications are equal to the power supply
(VCC = VOH-max = VIH-max ). The minimum input and output DC specification are equal to ground (GND
= 0 v = VOL-min = VIL-min ). In this way, using CMOS simplifies many of the specifications. If you state
that you are using "CMOS with a +3.4 v power supply", you are inherently stating that VCC = VOH-max
= VIH-max = +3.4 v and that VOL-min = VIL-min = 0 v. Many times, the name of the logic family will be

24
associated with the power supply voltage. For example, a logic family may go by the name "+3.3 v
CMOS" or "+2.5 v CMOS". These names give a first-level description of the logic family operation, but
more details about the operation must be looked up in the data sheet. There are two types of transistors
used in CMOS. The transistors will be closed or open based on an input logic level. The first transistor is
called an N-type MOSFET, or NMOS. This transistor will turn on, or close, when the voltage between
the gate and source (VGS ) is greater than its threshold voltage. The threshold voltage (VT ) is the amount
of voltage needed to create a conduction path between the drain and the source terminals. The threshold
voltage of an NMOS transistor is typically between 0.2 v and 1 v and much less than the VCC voltage
in the system. The second transistor is called a P-type MOSFET, or PMOS. This transistor turns on,
or closes, when the voltage between the gate and the source (VGS ) is less than VT , where the VT for
a PMOS is a negative value. This means that to turn on a PMOS transistor, the gate terminal needs
to be at a lower voltage than the source. The type of transistor (i.e., P-type or N-type) has to do with
the type of semiconductor material used to conduct current through the transistor. An NMOS transistor
uses negative charge to conduct current (i.e., negative-type), while a PMOS uses positive charge (i.e.,
positive-type). Fig. 1.22 shows the symbols for the PMOS and NMOS, the fabrication cross sections,
and their switch-level equivalents.

Figure 1.22: Complementary Metal Oxide Field Effect Semiconductor (CMOS) Transistor.

The basic operation of CMOS is that when driving a logic HIGH, the switches are used to connect
the output to the power supply (VCC ), and when driving a logic LOW, the switches are used to connect
the output to GND. In CMOS, VCC is considered an ideal logic HIGH and GND is considered an ideal
logic LOW. VCC is typically much larger than VT so using these levels can easily turn on and off the
transistors. The design of the circuit must never connect the output to VCC and GND at the same time or
else the device itself will be damaged due to the current flowing directly from VCC to GND through the
transistors.
Due to the device physics of the MOSFETS (We will discuss the details of this later on), PMOS tran-
sistors are used to form the network that will connect the output to VCC (aka, the pull-up network), and

25
NMOS transistors are used to form the network that will connect the output to GND (aka, the pull-down
network). Since PMOS transistors are closed when the input is a 0 (thus providing a logic HIGH on
the output) and NMOS transistors are closed when the input is a 1 (thus providing a logic LOW on the
output), CMOS implements negative logic gates. This means CMOS can implement inverters, NAND
and NOR gates, but not buffers, AND and OR gates, directly. In order to create a CMOS AND gate, the
circuit would implement a NAND gate followed by an inverter and similarly for an OR gate and buffer.

1.4.1.2 CMOS Inverter

Let’s now look at how we can use these transistors to create a CMOS inverter. Consider the transistor
arrangement shown in Fig. 1.23.

Figure 1.23: CMOS Inverter Schematic.

The inputs of both the PMOS and NMOS are connected together. The PMOS is used to connect the
output to VCC , and the NMOS is used to connect the output to GND. Since the inputs are connected
together and the switches operate in a complementary manner, this circuit ensures that both transistors
will never be on at the same time. When In = 0, the PMOS switch is closed and the NMOS switch is
open. This connects the output directly to VCC , thus providing a logic HIGH on the output. When In =
1, the PMOS switch is open and the NMOS switch is closed. This connects the output directly to GND,
thus providing a logic LOW. This configuration yields an inverter. This operation is shown graphically
in Fig. 1.24.

26
 Figure 1.24: CMOS Inverter Operation.

1.4.1.3 CMOS NAND Gate

Let’s now look at how we use a similar arrangement of transistors to implement a 2-input NAND gate.
Consider the transistor configuration shown in Fig. 1.25.

Figure 1.25: CMOS 2-Input NAND Gate Schematic.

The pull-down network consists of two NMOS transistors in series (M1 and M2), and the pull-up
network consists of two PMOS transistors in parallel (M3 and M4). Let’s go through each of the input

27
conditions and examine which transistors are on and which are off and how they impact the output. The
first input condition is when A = 0 and B = 0. This condition turns on both M3 and M4 creating two
parallel paths between the output and VCC . At the same time, it turns off both M1 and M2 preventing
a path between the output and GND. This input condition results in an output that is connected to VCC
resulting in a logic HIGH. The second input condition is when A = 0 and B = 1. This condition turns
on M3 in the pull-up network and M2 in the pull-down network. This condition also turns off M4 in the
pull-up network and M1 in the pull-down network. Since the pull-up network is a parallel combination
of PMOS transistors, there is still a path between the output and V CC through M3. Since the pull-down
network is a series combination of NMOS transistors, both M1 and M2 must be on in order to connect
the output to GND. This input condition results in an output that is connected to V CC resulting in a
logic HIGH. The third input condition is when A = 1 and B = 0. This condition again provides a path
between the output and VCC through M4 and prevents a path between the output and ground by having
M2 open. This input condition results in an output that is connected to V CC resulting in a logic HIGH.
The final input condition is when A = 1 and B = 1. In this input condition, both of the PMOS transistors
in the pull-up network (M3 and M4) are off preventing the output from being connected to VCC . At the
same time, this input turns on both M1 and M2 in the pull-down network connecting the output to GND.
This input condition results in an output that is connected to GND resulting in a logic LOW. Based on
the resulting output values corresponding to the four input codes, this circuit yields the logic operation
of a 2-input NAND gate. This operation is shown graphically in Fig. 1.26.

28
 Figure 1.26: CMOS 2-Input NAND Gate Operation.

Creating a CMOS NAND gate with more than two inputs is accomplished by adding additional
PMOS transistors to the pull-up network in parallel and additional NMOS transistors to the pull-down
network in series. Fig. 1.27 shows the schematic for a 3-input NAND gate. This procedure is followed
for creating NAND gates with larger numbers of inputs.

29
 Figure 1.27: CMOS 3-Input NAND Gate Schematic.

If the CMOS transistors were ideal switches, the approach of increasing the number of inputs could
be continued indefinitely. In reality, the transistors are not ideal switches, and there is a limit on how
many transistors can be added in series and continue to operate. The limitation has to do with ensuring
that each transistor has enough voltage to properly turn on or off. This is a factor in the series network
because the drain terminals of the NMOS transistors are not all connected to GND. If a voltage develops
across one of the lower transistors (e.g., M3), then it takes more voltage on the input to turn on the next
transistor up (e.g., M2). If too many transistors are added in series, then the uppermost transistor in the
series may not be able to be turned on or off by the input signals. The number of inputs that a logic gate
can have within a particular logic family is called its fan-in specification. When a logic circuit requires
a number of inputs that exceed the fan-in specification for a particular logic family, then additional logic
gates must be used. For example, if a circuit requires a 5-input NAND gate but the logic family has a
fan-in specification of 4, this means that the largest NAND gate available only has 4-inputs. The 5-input
NAND operation must be accomplished using additional circuit design techniques that use gates with 4
or less inputs. These design techniques will be covered in upcoming weeks.

1.4.1.4 CMOS NOR Gate

A CMOS NOR gate is created using a similar topology as a NAND gate with the exception that the pull-
up network consists of PMOS transistors in series and the pull-down network that consists of NMOS
transistors in parallel. Consider the transistor configuration shown in Fig. 1.28.

30
 Figure 1.28: CMOS 2-Input NOR Gate Schematic.

The series configuration of the pull-up network will only connect the output to VCC when both inputs
are 0. Conversely, the pull-down network prevents connecting the output to GND when both inputs are
0. When either or both of the inputs are true, the pull-up network is off, and the pull-down network is
on. This yields the logic function for a NOR gate. This operation is shown graphically in Fig. 1.29. As
with the NAND gate, the number of inputs can be increased by adding more PMOS transistors in series
in the pull-up network and more NMOS transistors in parallel in the pull-down network.

31
 Figure 1.29: CMOS 2-Input NOR Gate Operation.

The schematic for a 3-input NOR gate is given in Fig. 1.30. This approach can be used to increase
the number of inputs up until the fan-in specification of the logic family is reached.

32
 Figure 1.30: CMOS 3-Input NOR Gate Schematic.

1.4.2 Transistor-Transistor Logic (TTL)

One of the first logic families that emerged after the invention of the integrated circuit was transistor-
transistor logic (TTL). This logic family uses bipolar junction transistor (BJT) as its fundamental
switching item. This logic family defined a set of discrete parts that contained all of the basic gates
in addition to more complex building blocks. TTL was used to build the first computer systems in the
1960s. TTL is not widely used today other than for specific applications because it consumes more
power than CMOS and cannot achieve the density required for today’s computer systems. TTL is dis-
cussed because it was the original logic family based on integrated circuits, so it provides a historical
perspective of digital logic. Furthermore, the discrete logic pin-outs and part-numbering schemes are
still used today for discrete CMOS parts.

1.4.2.1 TTL Operation

TTL logic uses BJT transistors and resistors to accomplish the logic operations. The operation of a
BJT transistor is more complicated than a MOSFET; however, it performs essentially the same switch
operation when used in a digital logic circuit. An input is used to turn the transistor on, which in turn
allows current to flow between two other terminals. Fig. 1.31 shows the symbol for the two types of
BJT transistors. The PNP transistor is analogous to a PMOS and the NPN is analogous to an NMOS.
Current will flow between the emitter and collector terminals when there is a sufficient voltage on the
base terminal. The amount of current that flows between the emitter and collector is related to the current
flowing into the base. The primary difference in operation between BJTs and MOSFETs is that BJTs
require proper voltage biasing in order to turn on and also draw current through the base in order to stay
on. You learn the detailed operation of BJTs in another course (Electronic Devices).

33
 Figure 1.31: Bipolar Junction Transistor- PNP and NPN transistors.

Fig. 1.32 shows a simplified model of how TTL logic operates using BJTs and resistors. This
simplified model does not show all of the transistors that are used in modern TTL circuits but instead is
intended to provide a high-level overview of the operation. This gate is an inverter that is created with an
NPN transistor and a resistor. When the input is a logic HIGH, the NPN transistor turns on and conducts
current between its collector and emitter terminals. This in effect closes the switch and connects the
output to GND providing a logic LOW. During this state, current will also flow through the resistor to
GND through Q1, thus consuming more power than the equivalent gate in CMOS. When the input is a
logic LOW, the NPN transistor turns off and no current flows between its collector and emitter. This, in
effect, is an open circuit leaving only the resistor connected to the output. The resistor pulls the output up
to VCC providing a logic HIGH on the output. One drawback of this state is that there will be a voltage
drop across the resistor, so the output is not pulled fully to VCC .

34
 Figure 1.32: TTL Inverter - BJT Inverter Operation (Simplified).

1.4.3 The 7400 Series Logic Families

The 7400 series of TTL circuits became popular in the 1960s and 1970s. This family was based on
TTL and contained hundreds of different digital circuits. The original circuits came in either plastic
or ceramic dual-in-line packages (DIP). The 7400 TTL logic family was powered off of a +5 v sup-
ply. As mentioned before, this logic family set the pin-outs and part-numbering schemes for modern
logic families. There were many derivatives of the original TTL logic family that made modifications to
improve speed and reliability, decrease power, and reduce power supplies. Today’s CMOS logic families
within the 7400 series still use the same pin-outs and numbering schemes as the original TTL family.
It is useful to understand the history of this series because these parts are often used in introductory
laboratory exercises to learn how to interface digital logic circuits.

1.4.3.1 Part-Numbering Scheme

The part-numbering scheme for the 7400 series and its derivatives contains five different fields:

35
1. Manufacturer

2. Temperature Range

3. Logic Family

4. Logic Function

5. Package Type

The breakdown of these fields is shown in Fig. 1.33.

Figure 1.33: 7400 series part-numbering scheme.

36
1.4.3.2 DC Operating Conditions
Fig. 1.34 gives the DC operating conditions for a few of the logic families within the 7400 series. Notice
that the CMOS families consume much less power than the TTL families. Also notice that the TTL
output currents are asymmetrical (Look at IOMAX(H/L) column). The differences between the IOH and
IOL within the TTL families have to do with the nature of the bipolar transistors and the resistors used
to create the pull-up networks within the devices. CMOS has symmetrical drive currents due to using
complementary transistors for the pull- up (PMOS) and pull-down networks (NMOS).

Figure 1.34: DC operating conditions for a sample of 7400 series logic families.

1.4.3.3 Pin-Out Information for the DIP Packages

Fig. 1.35 shows the pin-out assignments for a subset of the basic gates from the 74HC logic family
in the dual-in-line package form factor. Most of the basic gates within the 7400 series follow these
assignments. Notice that each of these basic gates comes in a 14-pin DIP package, each with a single
VCC and single GND pin. It is up to the designer to ensure that the maximum current flowing through
the VCC and GND pins does not exceed the maximum specification. This is particularly important for
parts that contain numerous gates. For example, the 74HC00 part contains four, 2-input NAND gates.
If each of the NAND gates was driving a logic HIGH at its maximum allowable output current (i.e., 25
mA from Fig. 1.20), then a total of 4 × 25 mA + Iq = ∼100 mA would be flowing through its VCC pin.
Since the VCC pin can only tolerate a maximum of 50 mA of current (from Fig. 1.20), the part would
be damaged since the output current of ∼100 mA would also flow through the VCC pin. The pin-outs in
Fig. 1.35 are useful when first learning to design logic circuits because the DIP packages plug directly
into a standard breadboard.

37
Figure 1.35: Pin-outs for a subset of basic gates from the 74HC logic family in DIP packages.

38
 In-class Question 5: Why doesn’t the following CMOS transistor configuration yield a buffer?

1. In order to turn on the NMOS transistor, VGS needs to be greater than zero. In the given configu-
ration, the gate terminal of the NMOS (G) needs to be driven above the source terminal (S). If the
source terminal was at +3.4 v, then the input (In) would never be able to provide a positive enough
voltage to ensure the NMOS is on because "In" doesn’t go above +3.4 v.

2. There is no way to turn on both transistors in this configuration.

3. The power consumption will damage the device because both transistors will potentially be on.

4. The sources of the two devices can’t be connected together without causing a short in the device.

1.5 Driving Loads

At this point we’ve discussed in depth how proper care must be taken to ensure that not only do the
output voltages of the driving gate meet the input specifications of the receiver in order to successfully
transmit 1’s and 0’s but that the output current of the driver does not exceed the maximum specifications
so that the part is not damaged. The output voltage and current for a digital circuit depend greatly on the
load that is being driven. The following sections discuss the impact of driving some of the most common
digital loads.

1.5.1 Driving Other Gates

Within a logic family, all digital circuits are designed to operate with one another. If there is minimal
loss or noise in the interconnect system, then 1’s and 0’s will be successfully transmitted, and no current
specifications will be exceeded. Consider the example in Example 3 for an inverter driving another
inverter from the same logic family.

39
 Example 3: Determining if specifications are violated when driving another gate as a load.
Given: 74HC04 Specifications:

• II-max = 1 uA

• Iq = 20 uA

• IO-max = 25 mA

• ICC-max = 50 mA

Find: Were IO-max or ICC-max violated?

Solution: The maximum input current of the load (e.g., the receiving inverter) is 1 uA. This means
that IO for the driver will be 1 uA because the load sets the output current. This is far below the maximum
output current of 25 mA so the IO-max specification is not violated.
The driver will draw Iq through its VCC pin to power its functional operation. In addition to Iq the
driver will also pull a current equal to IO through the VCC pin while driving a logic HIGH. This means
the maximum current pulled through the VCC pin is Iq + IO = 20 uA + 1 uA = 21 uA. Again, this is well
below the specification for the maximum amount of current that can flow through the VCC pin (50 mA)
so the ICC-max specification is also not violated.
From this example, it is clear that there are no issues when a gate is driving another gate from the
same family. This is as expected because that is the point of a logic family. In fact, gates are designed
to drive multiple gates from within their own family. Based solely on the DC specifications for input
and output current, it could be assumed that the number of other gates that can be driven is simply IO-max
divide by II-max . For the example in Example 3, this would result in a 74HC gate being able to drive
25,000 other gates (i.e., 25 mA/1 uA = 25,000). In reality, the maximum number of gates that can be
driven is dictated by the switching characteristics. This limit is called the fan-out specification. The
fan-out specification states the maximum number of other gates from within the same family that can be
driven.
As discussed earlier, the output signal needs to transition quickly through the uncertainty region so
that the receiver does not have time to react and go to an unknown state. As more and more gates are
driven, this transition time is slowed down. The fan-out specification provides a limit to the maximum
number of gates from the same family that can be driven while still ensuring that the output signal
transitions between states fast enough to avoid the receivers from going to an unknown state. Example 4

40
shows the process of determining the maximum output current that a driver will need to provide when
driving the maximum number of gates allowed by the fan-out specification.

Example 4: Determining the output current when driving multiple gates as the load.
Given specifications:

• Fan-out = 3

• II-max = 1 uA

• Driving the maximum gates allowed by fan-out.

Find: IO .

Solution: The fan-out specification is 3, which means that the transmitting inverter can drive up to
3 other gates from its own logic family. Each of the receivers will draw their input current of II = 1 uA,
which will be provided by the driver. Therefore, the total amount of output current from the driver is
3 × 1 uA = 3 uA.

1.5.2 Driving Resistive Loads

There are many situations where a resistor is the load in a digital circuit. A resistive load can be an
actual resistor that is present for some other purpose such as a pull-up, pull-down, or for impedance
matching. More complex loads such as buzzers, relays, or other electronics can also be modeled as a
resistor. When a resistor is the load in a digital circuit, care must be taken to avoid violating the output
current specifications of the driver. The electrical circuit analysis technique that is used to evaluate how
a resistive load impacts a digital circuit is Ohm’s law. Ohm’s law is a very simple relationship between
the current and voltage in a resistor. Fig. 1.36 gives a primer on Ohm’s law. For use in digital circuits,
there are only a few cases that this technique will be applied to, so no prior experience with Ohm’s law
is required at this point.

1.5.2.1 Primer on Ohm’s Law

Ohm’s Law describes the relationship between current and voltage in a resistor. This simple equation is
used in nearly all electric circuit analysis. The equation is as follows:

41
 Figure 1.36: Ohm’s Law.

A resistor is characterized by its resistance, which describes how much current will flow when a
voltage is present across its two terminals. The units of resistance are Ohms (Ω = Volts / Amp). The
current in Ohm’s Law is defined to flow from + to - of the voltage.

Example 5: Use Ohm’s Law to to find the current flowing through the following resistor.

Solution: By plugging the parameters directly into Ohm’s Law we find:

V =I ×R (1.7)
3.4 = I × (1 k) (1.8)
I = 0.0034 A = 3.4 mA (1.9)

Let’s see how we can use Ohm’s law to analyze the impact of a resistive load in a digital circuit.
Consider the circuit configuration in Example 6 and how we can use Ohm’s law to determine the output
current of the driver. The load in this case is a resistor connected between the output of the driver and
the power supply (+5 v). When driving a logic HIGH, the output level will be approximately equal to
the power supply (i.e., +5 v). Since in this situation both terminals of the resistor are at +5 v, there is
no voltage difference present. That means when plugging into Ohm’s law, the voltage component is 0 v,
which gives 0 amps of current. In the case where the driver is outputting a logic LOW, the output will be
approximately GND. In this case, there is a voltage drop of +5 v across the resistor (5 v – 0 v). Plugging
this into Ohm’s law yields a current of 50 mA flowing through the resistor. This can become problematic
because the current flows through the resistor and then into the output of the driver. For the 74HC logic
family, this would exceed the IO-max specification of 25 mA and damage the part. Additionally, as more
current is drawn through the output, the output voltage becomes less and less ideal. In this example, the
first-order analysis uses VO = GND. In reality, as the output current increases, the output voltage will
move further away from its ideal value and may eventually reach a value within the uncertainty region.

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 Example 6: Determining the output current when driving a pull-up resistor as the load.
Give: The following circuit configuration:

Find: IO .

Solution: We need to solve for when the driver outputs both a HIGH and a LOW.

A similar process can be used to determine the output current when driving a resistive load between
the output and GND. This process is shown in Example 7.

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 Example 7: Determining the output current when driving a pull-down resistor as the load.
Give: The following circuit configuration:

Find: IO .

Solution: We need to solve for when the driver outputs both a HIGH and a LOW.

1.5.3 Driving LEDs

A light-emitting diode (LED) is a very common type of load that is driven using a digital circuit. The
behavior of diodes is typically covered in an analog electronics class. Here, the behavior of the LED will
be described using a highly simplified model. A diode has two terminals, the anode and cathode. Current

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that flows from the anode to the cathode is called the forward current. A voltage that is developed across
a diode from its anode to cathode is called the forward voltage. A diode has a unique characteristic that
when a forward voltage is supplied across its terminal, it will only increase up to a certain point. The
amount is specified as the LED’s forward voltage (Vf ) and is typically between 1.5 v and 2 v in modern
LEDs. When a power supply circuit is connected to the LED, no current will flow until this forward
voltage has been reached. Once it has been reached, current will begin to flow, and the LED will prevent
any further voltage from developing across it. Once current flows, the LED will begin emitting light. The
more current that flows, the more light that will be emitted up until the point that the maximum allowable
current through the LED is reached and then the device will be damaged. When using an LED, there
are two specifications of interest: the forward voltage and the recommended forward current. The
symbols for a diode and an LED are given in Fig. 1.37.

Figure 1.37: Symbols for a diode and a light-emitting diode.

When designing an LED driver circuit, a voltage must be supplied in order to develop the forward
voltage across the LED so that current will flow. A resistor is included in series with the LED for two
reasons. The first reason is to provide a place for any additional voltage provided by the driver to develop
in the situation that VO > Vf , which is most often the case. The second reason for the resistor is to set
the output current. Since the voltage across the resistor will be a fixed amount (i.e., VO – Vf ), then the
value of the resistor can be chosen to set the current. This current is typically set to an optimum value
that turns on the LED to a desired luminosity while also ensuring that the maximum output current of
the driver is not violated. Consider the LED driver configuration shown in Example 8 where the LED
will be turned on when the driver outputs a HIGH.

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 Example 8: Determining the output current when driving an LED where HIGH = ON.
Given:

Vf = +2v
If (rec) = 10mA

Find: R to achieve the recommended forward current of 10mA through the LED.

Solution:When the driver outputs a logic LOW, it will provide VO =O v. This means there will be no
voltage that develops across the series combination of the resistor and LED. Since there is not enough
voltage to meet the forward voltage requirements of the LED, no current will flow and the LED will be
OFF.
When the driver outputs a logic HIGH, it will provide VO =+5 v. This voltage will develop across
the series combination of the resistor and LED. The LED will increase up to its forward voltage of +2
v and then remain there. The rest of the output voltage will develop across the resistor (e.g., +3 v). We
can choose the value of the resistor to set the current that will flow through the series combination using
Ohm’s Law since we know the voltage across the resistor and the desired current. In this case, the LED
will be ON when the driver outputs a logic HIGH.

V = I.R
3 = (10mA).R
R = 300Ω

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 Example 9: Determining the output current when driving an LED where LOW = ON.
Given:

Vf = +1.8v
If (rec) = 4mA

Find: R to achieve the recommended forward current of 4 mA through the LED.

Solution:When the driver outputs a logic HIGH, it will provide VO =+3.4 v. This means there will
be no voltage that develops across the series combination of the resistor and LED. Since there is also at
+3.4 v. when driving a logic HIGH the LED will be OFF.
When the driver outputs a logic LOW, it will provide VO =0 v. Since the resistor is tied to +3.4 v, this
voltage will develop across the series combination of the resistor and LED. The LED will increase up to
its forward voltage of +1.8 v and then remain there. The rest of the output voltage will develop across

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the resistor (e.g., +1.6 v). We can choose the value of the resistor to set the current that will flow through
the series combination using Ohm’s Law since we know the voltage across the resistor and the desired
current. In this case, the LED will be ON when the driver outputs a logic LOW.

V = I.R
1.6v = (4mA).R
R = 400Ω

In-class Question 6: A fan-out specification is typically around 6–12. If a logic family has a maxi-
mum output current specification of IO-max = 25 mA and a maximum input current specification of only
II-max + 1 uA, a driver could conceivably source up to 25,000 gates (IO-max / II-max = 25 mA/ 1 uA =
25,000) without violating its maximum output current specification. Why isn’t the fan-out specification
then closer to 25,000?

1. The fan-out specification has significant margin built into it in order to protect the driver.

2. Connecting 25,000 loads to the driver would cause significant wiring congestion and would be
impractical.

3. The fan-out specification is in place to reduce power, so keeping it small is desirable.

4. The fan-out specification is in place for AC behavior. It ensures that the AC loading on the driver
doesn’t slow down its output rise and fall times. If too many loads are connected, the output
transition will be too slow, and it will reside in the uncertainty region for too long leading to
unwanted switching on the receivers.

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1.6 Assignments
1. Give the truth table for a 3-input AND gate with the input variables A, B, C and output F.
2. Give the truth table for a 3-input XNOR gate with the input variables A, B, C and output F.
3. Give the logic expression for a 3-input AND gate with the input variables A, B, C and output F.
4. Give the logic expression for a 3-input OR gate with the input variables A, B, C and output F. Give
the logic waveform for a 3-input AND gate with the input variables A, B, C and output F. Give the
logic waveform for a 3-input XNOR gate with the input variables A, B, C and output F.
5. Using the DC operating conditions from Table 1.34, give the noise margin HIGH (NMH ) for the
74LS logic family.
6. Using the DC operating conditions from Table 1.34, give the noise margin LOW (NML ) for the
74LS logic family.
7. Using the DC operating conditions from Table 1.34, give the noise margin HIGH (NMH ) for the
74HC logic family with VCC = +5 v.
8. Using the DC operating conditions from Table 1.34, give the noise margin LOW (NML ) for the
74HC logic family with VCC = +5 v.
9. For the driver configuration in Fig. 1.38, give the current flowing through the GND pin.
10. For the driver configuration in Fig. 1.38, give the current flowing through the VCC pin.

Figure 1.38: Driver Configuration for Assignment 9 and 10.

11. Using the data sheet excerpt from Fig. 1.21, give the maximum propagation delay (tpd ) for the
74HC04 inverter when powered with VCC = +2 v.

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12. Using the data sheet excerpt from Fig. 1.21, give the maximum propagation delay from low to high
(tPLH ) for the 74HC04 inverter when powered with VCC = +2 v. Note: When tpd is given instead of
tPHL and tPLH , that means the propagation delay is symmetrical (e.g., the delay is the same whether
the output goes from a LOW to HIGH or HIGH to LOW).

13. Using the data sheet excerpt from Fig. 1.21, give the maximum propagation delay from high to
low (tPHL ) for the 74HC04 inverter when powered with VCC = +2 v.

14. Using the data sheet excerpt from Fig.1.21, give the maximum transition time (tt ) for the 74HC04
inverter when powered with VCC = +2 v.

15. Using the data sheet excerpt from Fig. 1.21, give the maximum rise time (tr ) for the 74HC04
inverter when powered with VCC = +2 v. Note: When tt is given instead of tr and tf , that means the
transition time is symmetrical (e.g., the 10%-90% transition time is the same whether the output
goes from a LOW to HIGH or HIGH to LOW).

16. Using the data sheet excerpt from Fig. 1.21, give the maximum fall time (tf ) for the 74HC04
inverter when powered with VCC = +2 v.

17. Using the data sheet excerpt from Fig. 1.21, give the maximum propagation delay (tpd ) for the
74HC04 inverter when powered with VCC = +6 v.

18. Provide the transistor-level schematic for a 4-input NAND gate.

19. Provide the transistor-level schematic for a 4-input NOR gate.

20. Provide the transistor-level schematic for the 2-input AND Gate in CMOS.

21. Provide the transistor-level schematic for the 2-input OR Gate in CMOS.

22. Provide the transistor-level schematic for a Buffer in CMOS.

23. In the driver configuration shown in Fig. 1.39, the buffer is driving its maximum fan-out specifi-
cation of 6. The maximum input current for this logic family is II = 1 nA. What is the maximum
output current (IO ) that the driver will need to source?

Figure 1.39: Driver Configuration for Assignment 23.

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24. Calculate the value of the resistor shown in Fig. 1.40 in order to ensure that the output (IO ) does
not exceed 20 mA.

Figure 1.40: Driver Configuration for Assignment 24.

25. For the driver configuration shown in Fig. 1.41, calculate the values of the resistor in order to set
the LED forward current to 5 mA. The LEDs have a forward voltage of 1.9 v.

Figure 1.41: Driver Configuration for Assignment 25.

26. Calculate the value of the resistor shown in Fig. 1.42 in order to ensure that the forward current
does not exceed 5 mA and a voltage drop of 1.9 v.

Figure 1.42: Driver Configuration for Assignment 26.

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