Evaluation Board Documentation

ADE7753 Energy Metering IC

EVAL-ADE7753EB
FEATURES The evaluation board was designed so that the ADE7753 can be
Evaluation board is designed to be used together with evaluated in the end application, i.e., watt-hour meter. Using the
accompanying software to implement a fully functional appropriate transducers on the current channel, e.g., di/dt
energy meter (watt-hour meter) sensor, CT, and shunt, the evaluation board can be connected to
Easy connection of various external transducers via screw a test bench or high voltage (240 V rms) test circuit. An on-
terminals board resistor divider network provides the attenuation for the
Easy modification of signal conditioning components using line voltage. This data sheet also describes how the current
PCB sockets transducers should be connected for the best performance. The
LED indicators on logic outputs CF, ZX, SAG, and IRQ ADE7753 has a built-in digital integrator that allows for simple
Optically isolated data output connection to PC parallel port interfacing with any di/dt sensor (such as the Rogowski coil).
Optically isolated frequency output (CF) to BNC
External reference option available for on-chip reference The evaluation board (watt-hour meter) is configured and
evaluation calibrated via the parallel port of a PC. The data interface
between the evaluation board and the PC is fully isolated.
GENERAL DESCRIPTION
Windows® based software is provided with the evaluation board
The ADE7753 is a high accuracy electrical power measurement so it can be configured quickly as an energy meter.
IC with a serial interface and pulse output. The ADE7753
incorporates two second-order Σ-Δ ADCs, reference circuitry, The evaluation board also functions as a standalone evaluation
temperature sensor, and all the signal processing required to system, which can be incorporated easily into an existing system
perform active, reactive, and apparent energy measurement. via a 25-way D-Sub connector.

This data sheet describes the ADE7753 evaluation kit’s The evaluation board requires two external 5 V power supplies
hardware and software functionality. The ADE7753 evaluation (one is required for isolation purposes) and the appropriate
board, together with the ADE7753 data sheet and the EVAL- current transducer.
ADE7753EB data sheet, provides a complete evaluation
platform for the ADE7753.

FUNCTIONAL BLOCK DIAGRAM

AGND AVDD DVDD DGND +5V V+ V–

V1P
FILTER DOUT
NETWORK SCLK
V1N 74HC08 DIN
CS
AGND ADE7753 CONNECTOR
RESET
TO PC
PARALLEL
PORT
74HC08
V2N FILTER
NETWORK
AND
V2P ATTENUATION BNC
EXTERNAL BNC
EXTERNAL 2.5V CLOCK IN OPTICALLY CF
REFERENCE
AD780 COUPLED
FREQUENCY
OUTPUT
CF ZX SAG IRQ
PROTOTYPE
AREA
04728-0-001

Figure 1.

Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
or otherwise under any patent or patent rights of Analog Devices. Trademarks and Tel: 781.329.4700 www.analog.com
registered trademarks are the property of their respective owners. Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
EVAL-ADE7753EB

TABLE OF CONTENTS
Analog Inputs (SK1 and SK2) ......................................................... 3 Online Help................................................................................. 10

Current Sense Inputs (SK2) ........................................................ 3 Measuring CT Phase Errors Using the ADE7753.................. 11

Using a di/dt Sensor as the Current Transducer ...................... 3 Using Phase Calibration to Correct Small (<0.5°) External
Phase Errors ................................................................................ 11
Using a CT as the Current Transducer...................................... 4
Correcting Large External Phase Errors ................................. 11
Using a Shunt Resistor as the Current Transducer .................. 4
Evaluation Board Bill of Materials ............................................... 12
Voltage Sense Inputs .................................................................... 5
Evaluation Board Schematic (Rev. D and Rev. E) ...................... 13
Jumper Settings ................................................................................. 6
PCB Layout—Component Placement (Rev. D).......................... 14
Setting Up the ADE7753 Evaluation Board .................................. 7
PCB Layout—Component Side (Rev. D)..................................... 15
Evaluation Software.......................................................................... 8
PCB Layout—Solder Side (Rev. D) .............................................. 16
Installing the ADE7753 Software ............................................... 8
PCB Layout—Component Placement (Rev. E) .......................... 17
Removing the ADE7753 Evaluation Software.......................... 8
PCB Layout—Component Side (Rev. E) ..................................... 18
Main Menu.................................................................................... 8
PCB Layout—Solder Side (Rev. E) ............................................... 19
Calibrating the Meter................................................................... 9
Ordering Guide .......................................................................... 20
Menu Selections............................................................................ 9

Waveform Sampling Routine.................................................... 10

REVISION HISTORY
4/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 20
 EVAL-ADE7753EB

ANALOG INPUTS (SK1 AND SK2)

Voltage and current signals are connected at the screw terminals USING A DI/DT SENSOR AS THE CURRENT
SK1 and SK2, respectively. All analog input signals are filtered TRANSDUCER
using the on-board antialiasing filters before being presented to Figure 3 shows how a di/dt sensor can be used as a current
the analog inputs of the ADE7753. The default component transducer in a signal-phase, 2-wire distribution system. A di/dt
values, which are shipped with the evaluation board, are the sensor is typically made from an air-core coil. Because of the
recommended values for the ADE7753. Users can easily change mutual inductance between the coil and the phase wire, a
these components if they are familiar with selecting the voltage signal is output from the coil, which is proportional to
component values for the analog input filters. Interested users the time differentiation of the current (di/dt).
are encouraged to refer to the ADE7753 data sheet for a more
PHASE
comprehensive description of the antialiasing filters and their WIRE
function. JP15 JP1
TP1
CURRENT SENSE INPUTS (SK2) 100Ω 1kΩ
V1P
JP2 C11 33nF C50 33nF
SK2 is a 3-way connection block that allows the ADE7753 to be JP25 JP3
TP2
connected to a current transducer. Figure 2 shows the connector
V1N
SK2 and the filtering network provided on the evaluation board. JP4
100Ω 1kΩ
C21 33nF C51 33nF

The resistors SH1A and SH1B are by default not populated.

04728-0-003
ADE7753
They should be used as burden resistors when a CT is used as
the current transducer (see the Using a CT as the Current di/dt FULL-SCALE
CURRENT DIFFERENTIAL INPUT = 62.5mV
Transducer section). SENSOR AT GAIN = +8

The RC networks R41/C11 and R42/C21 provide attenuation Figure 3. di/dt Sensor Connection to Current Channel
of high frequency noise and equalize the 20 dB/dec gain at high
The di/dt sensor outputs a voltage by mutual inductance. When
frequency when the di/dt sensor is used as the current
using a di/dt sensor as the current sensor, Jumpers JP15/JP25
transducer (see the Using a di/dt Sensor as the Current
and JP1/JP3 should be left open. Both sets of filters are
Transducer section). These RC networks are easily disabled by
necessary to provide the antialiasing filters (see Figure 3).
placing JP15 and JP25 and removing C11 and C21 (socketed).
In theory, air-core di/dt sensors have an associated phase shift
The RC networks are the antialiasing filters required by the on-
of +90° at all input frequencies. This phase shift is compensated
chip ADCs. The default corner frequency for these low-pass
by the −90° phase shift of the integrator. Additional phase error,
filters (LPF) is selected as 4.8 kHz (1 kΩ and 33nF). These filters
from external component mismatch, for example, can be
can easily be adjusted by replacing the components on the
corrected by writing to the phase calibration register
evaluation board.
(PHCAL[7:0]) in the ADE7753. The software supplied with the
ADE7753 evaluation board allows users to adjust the phase
SH1A JP15 JP1
calibration register. See the Evaluation Software section for
TP1 more information.
R41 R50
SK2 1 V1P
100Ω 1kΩ
JP2 C11 33nF C50 33nF For this example, notice that the maximum analog input range
JP25 JP3
TP2 on Channel 1 is set to 62.5 mV, and the gain for Channel 1 has
R42 R51
SK2 2
100Ω 1kΩ
V1N been set to 8. The maximum analog input range and gain are set
JP4 C21 33nF C51 33nF via the gain register (GAIN). See the ADE7753 data sheet. The
evaluation software allows users to configure the channel range
04728-0-002

ADE7753
SK2 3 SH1B and gain. The maximum peak differential signal on Channel 1 is
0.5 V (at Gain = +1).

Figure 2. Current Channel on the ADE7753 Evaluation Board

Rev. 0 | Page 3 of 20
EVAL-ADE7753EB
USING A CT AS THE CURRENT TRANSDUCER USING A SHUNT RESISTOR AS THE CURRENT
Figure 4 shows how a CT can be used as a current transducer in TRANSDUCER
a signal phase 3-wire distribution system. This is how electrical Figure 5 shows how a shunt resistor can be used to perform the
energy is distributed to residential users in the United States. current-to-voltage conversion required for the ADE7753. A
Phase A and Phase B are nominally 180° out of phase. The shunt is a cost-effective way to perform the current-to-voltage
vector addition of the two currents is easily achieved by using conversion in a 2-wire, single-phase application. No isolation is
two primary turns of opposite polarity on the CT. required in a 2-wire application, and the shunt has advantages
PHASE B
over the CT arrangement. For example, a shunt does not suffer
SH1A
from dc saturation problems, and the phase response of the
IMAX = 80A JP15 JP1
CT
2.8Ω shunt is linear over a very wide dynamic range. Although the
TP1
1:1800 shunt is predominately resistive, it does have parasitic reactive
V1P
100Ω 1kΩ 355mV
JP2 C50 33nF RMS
elements (inductance) that can become significant, even at
JP25 JP3
TP2 50 Hz/60 Hz. This means that there can be a small phase shift
100Ω 1kΩ
V1N associated with the shunt. Once it is understood, the phase shift
JP4 C51 33nF is easily compensated for with the filter network R41/C11 and
PHASE A R42/C21 (see Application Note AN-559 for more details).
04728-0-004
ADE7753
SH1B
2.8Ω
The shunt used in this example is a 200 µΩ Manganin® type.
FULL-SCALE
DIFFERENTIAL INPUT = 250mV The resistance of the shunt should be as low as possible in order
AT GAIN = +2
to avoid excessive power dissipation in the shunt. Figure 5
Figure 4. CT Connection to Current Channel shows how the shunt can be connected to the evaluation board.
Two sense wires should be soldered to the shunt as shown at the
The CT secondary current is converted to a voltage by using a
copper/Manganin junctions. These sense wires should be
burden resistance across the secondary winding outputs. Care
formed into a twisted pair to reduce the loop area that reduces
should be taken when using a CT as the current transducer. If
antenna effects. A connection for the common-mode voltage
the secondary is left open, i.e., no burden is connected, a large
can be made at the connection point for the current carrying
voltage could be present at the secondary outputs. This can
conductor (see Figure 5).
cause an electrical shock hazard and potentially damage
electronic components. TWISTED-PAIR
CONNECTION
JP15 JP1
When using a CT as the current sensor, the phase compensation 200µΩ
TP1
network for a shunt application should be disabled. This is V1P
100Ω 1kΩ 16mV
achieved by closing Jumpers JP15/JP25 and removing C11/C21. JP2
JP25
C11 33nF
JP3
C50 33nF RMS
The antialiasing filters should be enabled by opening TP2
V1N
Jumpers JP1/JP3 (see Figure 4). 100Ω 1kΩ
80A JP4 C21 33nF C51 33nF
Most CTs have an associated phase shift of between 0.1° and 1°
ADE7753
at 50 Hz/60 Hz. This phase shift or phase error can lead to
significant energy measurement errors, especially at low power

04728-0-005
FULL-SCALE
BVM-D-R0002-5.0
factors. However, this phase error can be corrected by writing to DIFFERENTIAL INPUT = 31.25mV
AT GAIN = +16
the phase calibration register (PHCAL[7:0]) in the ADE7753.
The software supplied with the ADE7753 evaluation board Figure 5. Shunt Connection to Current Channel
allows users to adjust the phase calibration register. See the
Evaluation Software section for more information.

For this example, notice that the maximum analog input range
on Channel 1 is set to 250 mV, and the gain for Channel 1 has
be set to 2. The maximum analog input range and gain are set
via the gain register (GAIN). See the ADE7753 data sheet. The
evaluation software allows users to configure the channel range
and gain.

Rev. 0 | Page 4 of 20
 EVAL-ADE7753EB
VOLTAGE SENSE INPUTS Note that the analog input V2N is connected to AGND via the
The voltage input connections on the ADE7753 evaluation antialiasing filter R57/C54 using JP10. Also, Jumper JP9 should
board can be directly connected to the line voltage source. be left open.
The line voltage is attenuated using a simple resistor divider The voltage attenuation network is made up of R53, R54, and
network before it is presented to the ADE7753. Because of the R56. The maximum signal level permissible at V2P is 0.5 V
relatively large signal on this channel and the small dynamic peak. Although the ADE7753 analog inputs can withstand ±6 V
range requirement, the voltage channel can be configured in a without risk of permanent damage, the signal range should not
single-ended configuration. Figure 6 shows a typical connection exceed ±0.5 V with respect to AGND for specified operation.
for the line voltage.
The attenuation network can be easily modified by the user to
PHASE
JP9 accommodate any input signal levels. However, the value of R56
TP5
SK1 1 R57 (1 kΩ) should not be altered as the phase response of Channel 2
V2N
JP10
1kΩ
C54 33nF
should match the phase response of Channel 1 (see Application
JP7 Note AN-559).
R53 R54 JP51 TP4
SK1 2
V2P
499kΩ 499kΩ
JP8 R56 C53 100mV RMS
ATTENUATION TO
1kΩ 33nF
NETWORK 250mV RMS
100V RMS TO 250V RMS ADE7753 04728-0-006

NEUTRAL

Figure 6. Voltage Channel on the ADE7753 Evaluation Board

Rev. 0 | Page 5 of 20
EVAL-ADE7753EB

JUMPER SETTINGS
Table 1.
Jumper Option Description
JP1 Closed This shorts out R50. The effect is to disable the antialiasing filter on the analog input V1P. Default open.
Open Enable the antialiasing filter on V1P.
JP2 Closed This connects the analog input V1P to ground. Default open.
JP3 Closed This shorts out R51. The effect is to disable the antialiasing filter on the analog input V1N. Default open.
Open Enable the antialiasing filter on V1N.
JP4 Closed This connects the analog input V1N to ground. Default open.
JP5 A This connects the buffered logic output IRQ to the LED1.
B This connects the buffered logic output IRQ to Pin 10 on the D-Sub connector via an optical isolator.
JP6 A This connects the buffered logic output SAG to the LED2.
B This connects the buffered logic output SAG to Pin 11 on the D-Sub connector via an optical isolator.
JP7 Closed This shorts the attenuation network on Channel 2. Default open.
JP8 Closed This connects the analog input V2P to ground. Default open.
JP9 Closed This shorts out R57. The effect is to disable the antialiaing filter on the analog input V2N. Default open.
Open Enable the antialiasing filter on V2N.
JP10 Closed This connects the analog input V2N to ground. Default open.
JP11 Closed This connects the analog and digital ground planes of the PCB. Default closed.
JP12 A This connects the buffered logic output CF to the LED4.
B This connects the buffered logic output CF to the BNC2 connector via an optical isolator.
JP13 Closed This connects an external reference 2.5 V (AD780) to the ADE7753.
Open This enables the ADE7753 on-chip reference.
JP14 Closed This connects the optical isolator ground to the evaluation board ground (DGND). If full isolation between the
evaluation board and PC is required, this jumper should be left open.
JP15 Closed This shorts out R41. The effect is to disable the first-state antialiasing filter (for di/dt sensors or for shunts) on the
analog input V1P. Default open.
JP19 A This connects the buffered logic output ZX to the LED3.
B This connects the buffered logic output ZX to Pin 12 on the D-Sub connector via an optical isolator.
JP20 Closed This connects the AVDD and DVDD supply for the evaluation board together. Default closed.
JP21 Closed This connects the DVDD and 5 V (buffers) supply for the evaluation board together. Default closed.
JP25 Closed This shorts out R42. The effect is to disable the first-state antialiasing filter (for di/dt sensors or shunt) on the analog
input V1N. Default open.
JP51 Closed This shorts out/disconnects analog input V2P from the ADE7753. Default closed.

ADE7753/6/9 - Eval Rev D

JP21
JP20
JP14

JP15 JP1
JP2

JP4
JP25 JP3
ADE7753

JP9
JP51
JP10 AB
JP13 JP11
JP5
JP7
JP6

JP8 JP19
JP12
AB
04728-0-007

Figure 7. ADE7753 Evaluation Board Jumper Positions

Rev. 0 | Page 6 of 20
 EVAL-ADE7753EB

SETTING UP THE ADE7753 EVALUATION BOARD

Figure 8 shows a typical setup for the ADE7753 evaluation The evaluation board is connected to the PC parallel port using
board. In this example, a kWh meter for a 2-wire, single-phase the cable supplied. The cable length should not exceed 6 feet
distribution system is shown. For a more detailed description (2 meters) or the serial communication between the PC and the
on how to use a di/dt as a current transducer, see the Current evaluation board may become unpredictable and error prone.
Sense Inputs (SK2) section. The line voltage is connected
directly to the evaluation board, as shown in Figure 8. Note JP7 When the evaluation board has been powered up and is
should be left open to ensure that the attenuation network is not connected to the PC, the supplied software can be launched.
bypassed, and also note the use of two power supplies. The The software automatically starts in energy meter mode. The
second power supply is used to power the optical isolation. With next section describes how the ADE7753 evaluation software
JP14 left open, there is no electrical connection between the can be installed and removed.
high voltage test circuit and the PC. The power supplies should
have floating voltage outputs.

– –
5.000 V 5.000 V
+ +
NEUTRAL
PHASE
DVDD DGND +5V V+ V–

SK4 SK5
di/dt CURRENT SENSOR
220V JP1 = OPEN
JP15 JP1
SK2 JP2 = OPEN
R41 R50 JP3 = OPEN
V1P JP4 = OPEN
100Ω 1kΩ JP5 = B
JP2 C11 33nF C50 33nF JP6 = B
JP25 JP3
JP7 = OPEN
R42 R51 JP8 = OPEN TO PC
V1N JP9 = OPEN PARALLEL
100Ω 1kΩ JP10 = CLOSED PORT
JP4 C21 33nF C51 33nF JP11 = CLOSED
JP12 = B
JP13 = OPEN
AGND JP14 = OPEN
JP15 = OPEN
JP19 = B
SK1 JP9 JP20 = CLOSED
JP21 = CLOSED BNC2
R57 JP25 = OPEN
V2N
1kΩ
JP10 C54 33nF 310mV RMS
JP7
FREQUENCY COUNTER
R53 R54
V2P
499kΩ 499kΩ 1.0666 Hz
JP8 R56 C53 04728-0-008
1kΩ 33nF
LOAD

Figure 8. Typical Setup for the ADE7753 Evaluation Board

Rev. 0 | Page 7 of 20
EVAL-ADE7753EB

EVALUATION SOFTWARE
The ADE7753 evaluation board is supported by Windows based
software that allows users to access all the functionality of the
ADE7753. The software is designed to communicate with the
ADE7753 evaluation board via the parallel port of the PC.

INSTALLING THE ADE7753 SOFTWARE

The ADE7753 software is supplied on a CD. The minimum
requirements for the PC are Pentium® II 233 MHz processor,
32 MB RAM, 10 MB free HD space, and at least one PS/2 or
ECP parallel port. To install the software, place the CD in the
drive and double-click setup.exe. This launches the setup
program, which automatically installs all the software
components, including the uninstall program, and creates the
required directories. When the setup program has finished
installing the ADE7753eval program, users are prompted to
install National Instruments’ run-time engine. This software
was developed using National Instruments’ LabVIEW™
software, and the run-time engine is required in order to run
the ADE7753eval program. GIVEIO software is required to run
the program on all systems. Users are prompted to install this
software as well, and they should follow the on-screen
instructions to complete the installation. Users need to reboot
their computers to complete the installation. To launch the Figure 9. Removing the ADE7753 Evaluation Software
software, select Start—>Programs—>ADE7753 menu and click
on ADE7753eval. MAIN MENU
When the software is launched, the program automatically
REMOVING THE ADE7753 EVALUATION displays up the menu screen shown in Figure 10. To stop the
SOFTWARE ADE7753eval software, select Exit from the menu. Each of the 9
The ADE7753Eval program, National Instruments’ run-time selections in the menu starts a new window that accesses the
engine, and GIVEIO are easily removed by using the Add registers and displays information from the ADE7753. By
or Remove Programs feature in the Control Panel. Select pressing the Exit button in the new window, users are brought
Start—>Control Panel—>Add or Remove Programs and click back to the main menu. Register values are not reset by the
the program to remove it. program when a new window opens or closes. The register
addresses and functionality can be found in the ADE7753
data sheet.

Using the ADE7753eval software, the evaluation board can be

used as a fully functional energy meter. When the appropriate
line voltage, test current, frequency, and meter constant are set
up, users can use the calibration routine to remove any errors
associated with the transducers. The CF output can be used
with a standard frequency counter to check the accuracy. The
measured CF output frequency should be adjusted to match the
theoretical CF frequency of the evaluation software.

Note that the calibration routine does not automatically remove

the phase mismatch errors associated with the current and
voltage transducer. These must be removed by using the
ADE7753 PHCAL register. This is explained in the Measuring
CT Phase Errors Using the ADE7753 section. The calibration
routine is launched by selecting Calibration from the menu.

Rev. 0 | Page 8 of 20
 EVAL-ADE7753EB
Ensure that the analog input signal levels have been matched to
the transducer output signal levels, as previously described.

Figure 10. Main Menu

Note also that the input signal range and gain must be set for
Figure 11. Calibration Window
the PGAs on Channel 1 and Channel 2. This ensures that the
output signal range from the transducers is matched to the MENU SELECTIONS
analog inputs. For example, by selecting a gain of 1 for the PGA The menu selections include the following: Interrupt Registers,
in Channel 2, the peak differential input signal is set to 500 mV. Active Energy, Reactive Energy, Apparent Energy, Offsets, Power
In the meter example shown in Figure 8, the line voltage is Quality Information, Line Accumulation, Calibration, and
attenuated to approximately 215 mV rms or 304 mV peak. Temperature.
Similarly as an example for Channel 1, assuming a maximum
current of 120 A, the maximum differential output signal from The mask and status interrupt registers described in the
the di/dt sensor is 30 mV rms or 42 mV peak (the value ADE7753 data sheet are accessible from the Interrupt Registers
depends on the sensor used). To allow for surge current, the window. In the Active Energy, Reactive Energy, and Apparent
full-scale differential input signal level is set to 62 mV by setting Energy windows, users can view the datapath, configure or reset
the gain to 2 if the ADC input range is set to 0.125 V (see the part by writing to the necessary registers, and read the
Table I in the ADE7753 data sheet). Access to the PGAs is active, reactive, or apparent energy registers.
allowed in the active energy, apparent energy, and reactive
In addition, Waveform Sampling is available from any of these
energy windows that can be opened from the menu.
selections. Figure 12 shows the Active Energy window.
CALIBRATING THE METER
In order to calibrate the energy meter, the line voltage, test
current, line frequency, and meter constant must be entered, as
shown in Figure 11. In this example, the line voltage is 220 V, the
test current is 5 A, the frequency is 50 Hz, and the required
meter constant is 3,200 imp/kWh. The menu lists the option for
calibrating active, reactive, or apparent energy. When the
parameters are entered, the voltage and current circuits are
energized, and the energy is selected, click the Calibrate button.
The software then executes the calibration routine and
automatically starts to register energy.

Calibration can be done by changing the CFDEN, CFNUM, and

WGAIN (or VAGAIN) registers, which is explained in the Figure 12. Active Energy Window
ADE7753 data sheet. The measured CF output frequency is
then adjusted to match the theoretical CF frequency of the Channel 1, Channel 2, active power, and rms offset registers are
evaluation software. To write to CFNUM, CFDEN, and WGAIN accessible via the Offsets selection from the menu. The user
for manual calibration, click Adjust Values. Calibration should may modify and view rms, peak, and SAG registers from the
be run before this is done to calculate the target frequency. Power Quality window. Additionally, the relevant mask and
status registers are presented in this window.

Rev. 0 | Page 9 of 20
EVAL-ADE7753EB
The Line Accumulation window allows one to view line When using this feature with sine-wave signals, the user should
accumulation active energy, line accumulation VA energy, and be aware that if the samples represent a noninteger number of
reactive energy. To begin line accumulation, press the Start Read periods of the selected signal, then the rms and mean values are
button. The number of line cycles can be changed in this biased. To correct this, the number of samples should be chosen
window at any time. to give an integer number of signal cycles:

WAVEFORM SAMPLING ROUTINE No. of Signal Cycles × ADE7753 CLKIN Frequency

No. of Samples =
1024 × Signal Frequency
In this mode, the evaluation software programs the ADE7753
for waveform sampling with an updated rate of 3.5 kSPS
ONLINE HELP
(CLKIN/1024). The user can define the number of samples
needed and select the signal waveform to transfer. The options The ADE7753 evaluation software also comes with an online
are Channel 1, Channel 2, or multiplier waveforms. Three help feature. Select Help —> Show Help from the menu (see
parameters are processed when the waveform is displayed: rms Figure 14). A Help Window opens. For a description of a
value, mean value, and standard deviation. For comparison, the particular option, e.g., button or text box, move the cursor over
voltage and current rms registers are shown in the waveform the item. The Help window displays a description of the item.
sampling window. The waveform sampling routine can be
accessed from the Active Energy, Reactive Energy, Apparent
Energy, or Power Quality windows by pressing the waveform
sampling button. Figure 13 shows the Waveform Sampling
window.

Figure 14. Online Help Function

Figure 13. Waveform Sampling

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 EVAL-ADE7753EB
MEASURING CT PHASE ERRORS USING THE USING PHASE CALIBRATION TO CORRECT SMALL
ADE7753 (<0.5°) EXTERNAL PHASE ERRORS
The ADE7753 can measure the phase error associated with the From the previous example, it is seen that the CT introduced a
current sensor during calibration. The ADE7753 has negligible phase lead in Channel 1 of 0.091°. Therefore, instead of a 60°
internal phase error (PHCAL = 00 hex), and the error due to phase difference between Channel 1 and Channel 2, it is
external components is small (<0.5°). The procedure is based on actually 59.89°. In order to bring the phase difference back to
a 2-point measurement, at PF = 1 and PF = 0.5 (lag). The PF is 60°, the phase compensation circuit in Channel 2 is used to
set up using the test bench source, and this source must be very introduce an extra lead of 0.091°. This is achieved by reducing
accurate. The ADE7753 should be configured for energy the amount of time delay in Channel 2.
measurement mode.
The maximum time delay adjustment in Channel 2 is −97.86 µs
An energy measurement is first made with PF = 1 to +39.96 µs with a CLKIN of 3.579545 MHz. The PHCAL
(Measurement A). A second energy measurement should be register is a signed twos complement 6-bit register. Therefore,
made at PF = 0.5 (Measurement B). The frequency output CF each LSB is equivalent to 2.22 µs. The default value of this
can be used for this measurement. Using the following formula, register is 0x0D and is equivalent to 0.00°. In this example, the
the phase error is easily calculated: line frequency is 50 Hz. This means each LSB is equivalent to
360° × 2.22 µs × 50 Hz = 0.040°. To introduce a lead of 0.091°,
⎛ B − A2 ⎞ the delay in Channel 2 must be reduced. This is achieved by
Phase Error (°) = tan −1 ⎜ ⎟
⎜A × 3⎟ writing 0xB or +0.08° to the PHCAL register. The PHCAL
⎝ 2 ⎠
register can be written to by entering the value in the active
For example, using the frequency output CF to measure power, energy window.
a frequency of 3.66621 Hz is recorded for PF = 1. The PF is then
CORRECTING LARGE EXTERNAL PHASE ERRORS
set to 0.5 lag and a measurement of 1.83817 Hz is obtained.
Using the formula above, the phase error on Channel 1 is In this example, the phase correction range at 50 Hz is
calculated as approximately +1.7 and −0.7°. However, it is best to use the
PHCAL register only for small phase corrections, i.e., <0.5. If
⎛ 1.83817 − 3.6662 1 2 ⎞ larger corrections are required, the larger part of the correction
Phase Error (°) = tan −1 ⎜ ⎟ = 0.091°
⎜ 3.6662 1 × 3 ⎟ can be made using an external passive component. For example,
⎝ 2 ⎠ the resistors in the antialiasing filter can be modified to shift the
The formula also gives the correct sign for the phase error. In corner frequency of the filter to introduce more or less lag. The
this example, the phase error is calculated as 0.091° at the input lag through the antialiasing filters with 1 kΩ and 33 nF is 0.56°
to Channel 1 of the ADE7753. This means that the current at 50 Hz. Fine adjustment can be made with the PHCAL
sensor has introduced a phase lead of 0.091°. Therefore, the register. Note that typically CT phase shift does not vary
phase difference at the input to Channel 1 is now 59.89° lag significantly from part to part. If a CT phase shift is 1°, then the
instead of 60° lag. Determining whether the error is a lead or part-to-part variation should only be about ±0.1°. Therefore, the
lag can also be figured intuitively from the frequency output. bulk of the phase shift (1°) can be canceled with fixed
Figure 15 shows how the output frequency varies with phase component values at design. The remaining small adjustments
(cos {Φ}). Because the Output Frequency B (1.83817 Hz) at the can be made in production using the PHCAL register.
PF = 0.5 lag setting in the example is actually greater than A/2
(1.833105 Hz), the phase error between Channel 1 and Channel 2
is actually less than 60°. This means there is additional lead in
Channel 1 due to the CT.
CF (Hz) FREQUENCY B > A/2
PHASE DIFFERENCE < 60° LAG
PF = 1
PF > 0.5
PF = 0.5
PF < 0.5

PF = 0
60° 360°

PHASE LAG
04728-0-015

Figure 15. CF Frequency vs. Phase (PF)

Rev. 0 | Page 11 of 20
EVAL-ADE7753EB

EVALUATION BOARD BILL OF MATERIALS

Table 2.
Designator Value Description
R3, R5, R6, R13, R22, 100 Ω, 5%, ¼ Ω Resistor, No Special Requirements.
R30, R31, R33, R34, R37
R2, R7 to R10, R39, R40 10 kΩ, 5%, ¼Ω Resistor, No Special Requirements.
R1, R14 to R27, R36 820 Ω, 5%, ¼ Ω Resistor, No Special Requirements.
R50 to R52, R57 1 kΩ, 0.1%, ¼ Ω ±5 ppm/°C Resistor, Good Tolerance, Used as Part of the Analog Filter Network.
These resistors are not soldered but are plugged into the PCB pin sockets for easy
modification by the customer. Low drift Vishay Dale Part No. CMF551001BT-2.
R53, R54 499 kΩ, 0.1%, ¼ Ω ±5 ppm/°C Resistor, Good Tolerance. Vishay Dale Part No. CMF554993FT-1.
R41, R42 100 Ω, 0.1%, ¼ Ω ±5 ppm/°C Resistor, Good Tolerance. Low drift Vishay Dale Part No. CMF551000BT-2.
R11 51 Ω, 1%, ¼ Ω Not Populated, Pin Socket to Be Used with External 50 Ω Clock Source.
R4 0 Ω, 10%, ¼ Ω
C5, C7, C24,C28, C30 10 µF, 10 V dc Power Supply Decoupling Capacitors, 20%, AVX-Kyocera, Farnell Part No. 643-579.
C14, C15 22 pF, Ceramic Gate Oscillator Load Capacitors, Farnell Part No. 108-927.
C6, C8, C23, C25, C27, 100 nF, 50 V Power Supply Decoupling Capacitors, 10%, X7R type, AVX-Kyocera, Farnell Part No. 108-950.
C29, C31 to C36
C16 220 pF AVX-Kyocera, Farnell Part No. 108-946.
C11, C21, C50, 33 nF, 10%, 50 V X7R Capacitor, Part of the Filter Network. These resistors are not soldered but
C51, C53, C54 are plugged into the PCB mount sockets for easy modification by the customer.
The SR15 series AVX-Kyocera, Farnell Part No. 108-948.
U1 ADE7753ARS Supplied by Analog Devices, Inc.
U2, U3 74HC08 Quad CMOS AND Gates.
U4 AD780 2.5 V Reference, Supplied by Analog Devices, Inc.
U5, U7 to U9 HCPL2232 HP Optical Isolator, Newark Part No. 06F5434.
U6 HCPL2211 HP Optical Isolator, Newark Part No. 06F5428.
LED1 to LED4 LED Low Current, Red, Farnell Part No. 637-087.
XTAL 3.579545 MHz Quartz Crystal, HC-49 (US), ECS Part No. ECS-35-17-4.
Digi-Key Part No. X079-ND.
SK1, SK3, SK5 Screw Terminal 15 A, 2.5 mm Cable Screw Terminal Sockets. Farnell Part No. 151-785, Length 10 mm,
Pitch 5 mm, Pin Diameter 1 mm.
SK2, SK4 Screw Terminal 15 A, 2.5 mm Cable Screw Terminal Sockets. Farnell Part No. 151-786. Length 15 mm,
Pitch 5 mm, Pin Diameter 1 mm.
BNC1, BNC2 BNC Connector Straight Square, 1.3 mm Holes, 10.2 mm × 10.2 mm Farnell Part No. 149-453.
P1 D-Sub 25-Way Male AMP 747238-4 Right Angle D-Sub 8 mm PCB Mount, Digi-Key Part No. 747238-4.
TP4 to TP14 Test Point Loop Test Point Loop, Compnt Corp. TP-104-01-XX.
JP1 to JP4, JP7 to 2-Pin Header 2-Pin, 0.025 Sq., 0.01 Ctrs, Compnt Corp., CSS-02-02.
JP11, JP13 to JP15,
JP20,JP21,JP25, JP51
JP5, JP6, JP12, JP19 2-Pin Header × 2 2-Pin, 0.025 Sq., 0.01 Ctrs, Compnt Corp., CSS-02-02.
Pin Sockets DIL Sockets for U1 to U9, 0.022” to 0.025” Pin Diameter, ADI Stock 12-18-33.
ADVANCE KSS100-85TG.
Pin Sockets Discretes R11, R41, R42, R50 to R54, R57, C11, C21, C50 to C54. ADI Stock 12-18-41 .

Rev. 0 | Page 12 of 20
 +5V
DVDD C35
2 1
C27 1 C28 + 8 1
0.1µF VCC
SK4 100nF 2 10µF
1 JP21
2 1 2
1
R34 2 2
7
3 VO1
2
AVDD 100Ω
TBLK03 C29 C30 TP3 RESETBIN
JP20 DIN2 U5 1 R36 2 VMINUS
100nF 1 10µF + 1 2 HCPL2232 3 P1
1 1
R33 2 3
820Ω
1 1 6
+5V C31 C32 3 U3 VO2
0.1µF 7408 2 100Ω VPLUS
AVDD 2 0.1µF 2
SK3 R25 DIN
5 4 1 2 1 R1 2 2 VCC 8
1 1
TP10 GND 2 P1 DOUT
C25 C26 + 820Ω 7 1
R37 2
2 TP1 DOUT2 820Ω VO 13 P1
100nF 2 10µF
V1P 3 5 100Ω
TBLK02 1 R2 2 4 U6 GND
JP15 JP1 U3 6 +5V HCPL2211
1 2 1 2 TP11 10kΩ 5
7408 C36 SCLKIN
8
2 1 1 1
R26 2
JP2 SCLK VCC 5 P1
2 1 1 R41 2 1 R50 2 C50
1 820Ω
33nF 9 0.1µF
SH1A 100Ω 1kΩ 8 U3 1 R31 2 7 2
2 C11 7408 10 VO1 CSBIN
TP2 TP12 100Ω 1
R27 2
33nF 4 P1
JP4 V1N CSB U8
2 1 820Ω
1
JP25 JP3 12 HCPL2232
SH1B 1 2 1 2 11 U3 3
SK2 1
R30 2 6 18 P1
1 2 7408 13 VO2
2 1 R42 2 1 R51 2
C51 1 R4 2 100Ω 19 P1
33nF 1 U1 20
3 20 P1
TP14 TP13 100Ω 1kΩ 2 19 5 4
TP5 GND
TBLK03 AGND DGND C21 3 18 XTAL 21 P1
33nF V2N V1P 4 17 1 2 BNC1
JP11 22 P1
2 1 V1N 5 16 EXT_CLK
1 1
V2N 6 15 C14 C15 1 R6 2 23 P1
V2P 7 14 2 22pF 2 22pF 24 P1
8 13 100Ω 1 C23 +C24
1
R112 25 P1
JP10 JP9 9 12 0.1µF 10µF JP14
2
2 1 1 2 10 11 2 1
TP6 50Ω
ADE7753
IRQ JP5 SK5
SK1 1
1

Rev. 0 | Page 13 of 20
R15 2
1 1
R572 U2 3 1 2 1 1 VCC 8 VPLUS
1 R9 2 2
7408 820Ω VMINUS 2
2 1kΩ 3 4
C54 10kΩ
LED1
33nF 1 R392 2 7 TBLK02
TBLK02 DVDD 1 R19 2 1 2
VO1
EVALUATION BOARD SCHEMATIC (REV. D AND REV. E)

10kΩ +5V
TP4

Figure 16. Evaluation Board Schematic

JP8 JP7 TP7 2 1 820Ω LN21RPHL U7 IRQOUT
2 1 1 2 V2P 1 R22 2
SAG C16 220pF HCPL2232 10 P1
JP51 4 JP6 100Ω
1
1 2
R16 2 3 6
1 2 C6 + C5 U2 6 1
R53 2 1 R8 2 5 VO2
1 7408 820Ω
1 2 100nF 10µF 3 4
C53 10kΩ
499kΩ R56 1.0kΩ/1% LED2
33nF 1 R40 2 4 GND 5
2 DVDD SAGOUT
1 R18 2 1 2 1 R13 2
1 R54 2 10kΩ +5V 11 P1
TP8 820Ω LN21RPHL 100Ω
499kΩ
VX
12 JP19
AVDD U2 11 1 2 1 R20 2 1 8
1 R10 2 13 VCC
1 8 7408 3 820Ω
U4 10kΩ 4
2 7 JP13 LED3 VXOUT
3 6 2 1 2 7 1
R3 2
1 R212 2 1
VO1 12 P1
4 5 100Ω
1 AD780N +5V 820Ω
C8 + C7 TP9 LN21RPHL U9
2 100nF 10µF CF HCPL2232
9 JP12 R5 CFOUT
8 2 1 3 6
R17 2
U2 1 1 2
1 R7 2 10 VO2 15 P1
VCC 14 VCC 14 7408 3 4 820Ω 100Ω
1 C33 1
C34 10kΩ BNC2
LED4
U3 U2 4 5
2 0.1µF 2 0.1µF GND
7408 7408 R24 2 2
1 1
GND 7 GND 7
820Ω LN21RPHL
04728-0-016 VMINUS
EVAL-ADE7753EB
EVAL-ADE7753EB

PCB LAYOUT—COMPONENT PLACEMENT (REV. D)

Figure 17. PCB Layout—Component Placement

Rev. 0 | Page 14 of 20
 EVAL-ADE7753EB

PCB LAYOUT—COMPONENT SIDE (REV. D)

Figure 18. PCB Layout—Component Side

Rev. 0 | Page 15 of 20
EVAL-ADE7753EB

PCB LAYOUT—SOLDER SIDE (REV. D)

Figure 19. PCB Layout—Solder Side

Rev. 0 | Page 16 of 20
 EVAL-ADE7753EB

PCB LAYOUT—COMPONENT PLACEMENT (REV. E)

Figure 20. PCB Layout—Component Placement

Rev. 0 | Page 17 of 20
EVAL-ADE7753EB

PCB LAYOUT—COMPONENT SIDE (REV. E)

Figure 21. PCB Layout—Component Side

Rev. 0 | Page 18 of 20
 EVAL-ADE7753EB

PCB LAYOUT—SOLDER SIDE (REV. E)

Figure 22. PCB Layout—Solder Side

Rev. 0 | Page 19 of 20
EVAL-ADE7753EB

ORDERING GUIDE
Model Description
EVAL-ADE7753EB Evaluation Board

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D04728-0-4/04(0)

Rev. 0 | Page 20 of 20
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EVAL-ADE7753ZEB