Digital Logic Design
LECTURE 10: SEQUENTIAL LOGIC, LATCHES, FLIP FLOPS
After this class you should know
• Sequential Logic
• Types of sequential circuits
• Latches
• Flip Flops
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Combinational
Logic
Digital Logic
Sequential
Logic
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Digital Logic
Combinational Sequential
• Output at any instant of time • Output at any instant of time
depends only on input. depends on the previous values
• No memory units required as well along with the input.
• Faster • Memory units required.
• Easy design and analysis • Slower
• Parallel adder • Serial adder
• Examples: Full adder, • Examples: Flip flops, register,
Multiplexer, Decoder etc. counters
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Sequential Circuits
State of system is info stored
That, PLUS inputs, determine outputs
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Types of Sequential Circuits
Synchronous Asynchronous
• State changes synchronized • Changes occur
by one or more clocks independently
• Slower than asynchronous • Potentially faster
due to clock. • Harder Analysis and
• Easy Analysis and Design Design
• Change in input affects • Change in input signals
memory element upon affects memory elements at
activation of clock signal any instant of time.
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Latch: Basic Memory Storage Element
• A storage element in a digital circuit that can maintain a binary state indefinitely (as long as
power is delivered to the circuit), until directed by an input signal to switch states.
• Latch is the basic storage element (stores 1 bit) building block of flip flops.
• Storage elements that operate with signal levels are latches. (Level Sensitive)
•Storage elements that operate with clock transitions are flip flops. (Clock Sensitive)
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Latch Types
NOR
SR
Latches NAND
D
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SR (set-reset) Latches (NOR)
Basic storage made from gates
Evaluate 1 First •S & R both 0 in “resting” state
•Have to keep both from 1 at same time
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S R Latch (NAND)
Similar – made from NANDs
Evaluate 0 First
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Add Control Input
Is there latch w/ no illegal state?
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D-type Latch
No illegal state
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Standard Symbols – Latches
Circle at input indicates negation
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Flip-Flops
• Flip-Flops:
• Ensure output changes only once per clock cycle
• Two commonly-used types of flip-flops:
• Master-Slave
• Use a sequence of two latches
• Edge-Triggered
• Implementation very different from latches
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1. Master-Slave Flip-Flop
Either Master or Slave is enabled, not both
Store for a clock cycle.
Get what was stored in last cycle
Characteristic Equation
Q(t+1)=D Characteristic Table ?
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Edge-Triggered Flip-Flops
• New state latched on clock transition
• Low-to-high or high-to-low
• +ve edge-triggered, -ve edge-triggered
• Also: dual-edge-triggered
• Changes when clock high are ignored
• Note: Master-Slave sometimes called pulse triggered
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Clock Response
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Symbol for Edge Triggered D Flip Flop
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D Flip Flop Characteristic Table
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JK Flip Flop
Characteristic Equation
Q(t+1)=JQ’ +K’Q
J=1, K=0, D = Q’+Q=1
J=0, K=1, D =0
J=K=0, D=Q (Unchanged)
J=K=1, D=Q’ (Complement)
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T –Flip Flop
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Symbols – Master-Slave
Inverted ‘L’ indicates postponed output
Circle indicates whether enable is positive or negative
JK: like an SR flip-flop, but:
If J=K=1, output is toggled
Can make a toggle flip-flop (T flip-flop) from a JK
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Symbols – Edge-Triggered
Arrow indicates edge trigger
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Direct Inputs
• Use to force Set/Reset independent of clock
• Direct set or preset
• Direct reset or clear
• Often used for power-up reset
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