THREE LEVEL PWM DC-DC CONVERETR

USING SOFT SWITCHING FOR INDUSTRIAL

APPLICATIONS
M.Agnes Cansa Immaculate electrically isolating the input from the
Power Electronics and Drives/ PG Scholar output
Dr.Sivanthi Aditanar College of Engineering M.Bhuvaneshwari /Assistant Professor
[email protected] Department of Electrical and ElectronicsEngineering
Dr.Sivanthi Aditanar College of Engineering
Abstract - This project concentrates on wide range [email protected]
soft switching solutions to a pulse width
modulation (PWM) three-level (TL) dc–dc
Converter is well suited for industrial
applications, and proposes four kinds of new
PWM TL dc–dc converters. This topology have
the desirable features such as all switches in each
circuit sustain only half of the input voltage; off
state voltage of the switches are directly clamped
by the input capacitors and there is no primary
clamping devices, such as clamping diodes, flying
capacitors; and phase shifted control method is
used to achieve wide output range. The leading
switches in the converters can realize zero-voltage
switching (ZVS), while the lagging switches can
obtain ZVS or zero-current switching in all the
four converters. Analysis and verification of
converters can be done by MATLAB simulation.

Keywords—Industrial application, three-level dc–

dc converter, zero-current switching (ZCS), zero
voltage switching(ZVS).

INTRODUCTION
Fig. 1. Primary circuits of PWM dc–dc
New topology for high input voltage dc–dc converters. (a) Converter in paper [6]. (b)
power conversion is a hot researching issue in power Diode clamped ZVS ThreeLevel converter.
electronics because of much existing potential (c) Two-level PS FB converter.
demand, i.e., the second stage dc–dc converter after
the 3Φ power factor correction (PFC) circuit, dc–dc for safety and load voltage matching.
converters for grid, renewable energy, and distributed In the paper [6], a new PWM TL dc–
dc converter was proposed, which
power system. The present invention generally
features Vin /2 on each switch, capacitive
concerns power conversion, and particularly concerns turn-off, and zero-voltage turned on. Fig. 1
a fixed frequency DC to DC power converter shows the primary circuits of the
operating with zero voltage switching and zero converter in [6], diode clamped ZVS TL
current switching (turn-on and turn-off) from a no dc–dc converter, and two-level FB dc–dc
load operation to a full load operation while converter. As shown in Fig. 1(a), only one
more wire between the midpoint of the
input capacitors and switching pairs is interesting and valuable task to find wide range soft
required to fabricate TL structure. switching solutions to this converter.
The input voltage of these dc–dc converters
may be higher to achieve better system performance. II.WIDE RANGE SOFT SWITCHING PWM TL
Implementing soft switching in DC-DC converter CONVERTERS
helps in reducing switching losses. Phase shifted Proposed methodologies consist of four TL
control technique can be used to achieve wide output PWM DC-DC converters. Each converter is designed
range. The leading switches in converters realize with Commutation Auxiliary Circuit which consists
zero-voltage switching, while the lagging switches of NLC snubber circuit and a bidirectional switch and
can obtain ZVS or zero-current switching in different it provides ZVS and ZCS to the proposed converters.
converters. The controller adjusts the output of the
power converter by varying the switching frequency A. ZVS TL PWM Converter With One CAC Per
or duty cycle (i.e., pulse width modulation) of the Module
control signals applied to the switches. Switching
transitions occurs under favorable conditions device As shown in fig.2.,ZVS PWM TL converter
voltage or current is zero. Soft switching results in with one CAC per module is composed of two dc–dc
reduced switching losses, switch stress, low EMI, modules with similar structure. The second module is
easier thermal management. Soft switching power introduced to balance the dc link voltage. Each
converters overcome the requirement for higher peak module consists of four switches, one high frequency
currents by utilizing pre-dominantly square switching transformer, and one blocking capacitor. Cin1 to
waveform with resonant transitions. These power Cin4 are common dc link capacitors with equal
converters are characterised by intrinsic modes of values and large enough to share the input voltage
operation which allow an automatic, lossless resetting evenly, i.e., VCin1 = VCin2 =VCin3 = VCin4 =
of snubber circiuts by appropriately recirculating Vin /4. L1 and L2 are CAC inductances to extend
stored energy. The energy can be stored by the ZVS load range for the lagging switches. Llk1 and
snubber elements or any other parasitic elements, Llk2 are the leakage inductances of T1 and T2. Full
such as the leakage inductance or inter winding wave rectifier are adopted in the topology, and D01–
capacitance of the power transformer or the stored D04 are rectifier diodes. During the operation, all the
energy in any of the semiconductor devices. A ZVS eight switches can be divided into four switching
soft switching converter will use capacitive snubbers pairs, i.e., S1 and S2, S3 and S4, S5 and S6, S7 and
while a ZCS soft switching converter will use S8. The switches in each switching pair were
inductive snubbers. operated in complementary mode. S4 and S5 are
In many industrial applications, it is required switched simultaneously to balance the voltage of all
to convert fixed –voltage dc source into variable- input capacitors, while S3 and S6 are switched
voltage dc source. A dc-dc conveter converts dc to simultaneously. The two CACs can supply more
dc. Since it has many advantages researchers have energy to assist ZVS of S3, S4, S5, and S6. V01 is
done many researches on this dc –dc converter. New regulated by the phase angle between S1 and S4, and
topology for high input voltage dc–dc power Vo2 is regulated by the phase angle between S5 and
conversion is one of the hot researching issue in S8. Thus, the two dc-dc modules can supplyt either
power electronic because of much existing or single load or two independent loads.
potential demand, that is the second stage dc–dc
converter after the 3Φ power factor correction (PFC) B.ZVS TL PWM Converters With Two CACs Per
circuit, dc to dc converters for micro grid, renewable Module
energy, and also distributed power system[1]-[4].
Commonly, the input voltage of these dc to dc As shown if fig.3,.ZVS TL PWM converter
converters may be 800 V or higher to achieve good with two CACs per module. This converter is
system performance[1]. Although, 1700V or higher consists of four switches, one high frequency
voltage rating commercial IGBTs are available in transformer, and one dc-blocking capacitor. Cin1 −
now-a-days, their performance under high frequency Cin4 are common dc link capacitors with equal value
operation are worse than 1200V or 600V IGBTs. and large enough to share the input voltage evenly,
Therefore, it is still a hard job to select suitable power i.e.,VCin1 = VCin2 =VCin3 = VCin4 = Vin /4. L1
modules for high input voltage dc–dc converter[5]- and L2 are CAC inductances to extend ZVS load
[6]. However, it is also pointed out in that the soft range for the leading and also for lagging switches.
switching characteristic for the lagging switches is Llk is the leakage inductance. Fullwave rectifier is
worse than the leading switches especially under adopted in the topology, and Do1and Do2 are
small load current condition. Therefore, it is still an
rectifier diodes. With proper switching sequence, all D.ZVZCS TL PWM Converter With One CAC per
the switches can achieve ZVS even down to no load. Module.

C. ZVS TL PWM Converter With Two CACs per Fig.5., shows a kind of ZVZCS with one CAC
Module per module, and it is a combination of the converter
in Figs 2 and 4. The leading switches can obtain ZVS
As illustrated in Fig 4., it is composed of the with wide load range after introducing the CACs,
switches S1–S4 , cutoff diodes D3 and D4, frequency while ZCS technology is applied to lagging switches.

Fig 2. ZVS TL PWM converter with one CAC per Fig 4. ZVZCS type TL PWM converter
module

Fig 3. ZVS TL PWM with two CACs per module Fig 5. ZVZCS TL PWM converter with one CAC
per module
transformer T1, dc-blocking capacitor CBL. CBL is Like Fig. 2, Vo1 and Vo2 can power either single
capable of sustaining the average voltage of V in/2 load or two independent loads. The modes of
during the entire operation stages and the voltage operation of this circuit will be same as that of the
ripple of this blocking capacitor is designed to a ZVS TL PWM with one CAC per module. It is
specified value to assist ZCS of lagging switches. shown in figure 3.
Cin1 and Cin2 are dc link capacitors with same value
and large enough to share the input voltage equally, III. PRINCIPLE OF OPERATION
i.e.,VCin1 = VCin2 = Vin topology, and Do1 and Do2 are
rectifier diodes.The output of filter is L o and Co and The operating principle of the converter in fig.2 and 4
Ro is the load resistance. The modes of operation is discussed as an example in this part. Before
of this circuit will be sam as that of the built ZVS TL analysis, some assumptions must be done to clarify
PWM with two CAC per module. It is shown in the explanation: all the components in the four
figure 4. converters are ideal; the voltage ripple on the dc link
capacitors can be neglected; the voltage ripple of
blocking capacitors of the converter in fig.2 can be discharges C2 linearly with time. This stage continues
neglected, while the voltage ripple of such blocking until VC2 equals to zero, and VC1 increases to Vin /2.
capacitor of the converter in fig.4 is designed to some The voltage of point F is
specified value to reset the primary voltage; output Io1
filter and load is instead by constant current source; VF (t) = Vin − t
L1 equals L2 and is represented by LCAC in the 2kT1Cos
following deduced equations; the output capcitance The time of this period is given by
of each switch is with the value and represented by
COS in the following deducted equations. kT1VinCos
T10 =
Io1
When the Vrect1 decays to zero, T1 will be operated in
the free-wheeling mode. iL1 and iL2 keep increasing.
MODE 3: At instant t1,D2 is conducted naturally.S4,
S5 , and S8 are kept ON. T1 is operated in the free
wheeling mode, and T2 powers load through D03 .
D01,D02 , and D03 are conducted, while Do4 is OFF;
vrect1 = 0, vrect2 = Vin /2kT2 .During this stage, S2 must
be turned ON to obtain ZVS. According to Table 1.,
S2 is turned ON at instant t4. S1 and S6 are clamped by
Cin1 and Cin2 , while S3 and S7 are clamped by Cin3 and
Cin4.
MODE 4:At instant t2, S8 is turned OFF at zero
voltage due to the existence of C 8. iT2p charges C8 and
discharges C7 linearly with time. This stage ends until
vC8 equals to Vin /2, and vC7 decays to zero. The
voltage of point K can be represented by
Io2
VK (t) =
2kT 2Cos
The time of this period can be given by
Fig.6. Waveform of the ZVS PWM TL converters kT2VinCos
with one CAC per module. T23 =
Io2
When the vrect2 decays to zero, T2 will be operated in
A. ZVS PWM TL Converter With One CAC Per the free-wheeling mode.
Module MODE 5:At instant t3,D7 is conducted naturally. S4
and S5 are kept ON. T1 and T2 stay in the free-
MODE 1 : Before t0 , the circuit is operated in a wheeling mode. iT1p flows through Cin3, Cin4, S4,D2,
steady state and power is transferred from the input CBL1, T1 ; iT2p flows through Cin1, Cin2, S5,D7, CBL2, T2 ;
source through T1 and T2 to the loads. S1, S4, S5 , Vrect1 = Vrect2 = 0. During this stage, S7 must be turned
and S8 are turned ON; Do1 and Do3 are conducted, ON to obtain ZVS. According to Table 1.,S 7 is turned
while Do2 and Do4 are off; VGH =VJK =Vin/2; ON at instant t5. S1 and S6 are clamped by Cin1 and
Vrect1 =Vin /2kT1 , and Vrect2 =Vin /2kT 2 ; iT1p Cin2 , while S3 and S8 are clamped by Cin3 and
=Io1 /kT 1, iT2p = Io2 /kT2. S2 and S6 are directly Cin4 .
clamped by Cin1 and Cin2 , while S3 and S7 are MODE 6: At t6, S4 and S5 are turned OFF at zero
directly clamped by Cin3and Cin4 . iL1 and iL2 voltage due to the existence of C4 and C5 ; iL1 and
increase with time linearly; the slope of the currents iT2p charge C5 and discharge C6 linearly with time; iL2
is determined by and iT1p charge C3 and discharge C4 linearly with
time. iL1 and iL2 reach their maximum value and keep
diL1 diL2 Vin Vin this value during the stage. Thanks to the energy
= = = stored in L1 and L2,S3 and S6 can achieve ZVS. The
dt dt 2(L1 +L2) 4LCAC peak value of iL1 and iL2 is given by
MODE 2:At the instant t0, S1 is turned OFF at zero- VinTs
voltage due to the existence of C1. iT1p charges C1 and IL1 max = IL2 max =
16LCAC
MODES 7:At t8,D3 and D6 are transferred to the ON turned ON to ensure ZVS. According to Table 1.,S 3
status naturally. The circuit keeps in the free- and S6 are turned ON at t9. S1 and S5 are.
wheeling mode,iT1p, iT2p, iL1 , and iL2 decay due to
negative voltage applied to the terminals of Llk1, Llk2,
L1 , and L2 . During this stage, S3and S6 must be

Fig.7.Modes of operation ZVS PWM TL are over. Power is transferred from the input source
converters with one CAC per module to the load continually. VGH = VJK = −Vin /2;
Vrect1 = −Vin /2kT1 , and Vrect2 = −Vin /2kT2 ;
clamped by Cin1 and Cin2 , while S4 and S8 are
clamped by Cin3 and Cin4
MODE 8:At instant t9, S3 and S6 are gated ON. S2
and S7 have been turned ON. The primary currents of iT1p = −Io1 /kT1, iT2p = −Io2 /kT2 . iL1 and iL2
the transformers increase in the inverse direction, increase linearly in the reverse direction with time;
after these currents reach to −Io1 /kT1 and −Io2 /kT2 the slope of the currents is given by
respectively; the freewheeling modes of T1 and T2
 diL1 diL2 − Vin value VCBLP at the end of this stage; ip keeps constant
= = value of Io/kT during this intervals, and charges C1
dt dt 4LCAC and discharges C2 linearly with time. This stage
continues until VC1 equals to Vin /2 and VC2 decays to
zero. The voltage of point A is given by
Io
VA(t) = Vin − (t − t0 )
2kT Cos
TABLE 1 At instant t1, VA deceases to Vin /2 and the time of
OFF VOLTAGE OF THE SWITCHES OF THE this interval is
ZVS PWM TL CONVERTERS WITH ONE CAC kT CosVin
PER MODULE T10 =
Io
MODE 3:At instant t1,D2 is conducted naturally; the
circuit is operated in the freewheeling mode; both of
the rectifier diodes are conducted; During this stage,
S2 must be gated ON to achieve ZVS, and according
to Table 2., S2 is turned ON at instant t2 ; Vrect = 0.
The voltage of CBL can be a constant voltage source
represented as VCBLP during this stage and it is fully
applied to Llk to reset the primary side current. The
expression of ip in this stage can be given by
Io VCBLP − Vin/2
ip (t) = − (t − t1 )
kT Llk
The switches in the converter shown in figure can be This stage ends until ip decays to zero, and the time
turned ON and turned OFF according to the of this stage is
table1.The switches are operated and so the operating IoLlk
modes of the converter are shown in fig 4.2. The T31 =
switches are operated in such a way that this kT (VCBLP − Vin/2)
converter operating with one CAC per module can
be used for dual application. MODE 4:At instant t3, ip decays to zero. Due to the
existence of D4 , the primary current cannot be
B. ZVZCS TL PWM Converter conducted in the reverse direction. After the instant
of t3, ip keeps the value zero, so S4 can achieve ZCS
Fig.8., shows the six switching stages turned OFF. The voltage of CBL keeps constant.
of the converter in Fig.4 during the first MODE 5:At instant t4, S3 is gated ON, and S 3 can
half switching cycle, and the achieve ZCS turned ON due to the existence of the
corresponding keywaves are depicted in Llk; S2 has been turned ON at instant t 2 ; ip increases
Fig.9. linearly with time in the reverse direction, and the
circuits is still in the free-wheeling modes until ip
MODE1:Before t0 , the circuit operates in the steady reaches to −Io /kT . ip in this stage is given by
condition and power is transferred from input source −VCBL
to the load. S1 and S4 are turned ON; Do1 is ip (t) = (t − t4 )
conducted while Do2 is OFF; the voltage of CBL Llk
increases linearly with time, and the slope of VCBL MODE 6:At instant t5, ip reaches to −Io /kT ;
is given by thefree-wheeling mode is over. Primary powers the
dvCBL Io load from the energy stored in CBL through S2,D3,
= S3 , the transformer, and output rectifier and filter.
dt kTCBL VBC = −VCBL; Vrect = VCBL/kT ; ip = −Io /kT .
During this stage, VBC = Vin−VCBL; From stage 6, the circuit is operated in the second half
Vrect = (Vin−VCBL)/kT ; and ip = Io /kT . period. As illustrated in Table 2.,voltage across
MODE 2: At instant t0, S1 is turned OFF at zero the switches is not larger than Vin /2 at each
voltage due to the existence of C1 ;VCBL keeps operation state.
increasing during this stage, and reaches its peak
IV.SWITCHING TECHNIQUE OF PROPOSED When a switch is gated to OFF, the current flowing
CONVERTERS through this switch is transferred to the parallel
A. ZVS for the Leading Switches
1) Turn-Off Intervals:
Due to the existing output capacitance
or the leading switches can be achieved zero turn-off.

connected capacitor. As the voltage of the capacitors

Fig. 8. Modes of operation of ZVZCS TL PWM cannot be changed suddenly, its voltage rises
converter progressively until the final voltage. Thus, the cross-
TABLE 2. production of the voltage and current in the switch is
OFF VOLTAGE OF THE SWITCHES OF THE intervals can be reduced.
ZVZCS PWM TL CONVERTERS

2) Turn-On Intervals Without CAC:

During this commutation instant, the output
inductance together with leakage inductance of the
transformer charges or discharges related intrinsic
capacitance of leading switches, and energy is large
enough to drive the anti-parallel diode to conduct
even at the light load. So, leading switches can be
always turned ON at zero voltage. In order to achieve
higher light load efficiency, larger CAC inductors’
current is preferred, but the full load efficiency will
decrease due to added conduction loss. Thus, the
value of LCAC should be designed as a tradeoff
between light load efficiency and full load efficiency. B.ZVS TL PWM With two CAC Per Module

B.ZVS for the Lagging Switches With CAC Fig.13.shows the simulated result for ZVS TL
The turn-off conditions of the lagging PWM with two CAC per module features wide ZVS
switches are quite similar with leading switches, and load range for either leading switches or lagging
thanks to the parallel-connected capacitor, the voltage switches and only one module is required during the
across the switch is not increasing sharply. Therefore, operation. As the tailing current of IGBTs is a serious
the turn-off losses can be significantly reduced. As problem during the operation, ZVZCS is more
CAC is added into the circuit, the lagging switches suitable for applications with IGBTs.
can obtain ZVS even with no load current.
C.ZVZCS TL PWM Converter
C.ZCS FOR THE LAGGING SWITCHES
1) Turn-Off Intervals:
The lagging switches should be turned OFF
after ip decays to zero. When IGBTs are used as
lagging switches, the minority carriers in the
component can be combined within a specific time,
and this interval is determined by the component
itself .

2) Turn-On Intervals:
Due to the existed leakage inductance, the
switch can be achieved zero-current turn-on. When a
switch is gated ON, the current flowing through this
switch cannot be changed suddenly, and its value
rises progressively until the final current. Thus, the
cross-production of the voltage and current in the Fig.13.Simulated output for ZVS TL PWM with two
switch is decreased and the losses during the turned CAC per modulE
on intervals can be reduced.
Fig.14 shows the simulated result of ZVZCS
V.SIMUALTION RESULTS TL PWM converter. ZVZCS is more suitable for
applications with IGBTs. In order to minimize the
A.ZVS TL PWM with one CAC per module switching loss of the leading switches in ZVZCS
Figure.11. shows the simulation results for converters,
ZVS TL PWM with one CAC per module. Each
module gives the output at certain level according to
the input given this circuit can be used for dual
applications. The output of this circuit is
comparatively higher than the other proposed
converters.

Fig.14.Simulated output for ZVZCS TL PWM

Fig.12. simulated output for ZVS TL PWM with one converter
CAC per module
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