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SystemVerilog Advanced Interview Questions Handbook

The document is a handbook containing over 50 advanced interview questions focused on SystemVerilog for VLSI and verification engineers. It provides code-focused questions along with complete solutions, making it suitable for both freshers and experienced professionals preparing for VLSI job interviews. Key examples include constraints for random variables and packet classes demonstrating practical applications of SystemVerilog concepts.

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sharanunewgowdru
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100 views3 pages

SystemVerilog Advanced Interview Questions Handbook

The document is a handbook containing over 50 advanced interview questions focused on SystemVerilog for VLSI and verification engineers. It provides code-focused questions along with complete solutions, making it suitable for both freshers and experienced professionals preparing for VLSI job interviews. Key examples include constraints for random variables and packet classes demonstrating practical applications of SystemVerilog concepts.

Uploaded by

sharanunewgowdru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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SYSTEMVERILOG

ADVANCED INTERVIEW
QUESTIONS HANDBOOK
Code-Focused Questions with Complete
Solutions for VLSI & Verification Engineers

50+ advanced interview-ready


questions
Ideal for VLSI Enthusiasts,
Freshers, Experienced VLSI
Engineers & VLSI job interviews
Q1. Write a constraint where a 4-bit variable should
never take the values between 4 to 9.
class Test;
rand bit [3:0] data;
constraint c1 {
!(data inside {[4:9]});
}
endclass

module tb;
Test t = new();
initial begin
repeat(10) begin
void'([Link]());
$display("data = %0d", [Link]);
end
end
endmodule

Q2. Constrain an array of 5 integers such that sum


should be 50 and each element should be unique.
class Test;
rand int arr[5];
constraint c_sum {
foreach (arr[i]) arr[i] inside {[1:20]};
[Link]() == 50;
unique {arr};
}
endclass
module tb;
Test t = new();
initial begin
if ([Link]())
$display("arr = %p", [Link]);
else
$display("Randomization failed!");
end
endmodule

Q3. Write constraints for a packet class with length


between 64 to 1500, and the payload size equal to
length - 20.
class Packet;
rand int length;
rand int payload;
constraint c_range {
length inside {[64:1500]};
payload == length - 20;
}
endclass

module tb;
Packet p = new();
initial begin
if ([Link]())
$display("Length = %0d, Payload = %0d",
[Link], [Link]);
end
endmodule

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