CMOS Digital Integrated Circuits
Chapter 5
MOS Inverters:
Static Characteristics
Y. Leblebici
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Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.
Ideal Inverter
Voltage Transfer
Characteristic (VTC)
of the ideal inverter
1
Generic Inverter VTC
Voltage Transfer
Characteristic (VTC)
of a typical inverter
Noise Margins
Propagation of digital signals under the influence of noise
VOH : VOUT,MAX when the output level is logic "1“
VOL : VOUT,MIN when the output level is logic "0“
VIL : VIN,MAX which can be interpreted as logic "0“
VIH : VIN,MIN which can be interpreted as logic "1"
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Noise Margins
Definition of
noise margins
Noise Margins
3
Noise Margins
Nominal output
Output under noise
The nominal operating region is defined as the region where the gain is less than unity !
CMOS Inverter Circuit
4
CMOS Inverter Circuit
The NMOS switch transmits the logic 0 level to the output, while the PMOS switch
transmits the logic 1 level to the output, depending on the input signal polarity.
CMOS Inverter Circuit
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5
CMOS Inverter Circuit
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CMOS Inverter Circuit
determine
noise
margins
inversion (switching)
threshold voltage
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6
CMOS Inverter Circuit
nMOS transistor current-voltage characteristics
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CMOS Inverter Circuit
pMOS transistor current-voltage characteristics
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7
CMOS Inverter Circuit
Intersection of current-voltage surfaces of nMOS and pMOS transistors
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CMOS Inverter Circuit
Intersection of current-voltage surfaces gives the VTC in the voltage plane
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8
CMOS Inverter Circuit
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CMOS Inverter Circuit
How to choose the kR ratio to achieve a desired inversion threshold voltage:
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9
CMOS Inverter Circuit
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Supply Voltage Scaling
VTC of a CMOS inverter
for different power supply
voltage values.
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10
Dynamic Characteristics
of CMOS Inverter
VDD
charge-down
(W/L)p
(W/L)n
load
capacitance
Switching speed determined
by the time required to
charge-up or charge-down charge-up
the output load capacitance.
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Definition of Delay Times
The propagation delay times
are defined as the time delay
between the 50% crossing of
the input and the
corresponding 50% crossing of
the output.
The rise time and the fall time
of the output signal are defined
as the time required for the
voltage to change from its 10%
level to its 90% level (or vice
versa).
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11
Calculation of Propagation Delays
The falling output propagation delay is
determined by the NMOS transistor, which
starts pulling down the output node first in
saturation, and later, in linear mode.
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Calculation of Propagation Delays
The rising output propagation delay is
determined by the PMOS transistor, which
starts pulling up the output node first in
saturation, and later, in linear mode.
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Calculation of Propagation Delays
The time required by the NMOS transistor in saturation and in linear region
can be calculated separately.
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Calculation of Propagation Delays
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Calculation of Propagation Delays
The time required by the PMOS transistor in saturation and in linear region
can be calculated separately.
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Calculation of Propagation Delays
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Calculation of Propagation Delays
Summary:
The propagation delay times are proportional to the load capacitance,
and inversely proportional to the pull-up (or pull-down) transconductance.
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Influence of Nonzero Input Rise/Fall Time
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Components of the Output Load Capacitance
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Increasing the Switching Speed
• Need to increase the amount of charge-up and
charge-down current that switches the output.
• Increase the transistor (W/L) ratios both in the
pull-up path and in the pull-down path.
• However: increasing transistor dimensions will
influence the parasitic MOSFET capacitances.
• The switching speed of a classical CMOS gate
is ultimately limited by its intrinsic delay.
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Drain parasitics are mainly
responsible for the intrinsic
gate delay.
A closer look at the typical CMOS inverter
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Parasitic Capacitance Components
Drain parasitics:
Total capacitive load:
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17
Parasitic Capacitance Components
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Propagation Delays
rising input
falling output
falling input
rising output
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Propagation Delays
rising input
falling output
falling input
rising output
Notice that with increasing transistor width Wn
and Wp, both delays asymptotically approach
fixed limit values, independent of external
loads.
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Propagation Delays
Intrinsic delay limits will decrease for
• Smaller gate length L
• Larger µ and Cox
But for a given technology, the limits are fixed.
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Improving propagation delay times by transistor sizing
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Improving propagation delay times by transistor sizing
Delay
large gate delays
fanout ultimately
load converge to
limit value for
large W/L !
intrinsic delay
limit value
small Channel Width
fanout
load
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20
CMOS Inverter Layout
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CMOS Inverter Layout
Mask layout
of the inverter
Simplified
cross-section
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