Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolic

The Devices
July 30, 2002

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EE141 Integrated Circuits2nd Devices
 Goal of this chapter
‰ Present intuitive understanding of device
operation
‰ Introduction of basic device equations
‰ Introduction of models for manual
analysis
‰ Introduction of models for SPICE
simulation
‰ Analysis of secondary and deep-sub-
micron effects
‰ Future trends

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 The Diode
B Al A
SiO2

Cross-section of pn-junction in an IC process

A Al
p A

B B
One-dimensional
representation diode symbol

Mostly occurring as parasitic element in Digital ICs

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 Depletion Region
hole diffusion
electron diffusion
(a) Current flow.
p n

hole drift
electron drift
Charge ρ
Density
+ x (b) Charge density.
Distance
-

Electrical ξ
Field x
(c) Electric field.

V
Potential
ψ0 (d) Electrostatic
x potential.
-W 1 W2

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 Diode Current

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 Forward Bias

pn (W2)
pn0

Lp

np0

-W1 0 W2 x
p-region n-region

diffusion

Typically avoided in Digital ICs

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 Reverse Bias

pn0

np0

-W1 0 W2 x
p-region n-region

diffusion

The Dominant Operation Mode

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 Models for Manual Analysis

ID = IS(eV D/φT – 1) ID
+ +
+
VD VD VDon
–
– –

(a) Ideal diode model (b) First-order diode model

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 Junction Capacitance

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 Diffusion Capacitance

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 Secondary Effects
0.1

ID (A)

–0.1
–25.0 –15.0 –5.0 0 5.0
VD (V)

Avalanche Breakdown

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 Diode Model

RS

VD ID CD

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 SPICE Parameters

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 What is a Transistor?

A Switch! An MOS Transistor

VGS ≥ VT |VGS|

Ron
S D

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 The MOS Transistor

Polysilicon Aluminum

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MOS Transistors -
Types and Symbols
D D

G G

S S

NMOS Enhancement NMOS Depletion

D D

G G B

S S

PMOS Enhancement NMOS with

Bulk Contact

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Threshold Voltage: Concept
+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

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The Threshold Voltage

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 The Body Effect
0.9

0.85

0.8

0.75

0.7
V (V)

0.65
T

0.6

0.55

0.5

0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
V (V)
BS

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 Current-Voltage Relations
A good ol’ transistor
-4
x 10
6
VGS= 2.5 V

Resistive Saturation
4
VGS= 2.0 V
ID (A)

3 Quadratic
VDS = VGS - VT Relationship
2
VGS= 1.5 V

1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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Transistor in Linear

VGS VDS
S
G ID
D

n+ –
V(x)
+ n+

L x

p-substrate

MOS transistor and its bias conditions

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Transistor in Saturation
VGS

VDS > VGS - VT

G

D
S

- +
n+ VGS - VT n+

Pinch-off

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Current-Voltage Relations
Long-Channel Device

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A model for manual analysis

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 Current-Voltage Relations
The Deep-Submicron Era
-4
x 10
2.5

VGS= 2.5 V
Early Saturation
2

VGS= 2.0 V
1.5
ID (A)

Linear
1
VGS= 1.5 V Relationship

0.5 VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)

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 Velocity Saturation
υ n (m/s)

υsat = 105
Constant velocity

Constant mobility (slope = µ)

ξc = 1.5 ξ (V/µm)
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 Perspective

ID
Long-channel device

VGS = VDD
Short-channel device

V DSAT VGS - V T VDS

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 ID versus VGS
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1
quadratic
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

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 ID versus VDS

-4 -4
x 10 x 10
6 2.5
VGS= 2.5 V
VGS= 2.5 V
5
2
Resistive Saturation
4 VGS= 2.0 V
VGS= 2.0 V 1.5

ID (A)
ID (A)

3
VDS = VGS - VT 1 VGS= 1.5 V
2
VGS= 1.5 V
0.5 VGS= 1.0 V
1
VGS= 1.0 V
0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VDS(V) VDS(V)

Long Channel Short Channel

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A unified model
for manual analysis

S D

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 Simple Model versus SPICE
-4
x 10
2.5

VDS=VDSAT
2

Velocity
1.5
Saturated
ID (A)

Linear
1

VDSAT=VGT
0.5

VDS=VGT
Saturated
0
0 0.5 1 1.5 2 2.5
VDS (V)
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 A PMOS Transistor Assume all variables
negative!
-4
x 10
0
VGS = -1.0V

-0.2
VGS = -1.5V

-0.4
ID (A)

VGS = -2.0V
-0.6

-0.8
VGS = -2.5V

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)

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 Transistor Model
for Manual Analysis

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 The Transistor as a Switch
VGS ≥ VT
Ron ID
V GS = VD D
S D
Rmid

R0

V DS
VDD/2 VDD

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 The Transistor as a Switch
5
x 10
7

5
(O hm )

4
eq

3
R

0
0.5 1 1.5 2 2.5
V (V)
DD

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 The Transistor as a Switch

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The Sub-Micron MOS Transistor
‰ Threshold Variations
‰ Subthreshold Conduction
‰ Parasitic Resistances

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 Threshold Variations

VT VT

Long-channel threshold Low VDS threshold

VDS
L

Threshold as a function of Drain-induced barrier lowering

the length (for low VDS) (for low L)

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 Sub-Threshold Conduction

The Slope Factor

-2
10

Linear qVGS
CD
I D ~ I 0e nkT
, n = 1+
-4
10
Cox
-6
10 Quadratic
S is ∆VGS for ID2/ID1 =10
ID (A)

-8
10

-10 Exponential
10

-12
VT Typical values for S:
10
0 0.5 1 1.5 2 2.5 60 .. 100 mV/decade
VGS (V)

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 Sub-Threshold ID vs VGS
qVGS
 qV
− DS 
I D = I 0e nkT 1 − e kT 
 
 

VDS from 0 to 0.5V

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 Sub-Threshold ID vs VDS
qVGS
 qV
− DS 
I D = I 0e nkT 1 − e kT (1 + λ ⋅VDS )
 
 

VGS from 0 to 0.3V

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 Summary of MOSFET Operating
Regions
‰ Strong Inversion VGS > VT
ƒ Linear (Resistive) VDS < VDSAT
ƒ Saturated (Constant Current) VDS ≥ VDSAT
‰ Weak Inversion (Sub-Threshold) VGS ≤ VT
ƒ Exponential in VGS with linear VDS dependence

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 Parasitic Resistances

Polysilicon gate
Drain
contact
G LD

VGS,eff

W
S D

RS RD

Drain

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 Latch-up

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 Future Perspectives

25 nm FINFET MOS transistor

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