Dr.

Mahalingam College of Engineering and Technology, Pollachi

(An Autonomous Institution Affiliated to Anna University, Chennai)

Department of
Electronics Engineering (VLSI Design and Technology)

Record Note Book

23EVL301 – ANALOG ELECTRONICS LABORATORY

Dr. Mahalingam College of Engineering and Technology, Pollachi
Record Note Book
23EVL301 – ANALOG ELECTRONICS LABORATORY
INDEX
 Course Code: 23EVL301 Course Title: Analog Electronics Laboratory

Course Category: Major Course Level: Intermediate

L: T:P (Hours/Week) 0:0:3 Credits:1.5 Total Contact Hours:45 Max Marks:100

Course Objectives:

The course is intended to impart knowledge on design and analysis of amplifier and oscillator circuits with
using BJTs and MOSFETs.

List of Experiments: 45 Hours

1. Design and Biasing of BJT using DC Load Line Analysis

2. DC Biasing and Stability Analysis of MOSFET Amplifier
3. Small Signal Analysis of Common Emitter Amplifier
4. Small Signal Analysis of Common Source MOSFET Amplifier
5. Analysis of Feedback Amplifier Using Negative Feedback Topologies
6. Frequency Response of Single Stage BJT Amplifier
7. Frequency Response of Single Stage MOSFET Amplifier
8. Design and Analysis of Differential Amplifier (BJT or MOSFET)

9. Design and Analysis of Cascode Amplifier using BJT

10. Design and Analysis of Source Follower / Common Collector Buffer Amplifier

Course Outcomes
Cognitive Level
At the end of this course, students will be able to:
CO1: Analyze the biasing techniques and small-signal behaviour of BJT and Analyze
MOSFET amplifier circuits through practical implementation and
performance evaluation.

CO2: Design and evaluate single-stage and multistage amplifier Analyze

configurations, including differential, feedback, and Cascode amplifiers, for
desired gain, bandwidth, and stability.
 Course Articulation Matrix

CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2

CO1 - 3 - - - - - - 1 1 1 1 1 1

CO2 - - 3 - - - - - 1 1 1 1 1 1

High-3; Medium-2; Low-1

Reference Book:
R1. Laboratory Manual Prepared by Faculty of EE(VLSI) Dr. Mahalingam College of Engineering and
Technology
External Assessment: (100 Marks)
CRITERIA MARKS
Aim 10
Theory/Procedure 20
Schematic Diagram/ Calculation 40
Output 20
Viva 10
Total 100
* The external mark will be scaled down to 25 marks
Assessment Pattern
 EXP. NO. :01 DESIGN AND BIASING OF BJT USING DC LOAD LINE ANALYSIS
DATE:

AIM

To design a Biasing of BJT using DC Load Line Analysis.

APPARATUS REQUIRED

Components Value Quantity

Transistor BC547 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 A single-stage amplifier uses one BJT (Common Emitter configuration).

 It converts small AC input into a larger AC output.
 DC analysis involves finding the operating point (Q-point): VCE , IC using KVL.
 Biasing ensures transistor stays in active region for faithful amplification.

CIRCUIT DIAGRAM
OUTPUT CHARACTERISTICS

TABULATION

IB=20 µA IB=40 µA IB=60 µA

S.No
VCE(V) Ic(mA) VCE(V) Ic(mA) VCE(V) Ic(mA)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

 EXP. NO. :02 DC BIASING AND STABILITY ANALYSIS OF MOSFET AMPLIFIER
DATE:

AIM

To design a DC Biasing and Stability Analysis of MOSFET Amplifier

APPARATUS REQUIRED

Components Value Quantity

Transistor BC547 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Without bypass capacitor, the emitter resistor introduces negative feedback.

 This stabilizes the amplifier but reduces AC gain.
 Transient analysis shows how output responds over time.
 Gain is calculated Formula

Av =

CIRCUIT DIAGRAM
MODEL GRAPH

TABULATION

S.NO Gate Source voltage (VGS) Drain Current (ID)

CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

 EXP. NO. :03 SMALL SIGNAL ANALYSIS OF COMMON EMITTER AMPLIFIER
DATE:

AIM
To perform small signal analysis of a Common Emitter (CE) amplifier and calculate voltage gain, input and
output resistance.
APPARATUS REQUIRED

Components Value Quantity

Transistor BC547 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 2
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY
 Bias the transistor using voltage divider.
 Apply small AC input signal (~10 mV peak) through coupling capacitor.
 Measure input/output voltage using CRO.
 Calculate gain
Av =
 Sketch equivalent small signal model.
CIRCUIT DIAGRAM
MODEL GRAPH

TABULATION

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛

(𝑉𝑜𝑢𝑡)
CALCULTION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

 EXP. NO. :04 SMALL SIGNAL ANALYSIS OF COMMON SOURCE MOSFET AMPLIFIER
DATE:

AIM

To analyze a Common Source (CS) MOSFET amplifier using small signal model and determine its gain.

APPARATUS REQUIRED

Components Value Quantity

N – channel MOSFET IEF740 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Use MOSFET with proper gate biasing using resistors.

 Apply small AC input through coupling capacitor.
 Measure input and output voltages.
 Use small signal model to derive

𝐴v =

 Compare practical and theoretical gain.

Circuit Diagram:
MODEL GRAPH

TABULATION

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛

(𝑉𝑜𝑢𝑡)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

 EXP. NO. :05 ANALYSIS OF FEEDBACK AMPLIFIER USING NEGATIVE FEEDBACK
DATE: TOPOLOGIES

AIM

To study the effect of negative feedback on gain, input/output resistance, and bandwidth in a BJT amplifier.

APPARATUS REQUIRED

Components Value Quantity

N – channel MOSFET IEF740 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Construct CE amplifier.
 Add a feedback network (e.g., voltage series using a resistor).
 Apply AC input signal.
 Measure gain with and without feedback.
 Analyze improvement in linearity and bandwidth.

CIRCUIT DIAGRAM
MODEL GRAPH
TABULATION
𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛
(𝑉𝑜𝑢𝑡)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

EXP. NO. :06 FREQUENCY RESPONSE OF SINGLE STAGE BJT AMPLIFIER
DATE:

AIM:

To determine the frequency response (gain vs frequency) of a single stage BJT amplifier.

APPARATUS REQUIRED

Components Value Quantity

N – channel MOSFET IEF740 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Construct CE amplifier.
 Sweep input signal frequency from 10 Hz to 1 MHz.
 Measure output at each frequency.
 Plot gain (dB) vs frequency.
 Identify bandwidth and 3-dB points.

CIRCUIT DIAGRAM
MODEL GRAPH

TABULATION

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛

(𝑉𝑜𝑢𝑡)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

 EXP. NO. :07
DATE: FREQUENCY RESPONSE OF SINGLE STAGE MOSFET AMPLIFIER

AIM

To study how gain varies with frequency in a single-stage MOSFET amplifier.

APPARATUS REQUIRED

Components Value Quantity

N – channel MOSFET IEF740 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Construct common source amplifier.

 Vary frequency of input signal.
 Measure gain at different frequencies.
 Plot frequency response.
 Analyze low/high-frequency cutoffs.
CIRCUIT DIAGRAM
MODEL GRAPH

TABULATION

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛

(𝑉𝑜𝑢𝑡)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

EXP. NO. :08
DATE: DESIGN AND ANALYSIS OF MOSFET DIFFERENTIAL AMPLIFIER

AIM

To design a CMOS differential amplifier for a given specification using voltage divider bias and obtain
the frequency response characteristics.

APPARATUS REQUIRED

Components Value Quantity

N – channel MOSFET IEF740 2
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Two matched MOSFETs with shared source.

 Differential input:
 Output taken from one or both drains.
 Suppresses common-mode signals (good noise rejection).
 Used in op-amps and analog front ends.

CIRCUIT DIAGRAM
MODEL GRAPH

TABULATION

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛

(𝑉𝑜𝑢𝑡)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

EXP. NO. :09
DATE: DESIGN AND ANALYSIS OF CASCODE AMPLIFIER USING BJT

AIM
To construct a cascode amplifier and analyze its performance in terms of gain and frequency response.
APPARATUS REQUIRED

Components Value Quantity

N – channel MOSFET IEF740 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Cascade two BJT transistors – CE followed by CB stage.

 Bias both stages properly.
 Apply input at CE base and output from CB collector.
 Measure gain and compare with single-stage.
 Observe improvement in bandwidth and gain stability.

CIRCUIT DIAGRAM
MODEL GRAPH
TABULATION

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛

(𝑉𝑜𝑢𝑡)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date

 EXP. NO. :10 DESIGN AND ANALYSIS OF SOURCE FOLLOWER / COMMON
DATE: COLLECTOR BUFFER AMPLIFIER

AIM
To design a buffer amplifier using source follower (MOSFET) or common collector (BJT) and analyze gain
and impedance.

APPARATUS REQUIRED

Components Value Quantity

N – channel MOSFET IEF740 1
Resistors 56 kΩ, 4.7 kΩ, 470 kΩ Each 1
Capacitor 0.1 μF 1
Breadboard, CRO, Function Generator, DC 0 – 30V Required
Supply

THEORY

 Construct the amplifier using BJT or MOSFET.

 Apply AC input and observe output voltage.
 Calculate voltage gain
 Measure input and output resistance.
 Use for impedance matching applications.

CIRCUIT DIAGRAM
MODEL GRAPH

TABULATION

𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑜𝑢𝑡/𝑉𝑖𝑛 𝐺𝑎𝑖𝑛=20𝑙𝑜𝑔𝑉𝑜𝑢𝑡/𝑉𝑖𝑛

(𝑉𝑜𝑢𝑡)
CALCULATION
RESULT

Description Marks

Preparation /20

Observation and Results /25

Viva /10

Record Simulation / Experiment / /10

Performance / Neatness

Submission on time /10

Total /75

Signature of Faculty with date