• Pin configuration of 8085

• It has 40 pins and uses +5V for power.

• It is an 8-bit microprocessor.
• It is an appended version of the 8080 microprocessor.
• It can run at a maximum frequency of 3 MHz.
• The maximum memory attached to the 8085 microprocessor is 64 KB.
• The signals of this 40 pin IC grouped into 7 categories, which are given
below:
1. Power supply and clock signals
2. Data but
3. Address bus
4. Serial I/O ports
5. Control and status signals
6. Interrupts and externally generated signals
7. Direct memory access
• Pin description of 8085 Microprocessor
1. Power supply and clock signals
In 40 pin configuration, 4 pins are allotted to this particular category.
• Vcc – Pin number 40 denotes Vcc, and an external power supply of
+5V is provided at this pin
• Vss – Its pin number is 20. This pin shows the grounded connection
of the microprocessor.
• X1 and X2 –these are represented by pin number 1 and 2
respectively in the pin configuration. These 2 pins are connected
with a crystal oscillator or LC network to maintain the internal
frequency of the clock. (3KHz)
• CLK (OUT) - It is the 37th pin of the 8085 IC and acts as the system
clock that keeps the record of time duration required by each
operation to get completed.

2. Address Bus – This category contains 8 pins

• The address bus has 16 lines. I.e. it can carry 16 bits at a time.
However, out of 16, 8 are multiplexed with the data bus and the
leftover 8 are separately shown by pin number 21 to 28 in the pin
configuration.
• These are used to carry the address of data and instruction from
the processor to the memory location and is unidirectional in
nature. These are denoted by A8 to A15 that represents the 8 MSB
of the memory location or input-output address.
• The address bus contains the address of the desired memory
location from where the data or instruction is to be fetched. While
the data bus contains the data or instruction that is needed to be
fetched from the memory.

3. Serial I/O ports – it has basically 2 pins

• SID : SID denotes serial input data pin and its pin is numbered as 5.
with this pin, data is serially fed to the processor directly through the
input devices.
• SOD : SOD denotes serial output data pin and its pin number is 4, in
the pin configuration of 8085. Once the data is processed in the
microprocessor then this pin represents bit by bit results at the
output devices.
5. Control and status signals: 6 pins of the pin configuration are used
by control and status signals.
• ALE- ALE is an acronym for address latch enable and is pin number
30 in the configuration. The 8 lower order bits of the 16-bit address
bus are multiplexed with the 8-bit data bus. (ALE is a active high
signal. It represents the status of the address and data line.
• If address is passing through(12-19) pins, the ALE shows 1 value.
• If data is passing through (12-19) pins, The ALE shows 0 value.
• RD- This pin in numbered 32 in the configuration and low signal in
this pin shows the read operation either from I/O devices or
from the memory unit. Thereby indicating that the data bus is now
in a state or position to accept the data from the memory or I/O
devices.
• IO/M- it is pin number 34 and indicates the selection of a memory
address or input-output device. This shows whether the read/write
operation is to be carried out at the memory location or at the I/O
device.
• The low signal at this pin shows that operation is performing over
memory location. As against, a high signal at this pin represents the
operation at I/O device.
• S0 and S1- the pins S0 and S1 represent the status signal at pin
number 29 and 33 respectively. These signals show the type of
recent operation of the microprocessor. The table below represents
the status of the data bus under different conditions:

IO/M S1 S2 Data Bus Status

0 0 0 Halt
0 0 1 Memory Write
0 1 0 Memory Read
1 0 1 IO write
1 1 0 IO Read
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
6. Interrupts and Externally generated signals
• Interrupts are the signals that are generated to break the sequence
of an ongoing operation. When an interrupt signal is generated
then CPU immediately stops its recent task under operation and
switches to some other program know as interrupt service routine
(ISR).
• However, after handling ISR, the CPU gets back to its main program
for execution.
• In the pin configuration, 5 types of interrupts are shown by 5
different pins from pin number 6 to 10. These pins are used to
manage the interrupt.
• There are exists 2 types of interrupts:
1. Maskable Interrupt : We can disable the interrupt by writing some
instruction into the program
2. Not-maskable interrupt: We cannot disable the interrupt by writing
instruction.
Out of the 5 major interrupts 4 are the maskable interrupts. These are
INTR, RST5.5, RST6.5, RST7.5 are easily manageable interrupts.
However, TRAP is a non-maskable interrupt and holds the topmost
priority among all interrupts in the 8085 microprocessor. INTR has the
lowest priority.
RESET IN- it is pin number 36 in the pin diagram. An active low signal at this
pin resets the PC of the microprocessor to 0.
When microprocessor is Reset, then all the register including program
counter are cleared. Program counter holds the address of the next
instruction what it is going to fetch. (0000H).

RESET OUT: Tt is the 3rd pin in the diagram. This pin generates a signal to
provide information about the resetting of the microprocessor. Once a
processor is reset then all the connected devices must also be reset.
• So, enabling this signal shows the resetting of the interconnected devices.

• INTA: it is the 11th pin of the 8085 pin configuration. A signal at this pin
acknowledges the generated interrupt.
• 7. Direct Memory Access (DMA):
• Memory and I/O devices are connected with each other by the
microprocessor. So, the intermediator I.e., CPU manages the data
transfer between the input-output device and memory.
• When data in a large amount is to be transferred between
I/O devices and memory the CPU gets disabled by tri-stating its
buses. And this transfer is manageable by external control circuits.
The DMA has 2 pins.
• HOLD- the signal is generated at pin number 39. This pin generates
a signal to notify the processor that more than one request is
present to access the data and address bus.
• When this signal gets enabled, the CPU frees the bus
after completion of the recent operation. Once the hold signal
gets disabled, the processor can access the bus again.
• HLDA- the signal is generated at pin number 38. This signal is enabled
at the time when the processor gets HOLD signal and it releases
HLDA I.e, hold acknowledge signal. In order to show that the multiple
requests are kept on hold and will be considered once the bus gets
free after the recent operation.
• After the disabling of hold request, HLDA signal becomes low.
• READY- This is the 35th numbered pin in the pin diagram that
maintains synchronization between the processor and peripherals,
memory. It is clear that a microprocessor has a much faster response
than peripherals and memory.
• So this pin is enabled when the processor as well as the peripherals
and memory both become ready to begin the next operation.
• In this case when the READY pin is disabled, then the microprocessor
is in the WAIT state.
• Microprocessor Operation
• Operations of ALU is arithmetic as well as logical which includes addition,
increment, subtraction, decrement, logical operations like AND, OR, Ex-OR,
complement, evaluation, left shift or right shift. Both the temporary
registers as well as accumulators are utilized for holding the information
throughout the operations then the outcome will be stored within the
accumulator. The different flags are arranged or rearrange based on the
outcome of the operation.
• Flag Registers Control and Timing Unit
• Decoder and Instruction Register Register Array
• Special Purpose Registers Program Counter
• Stack Pointer in 8085 Increment or Decrement Register
• Address-Buffer & Address-Data-Buffer Address Bus and Data Bus
• Timing & Control Unit
• Flag Registers
• The flag registers of microprocessor 8085 are classified into five types
namely sign, zero, auxiliary carry, parity and carry. The positions of
bit set aside for these types of flags. After the operation of an ALU,
when the result of the most significant bit (D7) is one, then the sign
flag will be arranged. When the operation of the ALU outcome is zero
then the zero flags will be set. When the outcome is not zero then the
zero flags will be reset.
• Control and Timing Unit
• The control and timing unit coordinates with all the actions of the
microprocessor by the clock and gives the control signals which are
required for communication among the microprocessor as well as
peripherals.
• Decoder and Instruction Register
• As an order is obtained from memory after that it is located in the
instruction register, and encoded & decoded into different device
cycles.
• Register Array
• The general purpose programmable registers are classified into
several types apart from the accumulator such as B, C, D, E, H, & L.
These are utilized as 8-bit registers otherwise coupled to stock up the
l6 bit of data. The permitted couples are BC, DE & HL, and the short
term W & Z registers are used in the processor & it cannot be utilized
with the developer.
• Special Purpose Registers
• These registers are classified into four types namely program counter,
stack pointer, increment or decrement register, address buffer or data
buffer.
• Program Counter
• This is the first type of special-purpose register and considers that the
instruction is being performed by the microprocessor. When the ALU
completed performing the instruction, then the microprocessor
searches for other instructions to be performed. Thus, there will be a
requirement of holding the next instruction address to be performed
in order to conserve time. Microprocessor increases the program
when an instruction is being performed, therefore that the program
counter-position to the next instruction memory address is going to
be performed
• Stack Pointer in 8085
• The SP or stack pointer is a 16-bit register and functions similar to a
stack, which is constantly increased or decreased with two
throughout the push and pop processes.
• Increment or Decrement Register
• The 8-bit register contents or else a memory position can be
increased or decreased with one. The 16-bit register is useful for
incrementing or decrementing program counters as well as stack
pointer register content with one. This operation can be performed
on any memory position or any kind of register.
• Address-Buffer & Address-Data-Buffer
• Address buffer stores the copied information from the memory for
the execution. The memory & I/O chips are associated with these
buses; then the CPU can replace the preferred data by I/O chips and
the memory.
• Address Bus and Data Bus
• The data bus is useful in carrying the related information that is to be
stock up. It is bi-directional, but the address bus indicates the
position as to where it must be stored & it is uni-directional, useful
for transmitting the information as well as address input/output
devices.
• Timing & Control Unit
• The timing & control unit can be used to supply the signal to the 8085
microprocessor for achieving the particular processes. The timing and
control units are used to control the internal as well as external
circuits. These are classified into four types namely control units like
RD’ ALE, READY, WR’, status units like S0, S1, and IO/M’, DM like
HLDA, and HOLD unit, RESET units like RST-IN and RST-OUT.
• Instruction Cycle of 8085 Microprocessor:
• During normal operation, the microprocessor sequentially fetches,
decodes and executes one instruction after another until a halt
instruction (HLT) is executed.
• The fetching, decoding and execution of a single instruction
constitutes an instruction cycle, which consists of one to five read or
write operations between processor and memory or input/output
devices.
• Each memory or I/O operation requires a particular time period,
called machine cycle. In other words, to move byte of data in or out
of the microprocessor, a machine cycle is required.
• Each machine cycle consists of 3 to 6 clock periods/cycles, referred to
as T-states.
• Therefore we can say that, one Instruction Cycle of 8085 consists of
one to five machine cycles and one machine cycle consists of three to
six T-states i.e. three to six clock periods.
• There are seven different types of machine cycles in the 8085A. Three
status signals IO/M, S1 and S0 identify each type as shown in Table.
These signals are generated at the beginning of each machine cycle
and remained valid for the duration, of the cycle.
• Clock Signal:
• The 8085 divides the clock frequency provided at X1 and X2 inputs by
2, which is called operating frequency.
• All the operations within the Instruction Cycle of 8085 are
synchronized with this operating frequency.
• Therefore in the timing diagram operating frequency clock is shown
on the top and then the signals are shown with reference to
operating frequency clock.
• Ideally, the clock signal should be square wave with zero rise time and
fall time.
• But in practice, we don’t get zero rise time and fall time.
• Therefore the clock and other signals are always shown with
finite rise and fall times.
• Single Signal
• Single signal is represented by a line. It may have status either logic 0
or logic 1 or tri-state.
• The change in the state of the signal takes finite time and hence the
state change of signal is represented with finite rise time and fall
time, as shown in the figure.
• Group of Signals:
• Group of signals is also called a bus e.g. address bus and data bus.
• To avoid complications in the timing diagram these signal are grouped
and shown in the form of block as shown in figure.
• In the group representation individual state is not considered, but the
group state is considered.
• Change in state of single signal changes the state of group.
• It is represented by the cross as shown the figure.
• The tri-state condition of the group signals is shown by dotted lines.
• Two straight lines represent valid state/stable state.
• In microprocessor systems, activation of signal/signals depends on
the state of other signal/signals.
• Such situations are shown in the timing diagrams with the help of
specific symbols. There are four possibilities :

• Activation of a signal with the change in state of other signal.

• Activation of a signal with the Change in state of other signals.
• Activation of signals with the change in state of other signal.
• Activation of signals with the change in state of other signals.
• The representation of dependence of the signal/signals, in the
timing diagram
• Signal Timings:
• In the Instruction Cycle of 8085 microprocessor, signals are activated
at specific instant for specific time period.
• Once we understand this, it is very easy to draw timing diagrams.
• ALE (Address Latch Enable):
• This signal is active high signal.
• It is activated in the beginning of the T1 state of each machine
cycle, except bus idle machine cycle, and it remains active in the
T1 state as shown in the figure
• A0—A7 (Lower byte address):
• The lower byte of address is available on the multiplexed
address/data bus (AD0 – AD7) during T1 state of each machine cycle,
except bus idle machine cycle.
• D0-D7 (Data Bus):
• The data from memory or I/O device and from microprocessor to
memory or I/O device is transferred during T2 and T3-states.
• It is important to note that in Read machine cycle, data will appear
on the data bus during the latter part of the T2-state, as shown in the
first figure.
• Whereas in write cycle data will appear on the data bus at the
beginning of the T2-state, as shown in the second figure.
• To read data from memory or I/O device it is necessary to select
memory or I/O device.
• After selection, device will put the data from, selected location on
the data bus.
• This action needs finite time. This time is referred to as ‘access time‘.
• In case, of write cycle, data is available in the registers of the
microprocessor and it can put that data on the data bus with zero
access time.
• A8 – A15 (Higher byte address):
• The higher byte of address is available on the A8 – A15 bus during T1,
T2 and T3 — states of each machine cycle, except bus idle machine
cycle, as shown in figure.
• These signals are called status signals. They decide the type of
machine cycle to be executed.
• They are activated at the beginning of T1-state of each machine cycle
and remain active till the end of the machine cycle.
• RD and WR:
• These signals decide the direction of the data transfer. When RD
signal is active, data is transmitted from memory or I/O device to
the microprocessor, and when WR signal is active, data is
transmitted from microprocessor to the memory or I/O device. Both
signals are never active at a time.
• As we know data transfer in Instruction Cycle of 8085 takes place
during T2 and T3, these signals are activated during T2 and T3, as
shown in the figure.
• Figure
• Fetch Operation and Timing Diagram
• In the Opcode Fetch cycle, it fetches the instructions from memory
and delivers it to the instruction register of the microprocessor.
• The op-code fetch timing diagram can be explained as below:
• Operation:
• During T1 state, microprocessor uses IO/M(bar), S0, S1 signals are
used to instruct microprocessor to fetch opcode.
• Thus when IO/M(bar)=0, S0 = S1= 1, it indicates opcode fetch
operation.
• During this operation 8085 transmits 16-bit address and also uses ALE
signal for address latching.
• At T2 state microprocessor uses read signal and make data ready from
that memory location to read opcode from memory and at the same
time program counter increments by 1 and points next instruction to
be fetched.
•
• In this state microprocessor also checks READY input signal, if this pin
is at low logic level ie. '0' then microprocessor adds wait state
immediately between T2 and T3.
• At T3, microprocessor reads opcode and store it into instruction
register to decode it further.
• During T4 microprocessor performs internal operation like decoding
opcode and providing necessary actions.
• The opcode is decoded to know whether T5 or T6 states are required,
if they are not required then µp performs next operation.
• Memory Read Machine Cycle
• The MP places the 16-bit memory address from the program counter
on address bus. At time period T1, the higher order memory address
is placed on the address lines A15 – A8. When ALE is high, the lower
address is placed on the bus AD7 – AD0. The status signal IO/M(bar)
goes low indicating the memory operation and two status signals S1 =
1, S0 = 0 to indicate memory read operation.
• At time period T2, the MP sends RD(bar) control line to enable the
memory read. When memory is enabled with RD(bar) signal, the data
from the addressed memory location is placed on the data bus with
ALE low.
• The data is reached at processor register during T3 state. When data
is arrived, the RD(bar) signal goes high. It causes the bus to go into
high impedance state.
• Memory Write Machine Cycle
• The MP places the 16-bit memory address from the program counter
on address bus. At time period T1, the higher order memory address
is placed on the address lines A15 – A8. When ALE is high, the lower
address is placed on the bus AD7 – AD0. The status signal IO/M(bar)
goes low indicating the memory operation and two status signals S1 =
0, S0 = 1 to indicate memory write operation.
• At time period T2, the MP sends WR(bar) control line to enable the
memory write. When memory is enabled with WR(bar) signal, the
data from the processor is placed on the addressed location with ALE
low.
• The data is reached at memory location during T3 state. When data is
reached, the WR(bar) signal goes high. It causes the bus to go into
high impedance state.
• Timing diagram of MVI Instruction
• MVI A, 32 H → transfer 32H data into Accumulator (2 byte
instruction)
Memory Location Data
2000 H 3E H (Opcode )
2001 H 32 H

• In first phase, it will execute Opcode Fetch

• In second phase, it will execute Memory Read
• Timing Diagram
• Opcode Fetch Memory Read
T1 T2 T3 T4 T5 T6 T7
CLK

A8-A15
Higher Address (20 H) Unspecified Higher Address (20 H)

AD0 – AD7
Low (00 H) Data (3EH) Low (01 H) Data (32 H)

ALE

IO/M, S1, S0 IO/M = 0, S1 = 1, S0 = 1 IO/M = 0, S1 = 1, S0 = 0

Read
• Timing Diagram of INR M instruction
• C500H address INR M instruction is written
• But at that time memory is pointing to another location D050H
• D050 H contains the data E1H .
• When INR instruction is executed the content of Memory location
need to be increased to E2H. But it can’t be done at Memory Location
itself.
• Steps
1. INR M ( Opcode = 34 H), Read Opcode instruction
2. Read Data of Memory Content (E1 H) = Memory Read
3. Write the incremented value at Memory Location = Memory Write
 • Timing diagram
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3

CLK

A8-A15 D0 H
C5 H DOH

AD0- AD7 00 H E2 H
34 H 50H E1 H 50 H

ALE

IO/M,S1,S0 IO/M = 0, S1 =1, S0 =1 IO/M = 0, S1 = 1, S0 = 0 IO/M = 0, S1 = 0, S0 = 1

RD

WR
• Memory Device, Storage, and Classification
• Memory storage is just like a human brain. It is used to store data and
instruction. Computer memory is the storage space in the computer
where data is to be processed and instructions required for
processing are stored.
• In a broad sense, memory can be classified as –
• Main Memory– (Primary memory)
• Main memory has the disadvantage of high-cost and low-capacity storage.
But its advantage or facility is the high speed of data transfer.
• The control unit can be able to directly communicate with the main
memory.
• Main memory can be generally classified into random-access
memory (RAM) and read-only memory (ROM). It is a volatile memory. Due
to the absence of power, the content of this memory will be lost.

• Secondary Memory– Secondary memory is also frequently known

as auxiliary memory. The control unit can’t directly communicate with the
secondary memory. It is a non-volatile memory.
• RAM (Random Access Memory) is the internal memory of the
CPU for storing data, program, and program result. It is a read/write
memory which stores data until the machine is working. As soon as
the machine is switched off, data is erased.
• Access time in RAM is independent of the address, that is, each
storage location inside the memory is as easy to reach as other
locations and takes the same amount of time. Data in the RAM can
be accessed randomly but it is very expensive.
• RAM is volatile, i.e. data stored in it is lost when we switch off the
computer or if there is a power failure. Hence, a backup
Uninterruptible Power System (UPS) is often used with computers.
RAM is small, both in terms of its physical size and in the amount of
data it can hold.
• RAM is of two types −
1. Static RAM (SRAM)
2. Dynamic RAM (DRAM)

Static RAM (SRAM)

• The word static indicates that the memory retains its contents as long as
power is being supplied. However, data is lost when the power gets down
due to volatile nature. SRAM chips use a matrix of 6-transistors and no
capacitors. Transistors do not require power to prevent leakage, so SRAM
need not be refreshed on a regular basis.
• There is extra space in the matrix, hence SRAM uses more chips than
DRAM for the same amount of storage space, making the manufacturing
costs higher. SRAM is thus used as cache memory and has very fast access.
• Characteristic of Static RAM
• Long life
• No need to refresh
• Faster
• Used as cache memory
• Large size
• Expensive
• High power consumption
• Dynamic RAM (DRAM)
• DRAM, unlike SRAM, must be continually refreshed in order to
maintain the data. This is done by placing the memory on a refresh
circuit that rewrites the data several hundred times per second.
DRAM is used for most system memory as it is cheap and small. All
DRAMs are made up of memory cells, which are composed of one
capacitor and one transistor.
• Characteristics of Dynamic RAM
• Short data lifetime
• Needs to be refreshed continuously
• Slower as compared to SRAM
• Smaller in size
• Less expensive
• Less power consumption
• ROM stands for Read Only Memory.
• The memory from which we can only read but cannot write on it. This
type of memory is non-volatile. The information is stored
permanently in such memories during manufacture.
• A ROM stores such instructions that are required to start a
computer. This operation is referred to as bootstrap. ROM chips are
not only used in the computer but also in other electronic items like
washing machine and microwave oven.
• MROM (Masked ROM)
• The very first ROMs were hard-wired devices that contained a pre-
programmed set of data or instructions. These kind of ROMs are
known as masked ROMs, which are inexpensive.

• PROM (Programmable Read Only Memory)

• PROM is read-only memory that can be modified only once by a user.
The user buys a blank PROM and enters the desired contents using a
PROM program.
• Inside the PROM chip, there are small fuses which are burnt open
during programming. It can be programmed only once and is not
erasable.
• EPROM (Erasable and Programmable Read Only Memory)
• EPROM can be erased by exposing it to ultra-violet light for a
duration of up to 40 minutes.
• Usually, an EPROM eraser achieves this function. During
programming, an electrical charge is trapped in an insulated gate
region.
• The charge is retained for more than 10 years because the charge has
no leakage path. For erasing this charge, ultra-violet light is passed
through a quartz crystal window (lid).
• This exposure to ultra-violet light dissipates the charge. During
normal use, the quartz lid is sealed with a sticker.
• EEPROM (Electrically Erasable and Programmable Read Only Memory)
• EEPROM is programmed and erased electrically. It can be erased and
reprogrammed about ten thousand times.
• Both erasing and programming take about 4 to 10 ms (millisecond). In
EEPROM, any location can be selectively erased and programmed.
EEPROMs can be erased one byte at a time, rather than erasing the
entire chip.
• Hence, the process of reprogramming is flexible but slow.
• Advantages of ROM
• Non-volatile in nature
• Cannot be accidentally changed
• Cheaper than RAMs
• Easy to test
• More reliable than RAMs
• Static and do not require refreshing
• Contents are always known and can be verified
• Serial Access Memory
• In sequential access memory, data is read in sequence. Access can still
be made to arbitrary locations by seeking the requested location.
• This operation, however, is often relatively inefficient because of the
seek time.
• In SAM, any address at any location cannot be accessed directly, but
it should be accessed sequentially that is one after another.
Therefore it is called sequential access memory.
• Magnetic tape is used in serial access memory.
• SAM is also called a Shift Register.
• If the output of SAM is connected to the input it is called circular Shift
Register.
 Read Operation
• SAM Read

1 0 1 Output 1
Input
cell
Write

Write Operation
Read

1 0 1 Output 0
Input
0
cell

Write
• Magnetic SAM Read / Write Head

Read Operation

0 1 0 1 0

Magnetic Tape Moves

Output:
Read / Write Head
Write Operation If we want to 1 0 0 1 0 0

0 0 1 0 0 1

Magnetic Tape Moves

• Direct Access Memory
• Direct access memory or Random Access Memory, refers to
conditions in which a system can go directly to the information that
the user wants. Memory device which supports such access is called
a Direct Access Memory.
• Magnetic disks, optical disks are examples of direct access memory.
• It is designed by Intel to transfer data at fastest rate.
• It allows the I/O devices to send or receive data directly to or from
the memory without the involvement of the CPU.
• How DMA operation are performed?
1. If I/O device wants to send data to the memory, it first has to send
DMA request (DRQ) to DMA controller.
2. DMA controller then sends Hold Request (HLQ) to CPU and waits
for the CPU to send Hold Acknowledgement.
3. The CPU leaves control over bus and acknowledges the HLDA signal
to DMA controller.
4. Now CPU is in Hold state, DMA controller has to manage operations
over buses between CPU, Memory, I/O Devices.
• DMA

Peripherals Memory

DRQ

Controls System Bus

DMA Controller

HLQ HDLA

CPU
• Cache Memory
• It is also called cache, supplementary memory system that
temporarily stores frequently used instruction and data for quicker
processing by the central processing unit (CPU) of a computer.
• It is an extension of a computer’s main memory.
• It is not high cost as registers and not cheaper like main memory.
Therefore we use this memory to reduce bottleneck.
• Cache holds a copy only the most frequently used information or
program codes stored in the main memory.
• The smaller capacity of the cache reduces the time required to locate
data within it and provide it to the CPU for processing.
• When a computer’s CPU accesses its internal memory, it first checks
to see of the information it needs is stored in the cache.
• If it is in the Cache, it returns the data to the CPU.
• If the information is no in the cache, the CPU retrieves it from the
main memory.

Main
Memory CPU

Cache registers
memory
• Advantages of Cache Memory
• Cache memory is faster than the main memory.
• It consumes less access time as compared to the main memory.
• It stores the program that can be executed within a short period of
time.
• It stores data for temporary use.

• Disadvantages of Cache Memory

• Cache memory has limited capacity.
• It is very expensive.
• Virtual memory
• It is the memory which appear to be present but it is not .
• It allows user to use more memory for a program than the real
memory of computer.
• For example, the real memory of the computer is 4 GB but the virtual
memory can be 16 GB (not constant)
• It is a concept that gives the illusion to the user that they have main
memory equal to the capacity of the secondary storage media.
• A programmer can write a program which requires more memory
than the capacity of the Main memory, such a program is executed by
the help of virtual Memory technique.
• Only a part of program needs to be in main memory for execution.
• Logical address space (virtual) can therefore be much larger than
physical address space (main).
• It allows address space to be shared by several processes
• So more programs can be can concurrently
• Less number of I/O would be needed to load or swap each user
program into memory.
• Figure

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Disk
• Auxiliary Memory (secondary Memory)
• Secondary memory is also known as auxiliary memory.
• It is used to store data and programs permanently.
• In this memory data and programs are retained with the power is
turned off.
• It is a non-volatile memory.
• Characteristics of Auxiliary Memory are following −
• Non-volatile memory − Data is not lost when power is cut off.
• Reusable − The data stays in the secondary storage on a permanent
basis until it is not overwritten or deleted by the user.
• Reliable − Data in secondary storage is safe because of the high
physical stability of secondary storage devices.
• Convenience − With the help of computer software, authorized
people can locate and access the data quickly.
• Capacity − Secondary storage can store large volumes of data in sets
of multiple disks.
• Cost − It is much lesser expensive to store data on a tape or disk than
primary memory.
• Address Decoding
• Interfacing 8085 means the way to properly connect the
microprocessor with the outside unit i.e. I/O unit and the inside unit
i.e. Memory unit. So, there are two types of interfacing: I/O
interfacing and Memory interfacing.
• I/O interfacing means how to connect MP to the peripheral devices .
• Memory interfacing means how to connect MP to the memory
devices e.g. RAM, ROM, EPROM etc.
• For the interfacing, the address pins must be decoded using the
technique called "Address Decoding".
• Address Decoding technique uses following decoders to decode:
• i) Logic Gate Decoder (Simple NAND Gate decoder)
• ii) Line Decoder
- The 1-to-2 line decoder
- The dual 2-to-4 line decoder
- The 3-to-8 line decoder
• 8085 microprocessor has 16-bit address i.e. it uses 16 pins for address
bus.
• When we have to interface with 4 KB RAM. This RAM has 12-bit
address bus ( 2^n *m) = (2^12 = 4*1024 bytes).
• Where n= number of address lines and m = no of data line
• Lower 12-bits (A0-A11) of MP gets directly connected to address pins
of RAM.
• But, other upper 4-bits (A12-A15) address of MP pins are needed to
be decoded by using above decoders.
• RD’ is used by the memory to output/read data on data lines and
WR’ is used to write/ input into specific memory location.
• The memory is enabled by CS’ (Chip select) and operated at CLK
speed at which the memory read and write data.
• Decoder and Address Range
No. of Memory Size Address Range
S2 S1 S0 D0-D7 add
D0 0 0 0 D0 line
S0 D1 4 2^4 =16 0H to FH
0 0 1 D1
D2
0 1 0 D2 8 2^8 = 256 00H to FFH
S13 * 8 Decoder D3
D4 0 1 1 D3 10 2^10 = 1K 000H to 3FFH
D5 11 2^11 = 2K 000H to 8FFH
S2 1 0 0 D4
D6
D7 1 0 1 D5 12 2^12 = 4K 0000H to FFFH
1 1 0 D6 13 2^13 = 8K 0000H to 1FFFH
1 1 1 D7 14 2^14 = 16K 0000H to 3FFFH
15 2^15 = 32K 0000H to 7FFFH
16 2^16 = 64K 0000H to FFFFH
• 8085 has 16 address line and its memory addressing capacity is
• 2^16 = 64 KB addresses
• More than 1 memory chip are connected to processor
• Sum of all memory sizes ≤ processor's memory addressing capacity
• Maximum size of memory connected to 8085 is 64KB, which can be in
any combination of different memory sizes. (1KB, 2KB, 4KB,8KB, 16KB)
• Memory Interfacing
• Control signals of the memory (RD’ and WR’) are connected to
MEMR’ and MEMW’ generated from the processor’s control signals.
• Data lines of the memory are directly connected to the Processor’s
data lines.
• As number of address lines differ in the memory and the
microprocessor (memory has less no of address lines)
• We should connect the required address lines (starting from lower order)
from processor to memory.
• Remaining address lines of the processor are decoded to connect to chip
select (CS’) of memory to generate unique address range for the decoder.
• Example : 2K * 8 Memory
• 11 address lines (2^ = 2048 ie 2K) and 8 data lines
• A0 –A10 and D0-D711 A B Z
A11 – A15 A 0 0 1
Z
B 0 1 1
1 0 1
8085
CS’ 1 1 0
A0- A15 Data Lines
Memory
A0 – A10 (2K*8)

• CS’ would be selected when all the inputs are high

• Address Range
Chip select Address Lines
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 F800H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFH
• Example : 8K * 8 Memory
• 13 address lines (2^13 = 8192 ie 8K) and 8 data lines
A B Z
0 0 1
A13 – A15 A 0 1 1
Z
B 1 0 1
8085 1 1 0
CS’
A0- A15 Data Lines
Memory
A0 – A12 (8K*8)
• Address Range
Chip select Address Lines

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 E000H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFH
• Example: 4K * 8 Memory using Decoder

A15 O0’
CE’ O1’

3*8 Decoder
O2’
A14 0 S0 O3’
A13 1 S1 O4’
A12 0 O5’
S2 O6’
O7’
8085
CS’
A0- A15 Data Lines
Memory
A0 – A11 (8K*8)

• 12 address lines (2^12 = 4096 i.e 4K) and 8 data lines

• A15 is connected to decoder Chip Enable.
• It Chip Enable should be low. Until the Chip Enable is not on, the
Decoder will not work.

• Address Range
Chip select Address Lines

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2000H
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 2FFFH
• Example: 8K * 8 Memory Using Decoder
• 13 address lines (2^13 = 8192 i.e 8K) = 8 data lines

GND O0’
CE’ O1’

3*8 Decoder
O2’
A15 1 S0 O3’
A14 0 S1 O4’
A13 0 O5’
S2 O6’
O7’
8085
CS’
A0- A15 Data Lines
Memory
A0 – A12 (8K*8)
• Ashish Dhakal Madhav
• Sanjeev Adhikari Prasant
• Sundar Chettri Himal
• Prabesh Susmita
• Ayush Shiv
• Shraddha Sima
• Soni
• Address Range

Chip select Address Lines

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 9FFFH