Full Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity full_adder_vhdl_code is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end full_adder_vhdl_code;
architecture gate_level of full_adder_vhdl_code is
begin
S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;
end gate_level;
Logic Gates
And Gate
library IEEE;
use IEEE.std_logic_1164.all;
-- Entity declaration
entity andGate is
port(A : in std_logic; -- AND gate input
B : in std_logic; -- AND gate input
Y : out std_logic); -- AND gate output
end andGate;
-- Dataflow Modelling Style
-- Architecture definition
architecture andLogic of andGate is
begin
Y <= A AND B;
end andLogic;
OR gate
library IEEE;
use IEEE.std_logic_1164.all;
-- Entity declaration
entity orGate is
port(A : in std_logic; -- OR gate input
B : in std_logic; -- OR gate input
Y : out std_logic); -- OR gate output
end orGate;
-- Dataflow Modelling Style
-- Architecture definition
architecture orLogic of orGate is
begin
Y <= A OR B;
end orLogic;
Full Subtractor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FULLSUBTRACTOR_BEHAVIORAL_SOURCE is
Port ( A : in STD_LOGIC_VECTOR (2 downto 0);
Y : out STD_LOGIC_VECTOR (1 downto 0));
end FULLSUBTRACTOR_BEHAVIORAL_SOURCE;
architecture Behavioral of FULLSUBTRACTOR_BEHAVIORAL_SOURCE is
begin
process (A)
begin
if (A = "001" or A = "010" or A = "111") then
Y <= "11";
elsif (A = "011") then
Y <= "01";
elsif (A = "100") then
Y <= "10";
else
Y <= "00";
end if;
end process;
end Behavioral;
MUltiplexer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity MUX_SOURCE is
Port ( S : in STD_LOGIC_VECTOR (1 downto 0);
I : in STD_LOGIC_VECTOR (3 downto 0);
Y : out STD_LOGIC);
end MUX_SOURCE;
architecture Behavioral of MUX_SOURCE is
begin
process (S,I)
begin
if (S <= "00") then
Y <= I(0);
elsif (S <= "01") then
Y <= I(1);
elsif (S <= "10") then
Y <= I(2);
else
Y <= I(3);
end if;
end process;
end Behavioral;
VHDL Code for 1 to 4 Demux
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity demux_1to4 is
port(
F : in STD_LOGIC;
S0,S1: in STD_LOGIC;
A,B,C,D: out STD_LOGIC
);
end demux_1to4;
architecture bhv of demux_1to4 is
begin
process (F,S0,S1) is
begin
if (S0 ='0' and S1 = '0') then
A <= F;
elsif (S0 ='1' and S1 = '0') then
B <= F;
elsif (S0 ='0' and S1 = '1') then
C <= F;
else
D <= F;
end if;
end process;
end bhv;
VHDL Code for 2 to 4 decoder using case statement
view sourceprint?
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity decoder is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder;
architecture bhv of decoder is
begin
process(a)
begin
case a is
when "00" => b <= "0001"; when "01" => b <= "0010"; when "10" => b <= "0100"; when
"11" => b <= "1000";
end case;
end process;
end bhv;
VHDL Code for 4 to 2 encoder using if else statement
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder1 is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder1;
architecture bhv of encoder1 is
begin
process(a)
begin
if (a="1000") then
b <= "00";
elsif (a="0100") then
b <= "01";
elsif (a="0010") then
b <= "10";
elsif (a="0001") then
b <= "11";
else
b <= "ZZ";
end if;
end process;
end bhv;
