DIGITAL PRINCIPLES AND COMPUTER
U23EC301 L T P C
ORGANIZATION
3 0 2 4
COURSE OBJECTIVES:
To present the fundamentals of digital circuits and simplification methods.
To bring out the analysis and design procedures for synchronous and
asynchronous Sequential circuits.
To understand the basic structure and operation of a digital computer.
UNIT I BASIC CONCEPTS 9
Review of number systems-representation-conversions, Review of Boolean algebra-
theorems, sum of product and product of sum simplification, canonical forms min
term and max term, Simplification of Boolean expressions-Karnaugh map,
Implementation of Boolean expressions using universal gates.
UNIT II COMBINATIONAL LOGIC CIRCUITS 9
Problem formulation and design of combinational circuits - Code-Converters(Binary
to Gray code, Gray to Binary, BCD to Excess-3 code,Excess-3 to BCD), Half and Full
Adders, Binary Parallel Adder – Carry look ahead Adder, BCD Adder, Magnitude
Comparator, Decoder, Encoder, Mux/Demux, Case study: Digital trans-receiver Parity
Generator/Checker, Seven Segment display decoder
UNIT
SEQUENTIAL CIRCUITS 9
III
Latches, Flip flops – SR, JK, T, D, Master/Slave FF, Analysis and design of clocked
sequential circuits – Design - Moore/Mealy models, state minimization, state
assignment, Counters, Shift registers, Stable and Unstable states, output
specifications, Hazards, Essential Hazards, Design of Hazard free circuits.
UNIT IV COMPUTER FUNDAMENTAL 9
Functional Units of a Digital Computer: Von Neumann Architecture and Harvard
Architecture – Operation and Operands of Computer Hardware Instruction –
Instruction Set Architecture (ISA): Memory Location, Address and Operation –
Instruction and Instruction Sequencing – Addressing Modes.
UNIT
PROCESSOR AND MEMORY 9
V
Instruction Execution – Building a Data Path- Pipelining- basic memory, static
ROM,PROM,EPROM,EEPROM. Cache Memories: Mapping and Replacement
Techniques – Virtual Memory – DMA.
TOTAL: 45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Verification of Boolean theorems using logic gates.
2. Design and implementation of combinational circuits using gates for arbitrary
functions.
3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture
TEXT BOOKS:
1.M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to the
Verilog HDL, VHDL, and System Verilog”, Sixth Edition, Pearson Education, 2018.
2.David A. Patterson, John L. Hennessy, “Computer Organization and Design, The
Hardware/Software Interface”, Sixth Edition, Morgan Kaufmann/Elsevier, 2020.
REFERENCES:
1 Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian, “Computer
Organization and Embedded Systems”, Sixth Edition, Tata McGraw-Hill, 2012.
2 William Stallings, “Computer Organization and Architecture – Designing for
Performance”, Tenth Edition, Pearson Education, 2016.
3 M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education, 2016.
ONLINE RESOURCES:
1 https://archive.nptel.ac.in/courses/117/105/117105078/#
2 https://www.coursera.org/courses?query=computer%20architecture
3 https://onlinecourses.nptel.ac.in/noc21_ee39/preview
COURSE OUTCOMES:
Upon the completion of the course, the students will be able to
CO1 Apply Boolean Algebra and Simplification procedures relevant to digital logic
CO2 Design various combinational digital circuits using logic gates.
CO3 Design synchronous and asynchronous sequential digital circuits using logic
gates.
CO4 Summarize the basic structure and operation of a digital computer.
CO5 Analyze the data path unit of processor and concept of various memories .
CO – PO – PSO MAPPING:
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 3 2 1 2 - - - 2 2 2 - 1 2 2
CO2 3 3 3 3 1 - - 2 2 2 - 1 2 2
CO3 3 3 3 3 1 - - 2 2 2 - 1 2 2
CO4 2 2 1 1 - - - - - - - - 2 2
CO5 3 3 2 2 - - - - - - - - 2 2
