Exp.
No:11 FOUR BIT ARRAY MULTIPLIER
Date:
AIM:
To design and simulate 4X4 array multiplier using Modelsim software and Spartan FPGA
kit.
BLOCK DIAGRAM:
THEORY:
There are many different structures that can be used to implement a multiplier. Method 1 in
Table 1 shows diagrammatically the simple method for multiplication we were all taught in school,
modified so that all the numbers use binary notation. In the illustration, a 5-bit multiplicand is
multiplied by a 6-bit multiplier to obtain an 11-bit product. Each row of the array is the product of the
multiplicand and a single bit of the multiplier. Because multiplier bits are either 0 or 1, each row of
the array is either 0 or a copy of the multiplicand. The array is laid out so that each row is shifted to
the left to account for the increasing binary significance of the multiplier bits. We sum the rows of
the array to obtain the product. You may wish to verify that the result is correct: in base ten, the
multiplicand is 11, the multiplier 46, and the product 506. This simple method can be implemented
directly in hardware by using five Separate 2- input, 5- bit adders to add the six rows of the array
shown in the table. But this design suffers in two ways. First, it is large because there are a lot of
adders. And second, the delay will be substantial because bits must propagate through all five
adders and because each adder has a carry path to resolve a 5-bit carry.
PROGRAM:
--ARRAY MULTIPLIER
--AND GATE
library ieee;
use ieee.std_logic_1164.all;
entity andg is
port(a,b:in std_logic;c:out std_logic);
end andg;
architecture andg_arch of andg
is begin
c<=a and
b;
end andg_arch;
--HALF ADDER
library ieee;
use ieee.std_logic_1164.all;
entity ha is
port(a,b:in std_logic;s,c:out std_logic);
end ha;
architecture haa of ha
is begin
s<=a xor
b; c<=a and
b; end haa;
--FULL ADDER
library ieee;
use ieee.std_logic_1164.all;
entity fa is
port(a,b,c:in std_logic;s,ca:out std_logic);
end fa;
architecture fa_arch_data of fa
is begin
s<=a xor b xor c;
ca<=(a and b)or(c and b)or(a and c) ;
end fa_arch_data;
--ARRARY MULTIPLIER
--STRUCTURAL MODELLING
library ieee;
use ieee.std_logic_1164.all;
entity am is
port(a,b:in std_logic_vector(3 downto 0);p:out std_logic_vector(7 downto 0));
end am;
architecture ama of am is
signal x:std_logic_vector(15 downto
0); signal s:std_logic_vector(5 downto
0); signal c:std_logic_vector(10
downto 0); component andg
port(a,b:in std_logic;c:out
std_logic);
end component;
component ha
port(a,b:in std_logic;s,c:out
std_logic);
end component;
component fa
port(a,b,c:in std_logic;s,ca:out
std_logic);
end component;
begin
a1:andg port map(a(0),b(0),x(0));
a2:andg port map(a(1),b(0),x(1));
a3:andg port map(a(2),b(0),x(2));
a4:andg port map(a(3),b(0),x(3));
a5:andg port map(a(0),b(1),x(4));
a6:andg port map(a(1),b(1),x(5));
a7:andg port map(a(2),b(1),x(6));
a8:andg port map(a(3),b(1),x(7));
a9:andg port map(a(0),b(2),x(8));
a10:andg port
map(a(1),b(2),x(9));
a11:andg port
map(a(2),b(2),x(10));
a12:andg port map(a(3),b(2),x(11));
a13:andg port map(a(0),b(3),x(12));
a14:andg port map(a(1),b(3),x(13));
a15:andg port map(a(2),b(3),x(14));
a16:andg port map(a(3),b(3),x(15));
ha1:ha port map(x(1),x(4),p(1),c(0));
fa1:fa port map(c(0),x(5),x(2),s(0),c(1));
fa2:fa port map(c(1),x(6),x(3),s(1),c(2));
ha2:ha port map(c(2),x(7),s(2),c(3));
ha3:ha port map(x(8),s(0),p(2),c(4));
fa3:fa port map(c(4),x(9),s(1),s(3),c(5));
fa4:fa port
map(c(5),x(10),s(2),s(4),c(6)); fa5:fa
port map(x(11),c(3),c(6),s(5),c(7));
ha4:ha port map(x(12),s(3),p(3),c(8));
fa6:fa port
map(c(8),x(13),s(4),p(4),c(9));
fa7:fa port
map(c(9),x(14),s(5),p(5),c(10)); fa8:fa
port map(c(10),x(15),c(7),p(6),p(7));
p(0)<=x(0);
end ama;
OUTPUT:
Viva Questions:
1. What is a array multiplier
2. What type of adders and subtractors needed to built array multiplier.
3. What is partial product generation in array multiplier?
4. What are the advantages of array multiplier?
5. How delay is associated with array multiplier.
RESULT:
Thus 4X4 array multiplication was simulated and implemented using Modelsim software and
Spartan FPGA kit.
