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Exercise 4

The document discusses the benefits of relaxed memory consistency models, stating that they allow for operations to be executed in a non-strict sequence while maintaining functionality. It explains that memory consistency models are necessary for out-of-order cores but not for in-order cores, and that data races can be avoided with the DRF=SC model, which guarantees sequential consistency without the need for additional synchronization. Additionally, the document includes cycles illustrating optimized sequential consistency and processor consistency in multiprocessor architecture.

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18 views3 pages

Exercise 4

The document discusses the benefits of relaxed memory consistency models, stating that they allow for operations to be executed in a non-strict sequence while maintaining functionality. It explains that memory consistency models are necessary for out-of-order cores but not for in-order cores, and that data races can be avoided with the DRF=SC model, which guarantees sequential consistency without the need for additional synchronization. Additionally, the document includes cycles illustrating optimized sequential consistency and processor consistency in multiprocessor architecture.

Uploaded by

christopherjohnwilliams98
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Introduction to Multiprocessor Architecture (CS307)

Fall Semester 2022

Student: Christopher Williams


Sciper: 300174

EXERCISE 04
___

Questions

1. What is the benefit of relaxed memory consistency models? [1]


Many sets of operations that are sequentially organized in a program do not necessarily need
to be strictly sequential in order to function properly.

2. Are memory consistency models required in a single-core scenario (consider in-order


and out-of-order core)? Is it possible to detect memory re-orderings in a modern
out-of-order core while running only a single thread? Explain. [2]

Memory consistency models are not required for in-order, however they are required for
out-of-order core, as they employ dynamic scheduling. It is not possible to detect
re-orderings on a single thread with OoOE because, by principle, detectable weirdness can
only occur when loading memory that is being written to by other cores, without the presence
of these cores, we can assume and observe that the program has no side effects, and that it
runs as if each instruction was in order.

3. Define ‘DRF=SC’ model. What are the benefits of this model? [1]

The model states that code must not contain any data races to start with, as it can be
prevented using correctly synchronized and labeled code. The benefits are that SC is
guaranteed regardless of the environment that compiles and runs the code, while removing
the need for fences and barriers in the code.
4. Optimized sequential consistency

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 100


LSQ LSQ LSQ LSQ LSQ LSQ
LD A (P) ST H (P)
LD B (P) LD B LD A
ST D (P) ST A (P) ST C (P) ST C ST C LD B
SB SB SB SB SB SB
ST A ST A ST A ST C
ST D ST D ST D ST D ST A

Cycle 101 Cycle 102 Cycle 103 Cycle 104 Cycle 105 Cycle 200
LSQ LSQ LSQ LSQ LSQ LSQ
ST H ST H LD E(P) LD F(P) ST G(P) ST G
LD A LD A ST H LD E LD F LD F
LD B LD B LD A ST H LD E LD E
SB SB SB SB SB SB

ST C STH

Cycle 201 Cycle 202 Cycle 203 Cycle 204 Cycle 205 Cycle 301
LSQ LSQ LSQ LSQ LSQ LSQ
ST B(P) LD B
ST G ST B LD B
LD F ST G ST B LD B LD B LD B
SB SB SB SB SB SB
STB
ST G ST G ST B

Cycle 302: empty


Processor consistency

Cycle 0 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 100


LSQ LSQ LSQ LSQ LSQ LSQ
LD A (P) ST H (P)
LD B (P) LD B LD A
ST D (P) ST A (P) ST C (P) ST C ST C LD B
SB SB SB SB SB SB
ST A ST A ST A ST C
ST D ST D ST D ST D ST A

Cycle 101 Cycle 102 Cycle 103 Cycle 104 Cycle 105 Cycle 106
LSQ LSQ LSQ LSQ LSQ LSQ
LD E(P) LD F ST G(P) ST B(P) LD B(P)
ST H LD E LD F ST G ST B LD B
LD A ST H LD E LD F ST G ST B
SB SB SB SB SB SB
ST G
ST C ST H ST H STH ST H

Cycle 200 Cycle 201 Cycle 203 Cycle 204 Cycle Cycle
LSQ LSQ LSQ LSQ LSQ LSQ

LD B
SB SB SB SB SB SB
ST B ST B
ST G ST G ST G

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