Understanding SPI Communication in L9026
Serial Peripheral Interface (SPI) is a crucial protocol for data transfer between devices. This
presentation will explore its key components, functionality, and advanced features.
SPI Basics
Master Device Controls the communication, typically a microcontroller.
Slave Device Responds to master, often sensors or ICs.
Full-Duplex Communication Allows simultaneous data sending and receiving.
Key SPI Signals
MOSI (Master Out Slave In) Data sent from master to slave.
MISO (Master In Slave Out) Data sent from slave to master.
CLK (Clock) Synchronizes data transfer between devices.
NCS (Chip Select) Activates the slave device (low = active, high = inactive).
SPI Communication Process
1. Start Master pulls NCS line low to begin communication.
2. Clock Timing Data sent (shifted out) at falling edge, read (sampled) at rising edge of clock.
3. End Master sets NCS high to conclude communication.
SPI Frame Validity and Error Detection
16-Bit Minimum Rule Frames must contain at least 16 bits. Shorter frames are discarded and ERR
(error) flag is set.
Parity Bit Uses odd parity. Total number of 1s in frame must be odd otherwise ERR (error) flag is set.
Frame Counter Increments with each transmission. Incorrect counter sets ERR flag.
Special SPI Modes
Limp Home Mode SPI is read-only. Master can only read data from slave.
Sleep Mode SPI is disabled. MISO pin remains in high-impedance state (like it’s disconnected).
Daisy Chain Mode Multiple slave devices connected in series to a single master.
Daisy Chain Capability
In a daisy chain, multiple slave devices are connected in series to a single master.
The master sends data down a single MOSI line, and each device passes its data along the chain to the
next device. The final data comes back to the master on the MISO line.
Conditions for Daisy Chain:
All devices must use CPOL = 0, CPHA = 0.
Each device in the chain must receive and process its frame without errors.
SPI Frame Structure
MOSI Frame
1 command bit (R/W)
5 ADDRESS bits
8 DATA bits
1 PARITY bit
1 FR_CNT frame counter bit
MISO Frame
1 ERR error bit
5 ADDRESS bits
8 DATA bits
1 PARITY bit
1 FR_CNT frame counter bit
SPI Registers
1. CHIP_ID Register: Identifies the chip with a unique ID for recognition.
2. CFG_0 Register (Configuration 0): Configures channel modes and masks certain pins.
3. CFG_1 Register (Configuration 1): OUTn (Read-Write): 0: Channel operates as a low-side driver.
1: Channel operates as a high-side driver.
DIS_EN (Read-Write): 0: Mask DIS pin. 1: Enable DIS pin to disable all channels externally.
NRES_EN (Read-Write): 0: Mask NRES pin. 1: Enable NRES pin to reset the device externally.
RST (Write-Only): 0: Normal operation. 1: Execute reset command (self-clearing).
PWM_DIV_LED (Read-Write): Sets the PWM frequency for LED:
00: 122.5 Hz.
01: 245.1 Hz.
10: 490.2 Hz.
11: 980.4 Hz.
ACT (Read-Write): 0: Leave active mode. 1: Enter and hold in active mode.
4. CFG_2 Register (Configuration 2): Fine-tunes PWM generator frequencies.
5. BIM Register (Bulb Inrush Mode): Configures inrush current behavior for all channels. OUTn
(Read-Write):
0: BIM inactive.
1: Enable BIM for the channel.
FR_ADJ (Read-Write): Adjusts PWM frequency:
00: No adjustment.
01: -15%.
10: +15%.
11: No adjustment.
PWM_DIV_GEN (Read-Write): Sets PWM frequency for general-purpose channels:
00: 122.5 Hz.
01: 245.1 Hz.
10: 490.2 Hz.
11: 980.4 Hz.
6. PWM_SPI Register: Controls power outputs via SPI. OUTn (Read-Write):
0: Channel output is OFF
1: Channel output is ON
7. Mapping Registers (MAP_IN0, MAP_IN1, MAP_PWM): Maps input pins or PWM generators to
channels.
IN0: 0x04 (OUT2 mapped to IN0).
IN1: 0x08 (OUT3 mapped to IN1).
OUTn (Read-Write):
0: Not driven by input/PWM.
1: Driven by input/PWM.
8. PWM_GEN_DC/ PWM_LED_DC: PWM GEN/LED duty cycle setting.
B00000000: PWM GEN OFF
B11111111: PWM GEN fully ON
Diagnostic Registers Monitor faults like overcurrent, open load, and short circuits. OUTn (Read-Latch or
Write):
DIAG_OVC_OVT: Flags overcurrent or overtemperature.
DIAG_OPL_OFF: Detects open load in OFF state.
DIAG_OPL_ON: Detects open load in ON state.
DIAG_SHG: Detects shorted loads.
Provide real-time status of the device, including power conditions and operating mode.
Status Registers STA_0:
DIS, IDLE, IN1, IN0 (Read-Only): Echo the status of inputs.
OUT_ON_ERR/OUT_OFF_ERR (Read-Latch Reset): Flag errors like overcurrent or diagnostic failure.
STA_1:
POR, VDDIO_UV, VBATT_UV (Read-Latch Reset): Monitor power-on reset and undervoltage conditions.
MODE (Read-Only): Indicates operating mode:
00: Sleep Mode.
01: Limp Home Mode.
10: Idle Mode.
11: Active Mode.
SPI Timing Diagram
NCS (Chip Select)
Starts low to indicate the beginning of a communication session.
Goes high at the end of the session.
CLK (Clock)
Starts low when idle (CPOL = 0).
Rising edge: Data is sampled from MOSI.
Falling edge: Data is shifted out on MISO.
A square wave that synchronizes the data transfer.
MOSI & MISO
MOSI shows the bits sent by the master.
MISO displays bits shifted out by the slave.
Each bit is stable before the rising edge of CLK (tMOSI_SETUP) and held briefly after (tMOSI_HOLD).
Data becomes valid after the falling edge of CLK (tMISO_DELAY).
Important Timing Parameters
SPI communication is synchronized via the clock (CLK). The critical timing parameters include:
Clock Polarity (CPOL = 0): CLK starts low when idle.
Clock Phase (CPHA = 0): Data is:
Sampled (read) at the rising edge of CLK.
Shifted out (sent) at the falling edge of CLK.
tNCS_LOW: Duration NCS stays low during communication.
tMOSI_SETUP: Time MOSI data is valid before CLK rising edge.
tMOSI_HOLD: Time MOSI data remains valid after CLK rising edge.
tMISO_DELAY: Delay from CLK falling edge until MISO data is valid.
Topic Ends!
