PRELIMINARY TECHNICAL DATA

a Active and Apparent Energy Metering IC

with di/dt sensor interface
Preliminary Technical Data ADE7753*
FEATURES precise phase matching between the current and voltage
High Accuracy, supports IEC 61036 and IEC61268 channels. The integrator can be switched on and off based on
On-Chip Digital Integrator enables direct interface with the current sensor selected.
current sensors with di/dt output The ADE7753 contains an Active Energy register. It is
The ADE7753 supplies Active, Reactive and Apparent capable of holding more than 200 seconds of accumulated
Energy, Sampled Waveform, Current and Voltage RMS power at full load. Data is read from the ADE7753 via the
Less than 0.1% error over a dynamic range of 1000 to 1 serial interface. The ADE7753 also provides a pulse output
Positive only energy accumulation mode available (CF) with output frequency is proportional to the active
An On-Chip user Programmable threshold for line power.
voltage surge and SAG, and PSU supervisory In addition to rms calculation and active and apparent power
Digital Power, Phase & Input Offset Calibration information, the ADE7753 also accumulates the signed
An On-Chip temperature sensor (±3°C typical) reactive energy. The ADE7753 also provides various system
A SPI compatible Serial Interface calibration features, i.e., channel offset correction, phase
A pulse output with programmable frequency calibration and power calibration. The part also incorporates
An Interrupt Request pin (IRQ) and Status register a detection circuit for short duration low or high voltage
Proprietary ADCs and DSP provide high accuracy data over variations.
large variations in environmental conditions and time The ADE7753 has a positive only accumulation mode which
Reference 2.4V±8% (20 ppm/°C typical) gives the option to accumulate energy only when positive
with external overdrive capability power is detected. An internal no-load threshold ensures that
Single 5V Supply, Low power (25mW typical) the part does not exhibit any creep when there is no load.
A zero crossing output (ZX) produces an output which is
GENERAL DESCRIPTION synchronized to the zero crossing point of the line voltage.
The ADE7753 is an accurate active and apparent energy This information is used in the ADE7753 to measure the
measurements IC with a serial interface and a pulse output. line's period. The signal is also used internally to the chip in
The ADE7753 incorporates two second order sigma delta the line cycle Active and Apparent energy accumulation
ADCs, a digital integrator (on CH1), reference circuitry, mode. This enables a faster and more precise energy accumu-
temperature sensor, and all the signal processing required to lation and is useful during calibration. This signal is also
perform RMS calculation on the voltage and current, active, useful for synchronization of relay switching with a voltage
reactive, and apparent energy measurement. zero crossing.
An on-chip digital integrator provides direct interface to di/ The interrupt request output is an open drain, active low logic
dt current sensors such as Rogowski coils. The digital output. The Interrupt Status Register indicates the nature of
integrator eliminates the need for external analog integrator, the interrupt, and the Interrupt Enable Register controls
and this solution provides excellent long-term stability and which event produces an output on the IRQ pin.
The ADE7753 is available in 20-lead SSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD RESET DVDD DGND

PGA INTEGRATOR MULTIPLIER LPF2 WGAIN[11:0] ADE7753

V1P +
V1N -
ADC 冮dt Σ
HPF
CFNUM[11:0]
TEMP APOS[15:0]
SENSOR PHCAL[5:0]
DFC CF
Φ
IRMSOS[11:0] CFDEN[11:0]

VAGAIN[11:0]
: Σ
PGA ZX
VRMSOS[11:0]
V2P + SAG
ADC : Σ
V2N - VADIV[7:0] WDIV[7:0]
LPF1

4kΩ
2.4V
ADE7753 REGISTERS &
REFERENCE SERIAL INTERFACE

AGND REF IN/OUT CLKIN CLKOUT DIN DOUT SCLK CS IRQ

*U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469; others Pending.

REV. PrF 10/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
 PRELIMINARY TECHNICAL DATA
ADE7753–SPECIFICATIONS1,3 (AVDD = DVDD = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,
CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)
Parameter Spec Units Test Conditions/Comments

ENERGY MEASUREMENT ACCURACY

Measurement Bandwidth 14 kHz CLKIN = 3.579545 MHz
Measurement Error1 on Channel 1 Channel 2 = 300mV rms/60Hz, Gain = 2
Channel 1 Range = 0.5V full-scale
Gain = 1 0.1 % typ Over a dynamic range 1000 to 1
Gain = 2 0.1 % typ Over a dynamic range 1000 to 1
Gain = 4 0.1 % typ Over a dynamic range 1000 to 1
Gain = 8 0.1 % typ Over a dynamic range 1000 to 1
Gain = 16 0.2 % typ Over a dynamic range 1000 to 1
Channel 1 Range = 0.25V full-scale
Gain = 1 0.1 % typ Over a dynamic range 1000 to 1
Gain = 2 0.1 % typ Over a dynamic range 1000 to 1
Gain = 4 0.1 % typ Over a dynamic range 1000 to 1
Gain = 8 0.2 % typ Over a dynamic range 1000 to 1
Gain = 16 0.2 % typ Over a dynamic range 1000 to 1
Channel 1 Range = 0.125V full-scale
Gain = 1 0.1 % typ Over a dynamic range 1000 to 1
Gain = 2 0.1 % typ Over a dynamic range 1000 to 1
Gain = 4 0.2 % typ Over a dynamic range 1000 to 1
Gain = 8 0.2 % typ Over a dynamic range 1000 to 1
Gain = 16 0.4 % typ Over a dynamic range 1000 to 1
Phase Error1 Between Channels ±0.05 ° max Line Frequency = 45Hz to 65Hz, HPF on
AC Power Supply Rejection1 AVDD = DVDD = 5V+175mV rms/ 120Hz
Output Frequency Variation (CF) 0.2 % typ Channel 1 = 20mV rms, Gain = 16, Range = 0.5V
Channel 2 = 300mV rms/60Hz, Gain = 1
DC Power Supply Rejection1 AVDD = DVDD = 5V ± 250mV dc
Output Frequency Variation (CF) ±0.3 % typ Channel 1 = 20mV rms/60Hz, Gain = 16, Range = 0.5V
Channel 2 = 300mV rms/60Hz, Gain = 1
ANALOG INPUTS See Analog Inputs Section
Maximum Signal Levels ±0.5 V max V1P, V1N, V2N and V2P to AGND
Input Impedance (dc) 390 kΩ min
Bandwidth 14 kHz CLKIN/256, CLKIN = 3.579545MHz
Gain Error1,4 External 2.5V reference, Gain = 1 on Channel 1 & 2
Channel 1
Range = 0.5V full-scale ±4 % typ V1 = 0.5V dc
Range = 0.25V full-scale ±4 % typ V1 = 0.25V dc
Range = 0.125V full-scale ±4 % typ V1 = 0.125V dc
Channel 2 ±4 % typ V2 = 0.5V dc
Gain Error Match1 External 2.5V reference
Channel 1
Range = 0.5V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16
Range = 0.25V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16
Range = 0.125V full-scale ±0.3 % typ Gain = 1, 2, 4, 8, 16
Channel 2 ±0.3 % typ Gain = 1, 2, 4, 8, 16
Offset Error1
Channel 1 ±10 mV max Channel 1 Range = 0.5V
Channel 2 ±10 mV max Channel 2 Range = 0.5V
WAVEFORM SAMPLING Sampling CLKIN/128, 3.579545MHz/128 = 27.9kSPS
Channel 1 See Channel 1 Sampling
Signal-to-Noise plus distortion 62 dB typ 150mV rms/60Hz, Range = 0.5V, Gain = 2
Bandwidth (-3dB) 14 kHz CLKIN = 3.579545MHz
Channel 2 See Channel 2 Sampling
Signal-to-Noise plus distortion 52 dB typ 150mV rms/60Hz, Gain = 2
Bandwidth (-3dB) 140 Hz CLKIN = 3.579545MHz

-2- REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
Parameter Spec Units Test Conditions/Comments

REFERENCE INPUT
REFIN/OUT Input Voltage Range 2.6 V max 2.4 V +8%
2.2 V min 2.4V -8%
Input Capacitance 10 pF max
ON-CHIP REFERENCE Nominal 2.4V at REFIN/OUT pin
Reference Error ±200 mV max
Current source 10 µA max
Output Impedance 4 kΩ min
Temperature Coefficient 20 ppm/°C typ
CLKIN Note all specifications CLKIN of 3.579545MHz
Input Clock Frequency 4 MHz max
1 MHz min
LOGIC INPUTS
RESET, DIN, SCLK, CLKIN and CS
Input High Voltage, VINH 2.4 V min DVDD = 5 V ± 10%
Input Low Voltage, VINL 0.8 V max DVDD = 5 V ± 10%
Input Current, IIN ±3 µA max Typically 10nA, VIN = 0V to DVDD
Input Capacitance, CIN 10 pF max
LOGIC OUTPUTS3
SAG & IRQ Open Drain outputs, 10kΩ pull up resistor
Output High Voltage, VOH 4 V min ISOURCE = 5mA
Output Low Voltage, VOL 0.4 V max ISINK = 0.8mA
ZX & DOUT
Output High Voltage, VOH 4 V min ISOURCE = 5mA
Output Low Voltage, VOL 0.4 V max ISINK = 0.8mA
CF
Output High Voltage, VOH 4 V min ISOURCE = 5mA
Output Low Voltage, VOL 1 V max ISINK = 7mA
POWER SUPPLY For specified Performance
AV DD 4.75 V min 5V - 5%
5.25 V max 5V +5%
DV DD 4.75 V min 5V - 5%
5.25 V max 5V + 5%
AI DD 3 mA max Typically 2.0 mA
DIDD 4 mA max Typically 3.0 mA
NOTES:
1
See Terminology Section for explanation of Specifications
2
See Plots in Typical Performance Graphs
3
Specifications subject to change without notice
4
See Analog Inputs Section

ORDERING GUIDE
IOL
MODEL Package Option*
200 µA
ADE7753ARS RS-20
TO ADE7753ARSRL RS-20
OUTPUT +2.1V EVAL-ADE7753EB ADE7753 evaluation board
PIN
CL * RS = Shrink Small Outline Package in tubes; RSRL = Shrink Small Outline
50pF Package in reel.
1.6 mA IOH

Load Circuit for Timing Specifications

REV. PrF 10/02 –3–

 PRELIMINARY TECHNICAL DATA
ADE7753
ADE7753 TIMING CHARACTERISTICS1,2 (AVDD = DVDD = 5V ± 5%, AGND = DGND = 0V, On-Chip Reference,
CLKIN = 3.579545MHz XTAL, TMIN to TMAX = -40°C to +85°C)
Parameter A,B Versions Units Test Conditions/Comments

Write timing
t1 20 ns (min) CS falling edge to first SCLK falling edge
t2 150 ns (min) SCLK logic high pulse width
t3 150 ns (min) SCLK logic low pulse width
t4 10 ns (min) Valid Data Set up time before falling edge of SCLK
t5 5 ns (min) Data Hold time after SCLK falling edge
t6 TBD ns (min) Minimum time between the end of data byte transfers.
t7 TBD ns (min) Minimum time between byte transfers during a serial write.
t8 100 ns (min) CS Hold time after SCLK falling edge.
Read timing
t9 3.1 us (min) Minimum time between read command (i.e. a write to Communication
Reigster) and data read.
t10 TBD ns (min) Minimum time between data byte transfers during a multibyte read.
t113 30 ns (min) Data access time after SCLK rising edge following a write to the
Communications Register
t124 100 ns (max) Bus relinquish time after falling edge of SCLK.
10 ns (min)
t 13 4 100 ns (max) Bus relinquish time after rising edge of CS.
10 ns (min)

NOTES
1
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are specified with tr = tf = 5ns (10% to 90%)
and timed from a voltage level of 1.6V.
2
See timing diagram below and Serial Interface section of this data sheet.
3
Measured with the load circuit in Figure 1 and defined as the time required for the output to cross 0.8V or 2.4V.
4
Derived from the measured time taken by the data outputs to change 0.5V when loaded with the circuit in Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part
and is independent of the bus loading.

Serial Write Timing

t8
CS
t1 t2 t3 t6
t7 t7
SCLK
t4
t5
DIN 1 0 0 A4 A3 A2 A1 A0 DB7 DB0 DB7 DB0

Command Byte Most Significant Byte Least Significant Byte

Serial Read Timing

CS
t1 t13
t9 t10
SCLK

DIN 0 0 0 A4 A3 A2 A1 A0
t11 t11 t12

DOUT DB7 DB0 DB7 DB0

Command Byte Most Significant Byte Least Significant Byte

–4– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
ABSOLUTE MAXIMUM RATINGS* Storage Temperature Range . . . . . . . . –65°C to +150°C
(TA = +25°C unless otherwise noted) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150°C
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V 20 Pin SSOP, Power Dissipation . . . . . . . . . . . . 450 mW
DVDD to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 112°C/W
DVDD toAVDD . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Lead Temperature, Soldering
Analog Input Voltage to AGND Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . +215°C
V1P, V1N, V2P and V2N . . . . . . . . . . . . . . . . . . -6V to +6V Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . +220°C
Reference Input Voltage to AGND . . . . –0.3 V to AVDD +
0.3 V *
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
Digital Input Voltage to DGND –0.3 V to DVDD + 0.3 V damage to the device. This is a stress rating only and functional operation of the device
Digital Output Voltage to DGND –0.3 V to DVDD + 0.3 V at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
Operating Temperature Range extended periods may affect device reliability.
Industrial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumu-
late on the human body and test equipment and can discharge without detection. Although the ADE7753
features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to
WARNING!
high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid
performance degradation or loss of functionality. ESD SENSITIVE DEVICE

Terminology
MEASUREMENT ERROR
The error associated with the energy measurement made by input signal levels when the supplies are varied ±5%. Any
the ADE7753 is defined by the following formula: error introduced is again expressed as a percentage of
reading.
Percentage Error =
 Energy registered by ADE 7753 − True Energy  ADC OFFSET ERROR
  × 100 %
True Energy This refers to the DC offset associated with the analog inputs
 
to the ADCs. It means that with the analog inputs connected
to AGND the ADCs still see a dc analog input signal. The
PHASE ERROR BETWEEN CHANNELS magnitude of the offset depends on the gain and input range
The digital integrator and the HPF (High Pass Filter) in selection - see characteristic curves. However, when HPF1 is
Channel 1 have non-ideal phase response. To offset this switched on the offset is removed from Channel 1 (current)
phase response and equalize the phase response between and the power calculation is not affected by this offset. The
channels, two phase correction network is placed in Channel offsets may be removed by performing an offset calibration -
1: one for the digital integrator and the other for the HPF. see Analog Inputs.
Each phase correction network corrects the phase response of
the corresponding component and ensures a phase match GAIN ERROR
between Channel 1 (current) and Channel 2 (voltage) to The gain error in the ADE7753 ADCs is defined as the
within ±0.1° over a range of 45Hz to 65Hz and ±0.2° over difference between the measured ADC output code (minus
a range 40Hz to 1kHz. the offset) and the ideal output code - see Channel 1 ADC &
Channel 2 ADC. It is measured for each of the input ranges
POWER SUPPLY REJECTION on Channel 1 (0.5V, 0.25V and 0.125V). The difference is
This quantifies the ADE7753 measurement error as a per- expressed as a percentage of the ideal code.
centage of reading when the power supplies are varied.
For the AC PSR measurement a reading at nominal supplies GAIN ERROR MATCH
(5V) is taken. A second reading is obtained with the same The Gain Error Match is defined as the gain error (minus the
input signal levels when an ac (175mV rms/120Hz) signal is offset) obtained when switching between a gain of 1 (for each
introduced onto the supplies. Any error introduced by this of the input ranges) and a gain of 2, 4, 8, or 16. It is expressed
AC signal is expressed as a percentage of reading—see as a percentage of the output ADC code obtained under a gain
Measurement Error definition above. of 1. This gives the gain error observed when the gain
For the DC PSR measurement a reading at nominal supplies selection is changed from 1 to 2, 4, 8 or 16.
(5V) is taken. A second reading is obtained with the same

REV. PrF 10/02 –5–

 PRELIMINARY TECHNICAL DATA
ADE7753
PIN FUNCTION DESCRIPTION

Pin No. MNEMONIC DESCRIPTION

1 RESET Reset pin for the ADE7753. A logic low on this pin will hold the ADCs and digital
circuitry (including the Serial Interface) in a reset condition.
2 DVDD Digital power supply. This pin provides the supply voltage for the digital circuitry in
the ADE7753. The supply voltage should be maintained at 5V ± 5% for specified op-
eration. This pin should be decoupled to DGND with a 10µF capacitor in parallel with
a ceramic 100nF capacitor.
3 AVDD Analog power supply. This pin provides the supply voltage for the analog circuitry in
the ADE7753. The supply should be maintained at 5V ± 5% for specified operation.
Every effort should be made to minimize power supply ripple and noise at this pin by
the use of proper decoupling. The typical performance graphs in this data sheet show
the power supply rejection performance. This pin should be decoupled to AGND with a
10µF capacitor in parallel with a ceramic 100nF capacitor.
4,5 V1P, V1N Analog inputs for Channel 1. This channel is intended for use with the di/dt current
transducer such as Rogowski coil or other current sensor such as shunt or current trans-
former (CT). These inputs are fully differential voltage inputs with maximum
differential input signal levels of ±0.5V, ±0.25V and ±0.125V, depending on the full
scale selection - See Analog Inputs. Channel 1 also has a PGA with gain selections of 1,
2, 4, 8 or 16. The maximum signal level at these pins with respect to AGND is ±0.5V.
Both inputs have internal ESD protection circuitry and in addition an overvoltage of
±6V can be sustained on these inputs without risk of permanent damage.
6,7 V2N, V2P Analog inputs for Channel 2. This channel is intended for use with the voltage trans-
ducer. These inputs are fully differential voltage inputs with a maximum differential
signal level of ±0.5V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8 or
16. The maximum signal level at these pins with respect to AGND is ±0.5V. Both
inputs have internal ESD protection circuitry, and an overvoltage of ±6V can be sus-
tained on these inputs without risk of permanent damage.
8 AGND This pin provides the ground reference for the analog circuitry in the ADE7753, i.e.
ADCs and reference. This pin should be tied to the analog ground plane or the quietest
ground reference in the system. This quiet ground reference should be used for all ana-
log circuitry, e.g. anti-aliasing filters, current and voltage transducers etc. In order to
keep ground noise around the ADE7753 to a minimum, the quiet ground plane should
only connected to the digital ground plane at one point. It is acceptable to place the
entire device on the analog ground plane - see Applications Information.
9 REFIN/OUT This pin provides access to the on-chip voltage reference. The on-chip reference has a
nominal value of 2.4V ± 8% and a typical temperature coefficient of 20ppm/°C. An
external reference source may also be connected at this pin. In either case this pin
should be decoupled to AGND with a 1µF ceramic capacitor.
10 DGND This provides the ground reference for the digital circuitry in the ADE7753, i.e. multi-
plier, filters and digital-to-frequency converter. Because the digital return currents in
the ADE7753 are small, it is acceptable to connect this pin to the analog ground plane
of the system - see Applications Information. However, high bus capacitance on the DOUT
pin may result in noisy digital current which could affect performance.
11 CF Calibration Frequency logic output. The CF logic output gives Active Power informa-
tion. This output is intended to be used for operational and calibration purposes. The
full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM
Register—see Energy To Frequency Conversion.
12 ZX Voltage waveform (Channel 2) zero crossing output. This output toggles logic high and
low at the zero crossing of the differential signal on Channel 2—see Zero Crossing Detection.
13 SAG This open drain logic output goes active low when either no zero crossings are detected
or a low voltage threshold (Channel 2) is crossed for a specified duration. See Line Volt-
age Sag Detection.
14 IRQ Interrupt Request Output. This is an active low open drain logic output. Maskable
interrupts include: Active Energy Register roll-over, Active Energy Register at half
level, and arrivals of new waveform samples. See ADE7753 Interrupts.

–6– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
Pin No. MNEMONIC DESCRIPTION
15 CLKIN Master clock for ADCs and digital signal processing. An external clock can be pro-
vided at this logic input. Alternatively, a parallel resonant AT crystal can be connected
across CLKIN and CLKOUT to provide a clock source for the ADE7753. The clock
frequency for specified operation is 3.579545MHz. Ceramic load capacitors of between
22pF and 33pF should be used with the gate oscillator circuit. Refer to crystal manu-
facturers data sheet for load capacitance requirements.
16 CLKOUT A crystal can be connected across this pin and CLKIN as described above to provide a
clock source for the ADE7753. The CLKOUT pin can drive one CMOS load when
either an external clock is supplied at CLKIN or a crystal is being used.
17 CS Chip Select. Part of the four wire SPI Serial Interface. This active low logic input al-
lows the ADE7753 to share the serial bus with several other devices. See ADE7753 Serial
Interface.
18 SCLK Serial Clock Input for the synchronous serial interface. All Serial data transfers are
synchronized to this clock—see ADE7753 Serial Interface. The SCLK has a schmitt-trigger
input for use with a clock source which has a slow edge transition time, e.g., opto-
isolator outputs.
19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin on the rising edge of
SCLK. This logic output is normally in a high impedance state unless it is driving data
onto the serial data bus—see ADE7753 Serial Interface..
20 DIN Data Input for the Serial Interface. Data is shifted in at this pin on the falling edge of
SCLK—see ADE7753 Serial Interface..

PIN CONFIGURATION
SSOP Packages

RESET 1 20 DIN

DVDD 2 19 DOUT

AVDD 3 18 SCLK

V1P 4 ADE7753 17 CS
TOP VIEW
V1N 5 16 CLKOUT
(Not to Scale)
V2N 6 15 CLKIN

V2P 7 14 IRQ

AGND 8 13 SAG

REFIN/OUT 9 12 ZX

DGND 10 11 CF

REV. PrF 10/02 –7–

 PRELIMINARY TECHNICAL DATA
ADE7753
Typical Performance Characteristics-ADE7753

TBD TBD

TPC 4— Error as a % of Reading (Full-Scale input for Chan-

nel 1=0.25V, Gain=4)
TPC 1— Error as a % of Reading (Gain=1)

TBD TBD

TPC 5— Error as a % of Reading (Full-scale input for Chan-

TPC 2— Error as a % of Reading (Gain=4) nel 1=0.125V, Gain=8)

TBD TBD
TPC 3— Error as a % of Reading (Gain=16) TPC 6— Test Circuits for Performance Curves
–8– REV. PrF 10/02
 PRELIMINARY TECHNICAL DATA
ADE7753
ANALOG INPUTS
The ADE7753 has two fully differential voltage input chan- GAIN REGISTER*
Channel 1 and Channel 2 PGA Control
nels. The maximum differential input voltage for input pairs 7 6 5 4 3 2 1 0
V1P/V1N and V2P/V2N are ±0.5V. In addition, the maxi-
0 0 0 0 0 0 0 0 ADDR: 0FH
mum signal level on analog inputs for V1P/V1N and V2P/
V2N are ±0.5V with respect to AGND. PGA 1 Gain Select
Each analog input channel has a PGA (Programmable Gain 000 = x1
PGA 2 Gain Select 001 = x2
Amplifier) with possible gain selections of 1, 2, 4, 8 and 16. 000 = x1 010 = x4
001 = x2 011 = x8
The gain selections are made by writing to the Gain regis- 010 = x4 100 = x16
ter—see Figure 2. Bits 0 to 2 select the gain for the PGA in 011 = x8
100 = x16
Channel 1 Full Scale Select
00 = 0.5V
Channel 1 and the gain selection for the PGA in Channel 2 *Register contents show power on defaults
01 = 0.25V
10 = 0.125V
is made via bits 5 to 7. Figure 1 shows how a gain selection
for Channel 1 is made using the Gain register.
Figure 2— ADE7753 Analog Gain register
GAIN[7:0]
It is also possible to adjust offset errors on Channel 1 and
Channel 2 by writing to the Offset Correction Registers
(CH1OS and CH2OS respectively). These registers allow
Gain (k)
V1P selection channel offsets in the range ±20mV to ±50mV (depending on
the gain setting) to be removed. Note that it is not necessary
Vin + to perform an offset correction in an Energy measurement
- k.Vin application if HPF in Channel 1 is switched on. Figure 3
Σ shows the effect of offsets on the real power calculation. As
V1N + can be seen from Figure 3, an offset on Channel 1 and
Offset Channel 2 will contribute a dc component after multiplica-
Adjust tion. Since this dc component is extracted by LPF2 to
(±50mV)
generate the Active (Real) Power information, the offsets will
CH1OS[7:0]
Bit 0 to 5: Sign magnitude coded offset correction
have contributed an error to the Active Power calculation.
Bit 6: Not used This problem is easily avoided by enabling HPF in Channel
Bit 7: Digital Integrator (On=1, Off=0; default ON) 1. By removing the offset from at least one channel, no error
component is generated at dc by the multiplication. Error
terms at Cos(w.t) are removed by LPF2 and by integration of
Figure 1— PGA in Channel 1 the Active Power signal in the Active Energy register (AEN-
ERGY[23:0]) – see Energy Calculation.
In addition to the PGA, Channel 1 also has a full scale input
range selection for the ADC. The ADC analog input range DC component (including error term) is
extracted by the LPF for real power
selection is also made using the Gain register—see Figure 2. calculation
As mentioned previously the maximum differential input VOS.IOS
voltage is 1V. However, by using bits 3 and 4 in the Gain V.I
register, the maximum ADC input voltage can be set to 0.5V, 2

0.25V or 0.125V. This is achieved by adjusting the ADC

reference—see ADE7753 Reference Circuit. Table I below sum- IOS.V
marizes the maximum differential input signal level on VOS.I
Channel 1 for the various ADC range and gain selections. 0 ω 2ω
frequency (rad/s)

Figure 3— Effect of channel offsets on the real power cal-

culation
Table I The contents of the Offset Correction registers are 6-Bit, sign
Maximum input signal levels for Channel 1 and magnitude coded. The weighting of the LSB size
depends on the gain setting, i.e., 1, 2, 4, 8 or 16. Table II
Max Signal ADC Input Range Selection below shows the correctable offset span for each of the gain
Channel 1 0.5V 0.25V 0.125V settings and the LSB weight (mV) for the Offset Correction
registers. The maximum value which can be written to the
0.5V Gain = 1 — — offset correction registers is ±31 decimal —see Figure 4.
0.25V Gain = 2 Gain = 1 — Figure 4 shows the relationship between the Offset Correc-
0.125V Gain = 4 Gain = 2 Gain = 1 tion register contents and the offset (mV) on the analog inputs
0.0625V Gain = 8 Gain = 4 Gain = 2 for a gain setting of one. In order to perform an offset
0.0313V Gain = 16 Gain = 8 Gain = 4 adjustment, The analog inputs should be first connected to
0.0156V — Gain = 16 Gain = 8 AGND, and there should be no signal on either Channel 1
0.00781V — — Gain = 16 or Channel 2. A read from Channel 1 or Channel 2 using the
REV. PrF 10/02 –9–
 PRELIMINARY TECHNICAL DATA
ADE7753
Table II The current signal needs to be recovered from the di/dt signal
Offset Correction range before it can be used. An integrator is therefore necessary to
restore the signal to its original form. The ADE7753 has a
Gain Correctable Span LSB Size built-in digital integrator to recover the current signal from
the di/dt sensor. The digital integrator on Channel 1 is
1 ±50mV 1.61mV/LSB switched off by default when the ADE7753 is powered up.
2 ±37mV 1.19mV/LSB Setting the MSB of CH1OS register will turn on the
4 ±30mV 0.97mV/LSB integrator. Figures 6 to 9 show the magnitude and phase
8 ±26mV 0.84mV/LSB response of the digital integrator.
16 ±24mV 0.77mV/LSB
10

Waveform register will give an indication of the offset in the

channel. This offset can be canceled by writing an equal and 0

opposite offset value to the relevant offset register. The offset

correction can be confirmed by performing another read. -10

Note when adjusting the offset of Channel 1, one should

GAIN-dB
disable the digital integrator and the HPF. -20

-30
CH1OS[5:0]

1Fh 01, 1111b Sign + 5 Bits -40

-50
2 3
10 10
FREQUENCY-Hz

00h
-50mV 0mV
+50mV Figure 6– Combined gain response of the digital integrator
Offset and phase compensator
Adjust

-88
3Fh 11, 1111b Sign + 5 Bits

-88.5

Figure 4– Channel Offset Correction Range (Gain = 1)

PHASE-DEGREES

-89

-89.5

di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR

di/dt sensor detects changes in magetic field caused by ac -90

current. Figure 5 shows the principle of a di/dt current

sensor. -90.5
10
2
10
3

FREQUENCY-Hz

Magnetic field created by current

Figure 7– Combined phase response of the digital integra-
(directly propor tional to current) tor and phase compensator

-1

-1.5

+ EMF (electromotive force) -2

- induced by changes in -2.5

magnetic flux density (d/dt)
-3

Figure 5– Principle of a di/dt current sensor

GAIN-dB

-3.5

-4

The flux density of a magnetic field induced by a current is -4.5

directly proportional to the magnitude of the current. The -5

changes in the magnetic flux density passing through a -5.5

conductor loop generates an electromotive force (EMF)

-6
between the two ends of the loop. The EMF is a voltage signal 40 45 50 55
FREQUENCY-Hz
60 65 70

which is proportional to the di/dt of the current. The voltage

output from the di/dt current sensor is determined by the Figure 8– Combined gain response of the digital integrator
mutual inductance between the current carrying conductor and phase compensator (40Hz to 70Hz)
and the di/dt sensor.

–10– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
The phase response of this filter is shown in the Channel 2
-89.7 Sampling section of this data sheet. The phase lag response of
-89.75
LPF1 results in a time delay of approximately 0.97ms (@
60Hz) between the zero crossing on the analog inputs of
-89.8
Channel 2 and the rising or falling edge of ZX.
-89.85
The zero-crossing detection also drives one flag bit in the
PHASE-DEGREES

interrupt status register. An active low in the IRQ output will

-89.9
also appear if the corresponding bit in the Interrupt Enable
-89.95 register is set to logic one.
The flag in the Interrupt status register as well as the IRQ
-90
output are reset to their default value when the Interrupt
-90.05 Status register with reset (RSTSTATUS) is read.
40 45 50 55 60 65 70
Zero Crossing Timeout
FREQUENCY-Hz
The zero crossing detection also has an associated time-out
register ZXTOUT. This unsigned, 12-bit register is
Figure 9– Combined phase response of the digital integra-
decremented (1 LSB) every 128/CLKIN seconds. The reg-
tor and phase compensator (40Hz to 70Hz)
ister is reset to its user programmed full scale value every time
a zero crossing on Channel 2 is detected. The default power
Note that the integrator has a -20dB/dec attenuation and on value in this register is FFFh. If the register decrements
approximately -90° phase shift. When combined with a di/dt to zero before a zero crossing is detected and the DISSAG bit
sensor, the resulting magnitude and phase response should be in the Mode register is logic zero, the SAG pin will go active
a flat gain over the frequency band of interest. However, the low. The absence of a zero crossing is also indicated on the
di/dt sensor has a 20dB/dec gain associated with it, and IRQ pin if the ZXTO enable bit in the Interrupt Enable
generates significant high frequency noise, a more effective register is set to logic one. Irrespective of the enable bit
anti-aliasing filter is needed to avoid noise due to aliasing— setting, the ZXTO flag in the Interrupt Status register is
see Antialias Filter. always set when the ZXTOUT register is decremented to
When the digital integrator is switched off, the ADE7753 can zero - see ADE7753 Interrupts.
be used directly with a conventional current sensor such as The Zerocross Time-out register can be written/read by the
current transformer (CT) or a low resistance current shunt. user and has an address of 1Dh - see Serial Interface section. The
ZERO CROSSING DETECTION resolution of the register is 128/CLKIN seconds per LSB.
The ADE7753 has a zero crossing detection circuit on Thus the maximum delay for an interrupt is 0.15 second
Channel 2. This zero crossing is used to produce an external (128/CLKIN × 212).
zero cross signal (ZX) and it is also used in the calibration Figure 11 shows the mechanism of the zero crossing time out
mode - see Energy Calibration. The zero crossing signal is also detection when the line voltage stays at a fixed DC level for
used to initiate a temperature measurement on the ADE7753 more than CLKIN/128 x ZXTOUT seconds.
- see Temperature Measurement.
Figure 10 shows how the zero cross signal is generated from 16-bit internal
register value
the output of LPF1. ZXTOUT

REFERENCE
x1, x2, x4,
x8, x16 TO
Channel 2
V2P GAIN[7:5] MULTIPLIER
1 -63% to + 63% FS
V2 PGA2 ADC 2
V2N

ZERO ZXTO
ZX
CROSS detection bit
LPF1
f-3dB = 140Hz
23.2 8@ 60Hz
1.0
0.92
ZX Figure 11 - Zero crossing Time out detection

PERIOD MEASUREMENT
V2 LPF1
The ADE7753 provides also the period measurement of the
line. The period register is an unsigned 15-bit register and is
Figure 10– Zero cross detection on Channel 2 updated every period.
The ZX signal will go logic high on a positive going zero The resolution of this register is 2.2ms/LSB when
crossing and logic low on a negative going zero crossing on CLKIN=3.579545MHz, which represents 0.013% when the
Channel 2. The zero crossing signal ZX is generated from the line frequency is 60Hz. When the line frequency is 60Hz, the
output of LPF1. LPF1 has a single pole at 156Hz (at CLKIN value of the Period register is approximately 7576d. The
= 3.579545MHz). As a result there will be a phase lag length of the register enables the measurement of line
between the analog input signal V2 and the output of LPF1. frequencies as low as 13.9Hz.
REV. PrF 10/02 –11–
 PRELIMINARY TECHNICAL DATA
ADE7753
POWER SUPPLY MONITOR tains 03h the SAG pin will go active low at the end of the fifth
The ADE7753 also contains an on-chip power supply moni- line cycle for which the line voltage falls below the threshold,
tor. The Analog Supply (AVDD) is continuously monitored if the DISSAG bit in the Mode register is logic zero. As is
by the ADE7753. If the supply is less than 4V ± 5% then the the case when zero-crossings are no longer detected, the sag
ADE7753 will go into an inactive state, i.e. no energy will be event is also recorded by setting the SAG flag in the Interrupt
accumulated when the supply voltage is below 4V. This is Status register. If the SAG enable bit is set to logic one, the
useful to ensure correct device operation at power up and IRQ logic output will go active low - see ADE7753 Interrupts.
during power down. The power supply monitor has built-in The SAG pin will go logic high again when the absolute value
hysteresis and filtering. This gives a high degree of immunity of the signal on Channel 2 exceeds the sag level set in the Sag
to false triggering due to noisy supplies. Level register. This is shown in Figure 13 when the SAG pin
goes high during the tenth line cycle from the time when the
signal on Channel 2 first dropped below the threshold level.
AVDD
Sag Level Set
5V The contents of the Sag Level register (1 byte) are compared
4V to the absolute value of the most significant byte output from
LPF1, after it is shifted left by one bit. Thus for example the
nominal maximum code from LPF1 with a full scale signal
0V
on Channel 2 is 2518h—see Channel 2 sampling. Shifting one
Time bit left will give 4A30h. Therefore writing 4Ah to the SAG
ADE7753 Level register will put the sag detection level at full scale.
Power-on
Inactive Inactive Active Inactive Writing 00h will put the sag detection level at zero. The Sag
State Level register is compared to the most significant byte of a
waveform sample after the shift left and detection is made
SAG when the contents of the sag level register are greater.

PEAK DETECTION
Figure 12 - On-Chip power supply monitor
The ADE7753 can also be programmed to detect when the
As can be seen from Figure 12 the trigger level is nominally absolute value of the voltage or the current channel of one
set at 4V. The tolerance on this trigger level is about ±5%. phase exceeds a certain peak value. Figure 14 illustrates the
The SAG pin can also be used as a power supply monitor behavior of the peak detection for the voltage channel.
input to the MCU. The SAG pin will go logic low when the
ADE7753 is in its inactive state. The power supply and V2

decoupling for the part should be such that the ripple at VPKLVL[7:0]
AV DD does not exceed 5V±5% as specified for normal
operation.

LINE VOLTAGE SAG DETECTION PKV reset low

In addition to the detection of the loss of the line voltage when RSTSTATUS register
is read
signal (zero crossing), the ADE7753 can also be pro-
grammed to detect when the absolute value of the line voltage
drops below a certain peak value, for a number of line cycles. PKV Interrupt Flag
(Bit 8 of STATUS register)
This condition is illustrated in Figure 13 below.
Read RSTSTATUS register

Channel 2
Full Scale
Figure 14 - ADE7753 Peak detection

SAGLVL[7:0] Both channel 1 and channel 2 are monitored at the same time.
Figure 14 shows a line voltage exceeding a threshold which
is set in the Voltage peak register (VPKLVL[7:0]). The
SAG reset high
when Channel 2
Voltage Peak event is recorded by setting the PKV flag in the
SAGCYC[7:0] = 06H
exceeds SAGLVL[7:0] Interrupt Status register. If the PKV enable bit is set to logic
6 half cycles one in the Interrupt Mask register, the IRQ logic output will
go active low. Similarly, the Current Peak event is recorded
SAG by setting the PKI flag in the Ineterrupt Status register—see
ADE7753 Interrupts.
Peak Level Set
Figure 13– ADE7753 Sag detection The contents of the VPKLVL and IPKLVL registers are
respectively compared to the absolute value of channel 1 and
Figure 13 shows the line voltage fall below a threshold which channel 2, after they are multiplied by 2.
is set in the Sag Level register (SAGLVL[7:0]) for five line
cycles. Since the Sag Cycle register (SAGCYC[7:0]) con-
–12– REV. PrF 10/02
 PRELIMINARY TECHNICAL DATA
ADE7753
Thus, for example, the nominal maximum code from the read command—see Interrupt timing. When carrying out a read
channel 1 ADC with a full scale signal is 2851ECh —see with reset, the ADE7753 is designed to ensure that no
Channel 1 Sampling. Multiplying by 2 will give 50A3D8h. interrupt events are missed. If an interrupt event occurs just
Therefore, writing 50h to the IPKLVL register will put the as the Status register is being read, the event will not be lost
channel 1 peak detection level at full scale and set the current and the IRQ logic output is guaranteed to go high for the
peak detection to its least sensitive value. duration of the Interrupt Status register data transfer before
Writing 00h will put the channel 1 detection level at zero. going logic low again to indicate the pending interrupt. See
The detection is done when the content of the IPKLVL the next section for a more detailed description.
register is smaller than the incoming channel 1 sample. Using the ADE7753 Interrupts with an MCU
Peak Level Record Shown in Figure 15 is a timing diagram which shows a
The ADE7753 records the maximum absolute value reached suggested implementation of ADE7753 interrupt manage-
by channel 1 and channel 2 in two different registers - IPEAK ment using an MCU. At time t1 the IRQ line will go active
and VPEAK respectively. VPEAK and IPEAK are 24-bit low indicating that one or more interrupt events have oc-
unsigned registers. These registers are updated each time the curred in the ADE7753. The IRQ logic output should be tied
absolute value of the Waveform sample from the correspond- to a negative edge triggered external interrupt on the MCU.
ing channel is above the value stored in the VPEAK or IPEAK On detection of the negative edge, the MCU should be
register. The contents of the VPEAK register corresponds to configured to start executing its Interrupt Service Routine
2 times the maximum absolute value observed on the channel (ISR). On entering the ISR, all interrupts should be disabled
2 input. The contents of IPEAK represents the max absolute using the global interrupt enable bit. At this point the MCU
value observed on the channel 1 input. Reading the external interrupt flag can be cleared in order to capture
RSTVPEAK and RSTIPEAK registers will clear their re- interrupt events which occur during the current ISR. When
spective contents after the read operation. the MCU interrupt flag is cleared a read from the Status
ADE7753 INTERRUPTS register with reset is carried out. This will cause the IRQ line
ADE7753 Interrupts are managed through the Interrupt to be reset logic high (t2)—see Interrupt timing. The Status
Status register (STATUS[15:0]) and the Interrupt Enable register contents are used to determine the source of the
register (IRQEN[15:0]). When an interrupt event occurs in interrupt(s) and hence the appropriate action to be taken. If
the ADE7753, the corresponding flag in the Status register a subsequent interrupt event occurs during the ISR, that event
is set to a logic one - see Interrupt Status register. If the enable will be recorded by the MCU external interrupt flag being set
bit for this interrupt in the Interrupt Enable register is logic again (t3). On returning from the ISR, the global interrupt
one, then the IRQ logic output goes active low. The flag bits mask will be cleared (same instruction cycle) and the external
in the Status register are set irrespective of the state of the interrupt flag will cause the MCU to jump to its ISR once
enable bits. again. This will ensure that the MCU does not miss any
In order to determine the source of the interrupt, the system external interrupts.
master (MCU) should perform a read from the Status Interrupt timing
register with reset (RSTSTATUS[15:0]). This is achieved The ADE7753 Serial Interface section should be reviewed first
by carrying out a read from address 0Ch. The IRQ output will before reviewing the interrupt timing. As previously de-
go logic high on completion of the Interrupt Status register MCU
int. flag set

t1 t2 t3

IRQ

Read ISR Return

MCU Program Jump to Global int. Clear MCU Status with
ISR Action
Global int. Mask
Jump to
Sequence ISR Mask Set int. flag (Based on Status contents) ISR
Reset (05h) Reset

Figure 15– ADE7753 interrupt management

CS
t1
t9
SCLK

DIN 0 0 0 0 0 1 0 1
t11 t11

DOUT DB7 DB0 DB7 DB0

Read Status Register Command

Status Register Contents

IRQ

Figure 16– ADE7753 interrupt timing

REV. PrF 10/02 –13–
 PRELIMINARY TECHNICAL DATA
ADE7753
scribed, when the IRQ output goes low the MCU ISR must the 1-bit ADC is virtually meaningless. Only when a large
read the Interrupt Status register in order to determine the number of samples are averaged will a meaningful result be
source of the interrupt. When reading the Status register obtained. This averaging is carried out in the second part of
contents, the IRQ output is set high on the last falling edge the ADC, the digital low pass filter. By averaging a large
of SCLK of the first byte transfer (read Interrupt Status number of bits from the modulator the low pass filter can
register command). The IRQ output is held high until the last produce 24-bit data words which are proportional to the input
bit of the next 15-bit transfer is shifted out (Interrupt Status signal level.
register contents)— see Figure 16. If an interrupt is pending The sigma-delta converter uses two techniques to achieve
at this time, the IRQ output will go low again. If no interrupt high resolution from what is essentially a 1-bit conversion
is pending the IRQ output will stay high. technique. The first is over-sampling. By over sampling we
TEMPERATURE MEASUREMENT mean that the signal is sampled at a rate (frequency) which is
ADE7753 also includes an on-chip temperature sensor. A many times higher than the bandwidth of interest. For
temperature measurement can be made by setting bit 5 in the example the sampling rate in the ADE7753 is CLKIN/4
Mode register. When bit 5 is set logic high in the Mode (894kHz) and the band of interest is 40Hz to 2kHz. Over-
register, the ADE7753 will initiate a temperature measure- sampling has the effect of spreading the quantization noise
ment on the next zero crossing. When the zero crossing on (noise due to sampling) over a wider bandwidth. With the
Channel 2 is detected the voltage output from the tempera- noise spread more thinly over a wider bandwidth, the
ture sensing circuit is connected to ADC1 (Channel 1) for quantization noise in the band of interest is lowered—see
digitizing. The resultant code is processed and placed in the Figure 18. However, oversampling alone is not an efficient
Temperature register (TEMP[7:0]) approximately 26µs later enough method to improve the signal to noise ratio (SNR) in
(24 CLKIN cycles). If enabled in the Interrupt Enable the band of interest. For example, an oversampling ratio of
register (bit 5), the IRQ output will go active low when the 4 is required just to increase the SNR by only 6dB (1-Bit). To
temperature conversion is finished. Please note that tempera- keep the oversampling ratio at a reasonable level, it is
ture conversion will introduce a small amount of noise in the possible to shape the quantization noise so that the majority
energy calculation. If temperature conversion is performed of the noise lies at the higher frequencies. This is what
frequently (e.g. multiple times per second), a noticeable happens in the sigma-delta modulator, the noise is shaped by
error will accumulate in the resulting energy calculation over the integrator which has a high pass type response for the
time. quantization noise. The result is that most of the noise is at
The contents of the Temperature register are signed (2's the higher frequencies where it can be removed by the digital
complement) with a resolution of approximately 1 LSB/°C. low pass filter. This noise shaping is also shown in Figure 18.
The temperature register will produce a code of 00h when the
ambient temperature is approximately 70°C. The tempera-
ture measurement is uncalibrated in the ADE7753 and has an
offset tolerance that could be as high as ±20°C. Antialias filter (RC)
Sampling
Digital filter Shaped Frequency
Signal Noise
ADE7753 ANALOG TO DIGITAL CONVERSION
The analog-to-digital conversion in the ADE7753 is carried
out using two second order sigma-delta ADCs. For simplic-
Noise
ity reason, the block diagram in Figure 17 shows a first order
sigma-delta ADC. The converter is made up of two parts: the
sigma-delta modulator and the digital low pass filter. 0 2kHz 447kHz 894kHz
Frequency (Hz)
MCLK/4

Signal High resolution

Analog Low Pass Filter INTEGRATOR Digital Low Pass Filter output from Digital
LATCHED
+ LPF
Σ
COMPARATOR
e +
R VREF -
- 24
Noise
C

....10100101......
1-Bit DAC 0 2kHz 447kHz 894kHz
Frequency (Hz)
Figure 17– First Order Sigma-Delta (Σ−∆) ADC

A sigma-delta modulator converts the input signal into a Figure 18– Noise reduction due to Oversampling & Noise
continuous serial stream of 1's and 0's at a rate determined by shaping in the analog modulator
the sampling clock. In the ADE7753 the sampling clock is
Antialias Filter
equal to CLKIN/4. The 1-bit DAC in the feedback loop is
Figure 17 also shows an analog low pass filter (RC) on the
driven by the serial data stream. The DAC output is sub-
input to the modulator. This filter is present to prevent
tracted from the input signal. If the loop gain is high enough
aliasing. Aliasing is an artifact of all sampled systems.
the average value of the DAC output (and therefore the bit
Basically it means that frequency components in the input
stream) will approach that of the input signal level. For any
signal to the ADC which are higher than half the sampling
given input value in a single sampling interval, the data from
rate of the ADC will appear in the sampled signal at a
–14– REV. PrF 10/02
 PRELIMINARY TECHNICAL DATA
ADE7753
frequency below half the sampling rate. Figure 19 illustrates Output
Impedance
the effect. Frequency components (arrows shown in black) Maximum 6kΩ
above half the sampling frequency (also know as the Nyquist Load = 10µA
REFIN/OUT
frequency, i.e., 447kHz) get imaged or folded back down PTAT 60µA 2.42V
below 447kHz (arrows shown in grey). This will happen with
all ADCs regardless of the architecture. In the example 2.5V
1.7kΩ
shown, only frequencies near the sampling frequency, i.e.,
894kHz, will move into the band of interest for metering, i.e, 12.5kΩ

40Hz - 2kHz. This allows the usage of very simple LPF (Low
Pass Filter) to attenuate high frequency (near 900kHz) noise 12.5kΩ
and prevents distortion in the band of interest. For conven-
tional current sensor, a simple RC filter (single pole LPF) Reference input to ADC
12.5kΩ Channel 1 (Range Select)
with a corner frequency of 10kHz will produce an attenuation 2.42V, 1.21V, 0.6V
of approximately 40dBs at 894kHz—see Figure 18. The
20dB per decade attenuation is usually sufficient to eliminate 12.5kΩ

the effects of aliasing for conventional current sensor.

For di/dt sensor such as Rogowski coil, however, the sensor
has 20dB per decade gain. This will neutralize the -20dB per Figure 20 —ADE7753 Reference Circuit Ouput
decade attenuation produced by the simple LPF. Therefore, The REFIN/OUT pin can be overdriven by an external source,
when using a di/dt sensor, care should be taken to offset the e.g., an external 2.5V reference. Note that the nominal
20dB per decade gain coming from the di/dt sensor. One reference value supplied to the ADCs is now 2.5V not 2.42V.
simple approach is to cascade two RC filters to produce the This has the effect of increasing the nominal analog input
-40dB per decade attenuation needed. signal range by 2.5/2.42×100% = 3% or from 0.5V to
0.5165V.
Aliasing Effects The voltage of ADE7753 reference drifts slightly with
temperature—see ADE7753 Specifications for the temperature
Sampling Frequency coefficient specification (in ppm/°C) . The value of the
image
frequencies
temperature drift varies from part to part. Since the reference
is used for the ADCs in both Channel 1 and 2, any x% drift
in the reference will result in 2x% deviation of the meter
0 2kHz 447kHz 894kHz accuracy. The reference drift resulting from temperature
Frequency (Hz) changes is usually very small and it is typically much smaller
Figure 19 —ADC and signal processing in Channel 1 than the drift of other components on a meter. However, if
guaranteed temperature performance is needed, one needs to
ADC transfer function
use an external voltage reference. Alternatively, the meter can
Below is an expression which relates the output of the LPF be calibrated at multiple temperatures. Real time compensa-
in the sigma-delta ADC to the analog input signal level. Both tion can be easily achieved using the on the on-chip temperature
ADCs in the ADE7753 are designed to produce the same
sensor.
output code for the same input signal level.
CHANNEL 1 ADC
Vin
Code ( ADC ) = 3.0492 × × 262,144 Figure 21 shows the ADC and signal processing chain for
Vout Channel 1. In waveform sampling mode the ADC outputs a
Therefore with a full scale signal on the input of 0.5V and an signed 2’s Complement 24-bit data word at a maximum of
internal reference of 2.42V, the ADC output code is nomi- 27.9kSPS (CLKIN/128). With the specified full scale ana-
nally 165,151 or 2851Fh. The maximum code from the log input signal of 0.5V (or 0.25V or 0.125V – see Analog
ADC is ±262,144, this is equivalent to an input signal level Inputs section) the ADC will produce an output code which is
of ±0.794V. However for specified performance it is not approximately between 2851ECh (+2,642,412 Decimal)
recommended that the full-scale input signal level of 0.5V be and D7AE14h (-2,642,412 Decimal). This is illustrated in
exceeded. Figure 21.
ADE7753 Reference circuit Channel 1 Sampling
Shown below in Figure 20 is a simplified version of the The waveform samples may also be routed to the WAVE-
reference output circuitry. The nominal reference voltage at FORM register (MODE[14:13] = 1,0) to be read by the
the REFIN/OUT pin is 2.42V. This is the reference voltage used system master (MCU). In waveform sampling mode the
for the ADCs in the ADE7753. However, Channel 1 has WSMP bit (bit 3) in the Interrupt Enable register must also
three input range selections which are selected by dividing be set to logic one. The Active, Apparent Power and Energy
down the reference value used for the ADC in Channel 1. The calculation will remain uninterrupted during waveform sam-
reference value used for Channel 1 is divided down to ½ and pling.
¼ of the nominal value by using an internal resistor divider When in waveform sample mode, one of four output sample
as shown in Figure 20. rates may be chosen by using bits 11 and 12 of the Mode
register (WAVSEL1,0). The output sample rate may be
27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—see Mode Register.
The interrupt request output IRQ signals a new sample
REV. PrF 10/02 –15–
 PRELIMINARY TECHNICAL DATA
ADE7753
availability by going active low. The timing is shown in RMS register is equivalent to one LSB of a channel 1
Figure 22. The 24-bit waveform samples are transferred waveform sample. The update rate of the channel 1 RMS
from the ADE7753 one byte (8-bits) at a time, with the most measurement is CLKIN/4.
significant byte shifted out first. The 24-bit data word is right
Current Signal - i(t)
justified - see ADE7753 Serial Interface. 2851ECh Irms(t)
00h IRMSOS[11:0]
25 26 27 17 16 15 1C82B3h
IRQ D7AE14h SIGN 2 2 2 2 2 2

00h
SCLK +
HPF LPF3
Read from WAVEFORM
Σ
24 24
Channel 1 IRMS
DIN 0 0 0 01 Hex

DOUT Sign
Channel 1 DATA - 24 bits

Figure 23 - Channel 1 RMS signal processing

Figure 22 – Waveform sampling Channel 1
With the specified full scale analog input signal of 0.5V, the
The interrupt request output IRQ stays low until the interrupt ADC will produce an output code which is approximately
routine reads the Reset Status register - see ADE7753 Interrupt. ±2,642,412d—see Channel 1 ADC. The equivalent RMS val-
ues of a full-scale AC signal is 1,868,467d (1C82B3h).
Channel 1 RMS calculation
Root Mean Square (RMS) value of a continuous signal V(t) Channel 1 RMS offset compensation
is defined as: The ADE7753 incorporates a channel 1 RMS offset compen-
sation register (IRMSOS). This is 12-bit signed registers
which can be used to remove offset in the channel 1 RMS
1 T 2 ()
Vrms = ⋅ ∫ V t dt (1)
calculation. An offset may exist in the RMS calculation due
T 0 to input noises that are integrated in the DC component of
V2(t). The offset calibration will allow the content of the
For time sampling signals, rms calculation involves squaring IRMS register to be maintained at zero when no input is
the signal, taking the average and obtaining the square root: present on channel 1.
1 LSB of the Channel 1 RMS offset are equivalent to 32,768
LSB of the square of the Channel 1 RMS register. Assuming
⋅ ∑V (i ) (2)
1 N 2
Vrms = that the maximum value from the Channel 1 RMS calcula-
N i =1 tion is 1,868,467d with full scale AC inputs, then 1 LSB of
the channel 1 RMS offset represents 0.46% of measurement
ADE7753 calculates simultaneously the RMS values for error at -60dB down of full scale.
Channel 1 and Channel 2 in different register. Figure 23
shows the detail of the signal processing chain for the RMS Irms = Irms 2
+ IRMSOS × 32768
0
calculation on channel 1. The channel 1 RMS value is
processed from the samples used in the channel 1 waveform where Irmso is the RMS measurement without offset correc-
sampling mode. The channel 1 RMS value is stored in an tion.
unsigned 24-bit register (IRMS). One LSB of the channel 1

CURRENT RMS (IRMS)

2.42V, 1.21V, 0.6V CALCULATION
x1, x2, x4, GAIN[4:3]
REFERENCE
x8, x16
WAVEFORM SAMPLE
GAIN[2:0] DIGITAL REGISTER
V1P HPF INTEGRATOR*

V1 PGA1 ADC 1 ∫ ACTIVE AND REACTIVE

POWER CALCULATION

V1N
Channel 1 (Current Waveform)
Data Range After integrator (50Hz)
50Hz 1EF73Ch
V1
0.5V, 0.25V, 000000h
2851ECh
0.125V, 62.5mV, Channel 1 (Current Waveform)
31.3mV, 15.6mV, Data Range E108C4h
000000h
0V
2851ECh
D7AE14h
ADC Output
Analog Channel 1 (Current Waveform)
word Range 000000h
Input 60Hz Data Range After Integrator (60Hz)
Range
D7AE14h 19CE08h

000000h

*WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED E631F8h

DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A -20dB/DECADE
FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT WILL NOT BE FURTHER ATTENUATED.

Figure 21 —ADC and signal processing in Channel 1

–16– REV. PrF 10/02
 PRELIMINARY TECHNICAL DATA
ADE7753
CHANNEL 2 ADC directly to the multiplier and is not filtered. A HPF is not
Channel 2 Sampling required to remove any DC offset since it is only required to
In Channel 2 waveform sampling mode (MODE[14:13] = remove the offset from one channel to eliminate errors due to
1,1 and WSMP = 1) the ADC output code scaling for offsets in the power calculation. When in waveform sample
Channel 2 is not the same as Channel 1. Channel 2 waveform mode, one of four output sample rates can be chosen by using
sample is a 16-bit word and sign extended to 24 bits. For bits 11 and 12 of the Mode register. The available output
normal operation, the differential voltage signal between sample rates are 27.9kSPS, 14kSPS, 7kSPS or 3.5kSPS—
V2P and V2N should not exceed 0.5V. With maximum see Mode Register. The interrupt request output IRQ signals a
voltage input (±0.5V at PGA gain of 1), the outputs from the sample availability by going active low. The timing is the
ADC swings between 2852h and D7AEh (±10,322 Deci- same as that for Channel 1 and is shown in Figure 22.
mal). However, before being passed to the Waveform register, Channel 2 RMS calculation
the ADC output is passed through a single pole, low pass Figure 26 shows the details of the signal processing chain for
filter with a cutoff frequency of 140Hz. The plots in Figure the RMS calculation on Channel 2. The channel 2 RMS
24 shows the magnitude and phase response of this filter. value is processed from the samples used in the channel 2
waveform sampling mode. The RMS value will be slightly
0 0
60 Hz, -0.73dB attenuated because of LPF1. Channel 2 RMS value is stored
-10 50 Hz, -0.52dB -2 in the unsigned 24-bit VRMS register. The update rate of the
-20 -4
channel 2 RMS measurement is CLKIN/4.
50 Hz, -19.7° With the specified full scale AC analog input signal of 0.5V,
-30
60 Hz, -23.2°
-6
the outputs from the LPF1 swings between 2518h and
DAE8h at 60 Hz- see Channel 2 ADC. The equivalent RMS
Gain (dBs)

-40
Phase (°)

-8

-50
value of this full-scale AC signal is approximately 1,561,400
-10
(17D338h) in the VRMS register.
-60 -12

-70 -14
Voltage Signal - V(t)
-80 -16 2518h VRMSOS[11:0]
0h SGN 29 28 2
2
2
1
2
0
-90 -18
1 2 3
10 10 10 DAE8h VRMS[23:0]
Frequency (Hz)
LPF1 LPF3
+ 17D338h
+
Figure 24 – Magnitude & Phase response of LPF1
Channel 2
S 00h

The LPF1 has the effect of attenuating the signal. For

example if the line frequency is 60Hz, then the signal at the Figure 26 - Channel 2 RMS signal processing
output of LPF1 will be attenuated by about 8%.
Channel 2 RMS offset compensation
1 The ADE7753 incorporates a channel 2 RMS offset compen-
H(f) = = 0.919 = −0.73dB
( )
sation register (VRMSOS). This is a 12-bit signed registers
2
1 + 60Hz 140Hz which can be used to remove offset in the channel 2 RMS
calculation. An offset may exist in the RMS calculation due
Note LPF1 does not affect the power calculation. The signal to input noises and dc offset in the input samples. The offset
processing chain in Channel 2 is illustrated in Figure 25. calibration allows the contents of the VRMS register to be
maintained at zero when no voltage is applied.
2.42V 1 LSB of the channel 2 RMS offset are equivalent to 1 LSB
REFERENCE
x1, x2, x4,
x8, x16
of the RMS register. Assuming that the maximum value from
V2P GAIN[7:5] the channel 2 RMS calculation is 1,561,400d with full scale
V2 PGA2 ADC 2
ACTIVE AND REACTIVE
ENERGY CALCULATION
AC inputs, then 1 LSB of the channel 2 RMS offset represents
LPF1
V2N VRMS CALCULATION
0.064% of measurement error at -60dB down of full scale.
AND WAVEFORM

Vrms = Vrmso + VRMSOS

SAMPLING
Analog V1
(PEAK/SAG/ZX)
Input Range
0.5V, 0.25V, 0.125V, LPF Output
62.5mV, 31.25mV word Range
2852h
0V
2518h where Vrmso is the RMS measurement without offset correc-
tion.
0000h

DAE8h PHASE COMPENSATION

D7AEh
When the HPF is disabled, the phase error between Channel
1 and Channel 2 is zero from DC to 3.5kHz. When HPF is
Figure 25 – ADC and Signal Processing in Channel 2 enabled, Channel 1 has a phase response illustrated in
Unlike Channel 1, Channel 2 has only one analog input range Figures 28 & 29. Also shown in Figure 30 is the magnitude
(1V differential). However like Channel 1, Channel 2 does response of the filter. As can be seen from the plots, the phase
have a PGA with gain selections of 1, 2, 4, 8 and 16. For response is almost zero from 45Hz to 1kHz, This is all that
energy measurement, the output of the ADC is passed is required in typical energy measurement applications.
REV. PrF 10/02 –17–
 PRELIMINARY TECHNICAL DATA
ADE7753
However, despite being internally phase compensated the
ADE7753 must work with transducers which may have
inherent phase errors. For example a phase error of 0.1° to 0.9

0.3° is not uncommon for a CT (Current Transformer). 0.8

These phase errors can vary from part to part and they must 0.7
be corrected in order to perform accurate power calculations.
0.6
The errors associated with phase mismatch are particularly

PHASE-DEGREES
0.5
noticeable at low power factors. The ADE7753 provides a
means of digitally calibrating these small phase errors. The 0.4

ADE7753 allows a small time delay or time advance to be 0.3

introduced into the signal processing chain in order to 0.2

compensate for small phase errors. Because the compensa- 0.1

tion is in time, this technique should only be used for small 0

phase errors in the range of 0.1° to 0.5°. Correcting large
-0.1
phase errors using a time shift technique can introduce 10
2

FREQUENCY-Hz
10
3
10
4

significant phase errors at higher harmonics.

The Phase Calibration register (PHCAL[5:0]) is a 2’s
Figure 28 – Combined Phase Response of the HPF & Phase
complement signed single byte register which has values
Compensation (10Hz to 1kHz)
ranging from 21h (-31 in Decimal) to 1Fh (31 in Decimal).
The register is centered at 0Dh, so that writing 0Dh to the
0.2
register gives zero delay. By changing the PHCAL register,
the time delay in the Channel 2 signal path can change from 0.15

–100.8µs to +33.6µs (CLKIN = 3.579545MHz). One LSB

0.1
is equivalent to 2.22µs time delay or advance. With a line
frequency of 60Hz this gives a phase resolution of 0.048° at 0.05
PHASE-DEGREES

the fundamental (i.e., 360° × 2.22µs × 60Hz). Figure 27

illustrates how the phase compensation is used to remove a
0.1° phase lead in Channel 1 due to the external transducer. -0.05
In order to cancel the lead (0.1°) in Channel 1, a phase lead
must also be introduced into Channel 2. The resolution of the -0.1

phase adjustment allows the introduction of a phase lead in

-0.15
increment of 0.048°. The phase lead is achieved by introduc-
ing a time advance into Channel 2. A time advance of 4.48µs -0.2
40 45 50 55 60 65 70
is made by writing -2 (0Bh) to the time delay block, thus FREQUENCY-Hz

reducing the amount of time delay by 4.48µs, or equivalently,

a phase lead of approximately 0.1° at line frequency of 60Hz. Figure 29 – Combined Phase Response of the HPF & Phase
0Bh represents -2 because the register is centered with zero Compensation (40Hz to 70Hz)
at 0Dh.
0.2

V1P HPF 0.18

24
V1 PGA1 ADC 1 0.16

V1N LPF2
24 0.14

0.12
V2P
GAIN-dB

1
Delay Block Channel 2 delay 0.1
V2 PGA2 ADC 2 V2
4.48µs / LSB reduced by 4.48µs
V1
V2N (0.18lead at 60Hz) 0.08
0Bh in PHCAL[5:0]
5 0
V2
0.06
0.18 0 0 1 0 1 1
V1
PHCAL[5:0] 0.04
-100µs to +34µs
0.02

60Hz
0
40 45 50 55 60 65 70
FREQUENCY-Hz
60Hz

Figure 30 – Combined Gain Response of the

Figure 27 – Phase Calibration HPF & Phase Compensation

ACTIVE POWER CALCULATION

Power is defined as the rate of energy flow from source to
load. It is defined as the product of the voltage and current
waveforms. The resulting waveform is called the instanta-
neous power signal and it is equal to the rate of energy flow
at every instant of time. The unit of power is the watt or joules/

–18– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
sec. Equation 3 gives an expression for the instantaneous Since LPF2 does not have an ideal “brick wall” frequency
power signal in an ac system. response—see Figure 32, the Active Power signal will have
some ripple due to the instantaneous power signal. This
v()
t = 2V sin (ωt ) (1) ripple is sinusoidal and has a frequency equal to twice the line
frequency. Since the ripple is sinusoidal in nature it will be
i()
t = 2 I sin (ωt ) (2) removed when the Active Power signal is integrated to
where V = rms voltage, calculate Energy – see Energy Calculation.
I = rms current.
0

() () ()
p t = v t × i t -4

p(t ) = VI − VI cos(ωt )
(3)
-8

The average power over an integral number of line cycles (n)

-12

dBs
is given by the expression in Equation 4.
-16

∫ p (t )dt = VI
1 nT
P= (4)
-20

nT 0 -24
1.0Hz 3.0Hz 10Hz 30Hz 100Hz
where T is the line cycle period. Frequency

P is referred to as the Active or Real Power. Note that the

active power is equal to the dc component of the instanta- Figure 32 —Frequency Response of LPF2
neous power signal p(t) in Equation 3 , i.e., VI. This is the Figure 33 shows the signal processing chain for the
relationship used to calculate active power in the ADE7753. ActivePower calculation in the ADE7753. As explained, the
The instantaneous power signal p(t) is generated by multiply- Active Power is calculated by low pass filtering the instanta-
ing the current and voltage signals. The dc component of the neous power signal. Note that for when reading the waveform
instantaneous power signal is then extracted by LPF2 (Low samples from the output of LPF2,
Pass Filter) to obtain the active power information. This The gain of the Active Energy can be adjusted by using the
process is illustrated graphically in Figure 31. multiplier and Watt Gain register (WGAIN[11:0]). The
gain is adjusted by writing a 2’s complement 12-bit word to
Instantaneous
the Watt Gain register. Below is the expression that shows
Power Signal p(t) = V×I-V×I×cos(2ωt) how the gain adjustment is related to the contents of the Watt
19999Ah
Active Real Power Gain register.
Signal = V x I
  WGAIN 
V. I. Output WGAIN =  Active Power × 1 + 
CCCCDh
  212 
For example when 7FFh is written to the Watt Gain register
the Power output is scaled up by 50%. 7FFh = 2047d,
2047/212 = 0.5. Similarly, 800h = -2048 Dec (signed 2’s
00000h
Complement) and power output is scaled by –50%.
Current
i(t) = √2×I×sin(ωt) Shown in Figure 34 is the maximum code (in hex) output
range for the Active Power signal (LPF2). Note that the
Voltage
v(t) = √2×V×sin(ωt) output range changes depending on the contents of the Watt
Gain register. The minimum output range is given when the
Figure 31 – Active Power Calculation
Watt Gain register contents are equal to 800h, and the

HPF APOS[15:0] For Waveform

6 5 24
Sampling
sgn 2 -6 -7 -8
I 2 2 2 2
19999h
Current Signal - i(t)
LPF2
+
Σ
24 32
+ For Energy
MULTIPLIER
Accumulation
Active Power
Instantaneous Signal - P
Power Signal - p(t) WGAIN[11:0] CCCCDh
V 19999Ah
Voltage Signal - v(t)

000000h

Figure 33– Active Power Signal Processing

REV. PrF 10/02 –19–
 PRELIMINARY TECHNICAL DATA
ADE7753
maximum range is given by writing 7FFh to the Watt Gain Figure 35 shows a graphical representation of this discrete
register. This can be used to calibrate the Active Power (or time integration or accumulation. The Active Power signal
Energy) calculation in the ADE7753. in the Waveform register is continuously added to the internal
Active Energy register. This addition is a signed addition,
therefore negative energy will be subtracted from the Active
Energy contents.
Active Power Output

133333h
CCCCDh Positive The output of the multiplier is divided by WDIV. If the value
66666h Power in the WDIV register is equal to 0 then the internal Active
00000h Energy register is divided by 1. WDIV is an 8-bit unsigned
F9999Ah Negative register. After dividing by WDIV, the active energy is
F33333h Power accumulated in a 48-bit internal energy accumulation regis-
ECCCCDh ter. The upper 24 bit of this register is accessible through a
000h 7FFh 800h
read to the Active Energy register (AENERGY[23:0]). A
WGAIN[11:0]
read to the RAENERGY register will return the content of
Active Power the AENERGY register and the upper 24-bit of the internal
Calibration Range
register is clear after a read to AENERGY register.
As shown in Figure 35, the Active Power signal is accumu-
Figure 34 – Active Power Calculation Output Range lated in an internal 48-bit signed register.
ENERGY CALCULATION The Active Power signal can be read from the Waveform
As stated earlier, power is defined as the rate of energy flow. register by setting MODE[14:13] = 0,0 and setting the
This relationship can be expressed mathematically as WSMP bit (bit 3) in the Interrupt Enable register to 1. Like
Equation 5. the Channel 1 and Channel 2 waveform sampling modes the
waveform date is available at sample rates of 27.9kSPS,
dE 14kSPS, 7kSPS or 3.5kSPS—see Figure 22.
P= (5)
dt Figure 36 shows this energy accumulation for full scale
signals (sinusoidal) on the analog inputs. The three curves
Where P = Power and E = Energy. displayed, illustrate the minimum period of time it takes the
Conversely Energy is given as the integral of Power. energy register to roll-over when the Active Power Gain
E = ∫ Pdt (6)
register contents are 7FFh, 000h and 800h. The Watt Gain
register is used to carry out power calibration in the ADE7753.
The ADE7753 achieves the integration of the Active Power As shown, the fastest integration time will occur when the
signal by continuously accumulating the Active Power signal Watt Gain register is set to maximum full scale, i.e., 7FFh.
in an internal non-readable 56-bit Energy register. The
Active Energy register (AENERGY[23:0]) represents the AENERGY[23:0]

upper 24 bits of this internal register. This discrete time 7F,FFFFh

WGAIN = 7FFh
accumulation or summation is equivalent to integration in WGAIN = 000h
continuous time. Equation 7 below expresses the relationship WGAIN = 800h
3F,FFFFh

∞ 
E = ∫ p(t )dt = Lim∑ p(nT ) × T  (7) Time
t → 0  n =1  00,0000h
4 6.2 8 12.5 (minutes)

Where n is the discrete time sample number and T is the

40,0000h
sample period.
UPPER 24 BITS ARE
80,0000h
23 AENERGY[23:0] 0 ACCESSIBLE THROUGH
AENERGY[23:0] REGISTER
Current Channel
APOS [15:0] WDIV[7:0]

LPF2 + 46 0
Figure 36 - Energy register roll-over time for full-scale
+
Σ power (Minimum & Maximum Power Gain)

Voltage Channel
Active Power
WGAIN[11:0] Note that the energy register contents will roll over to full-
Signal - P* scale negative (800000h) and continue increasing in value
OUTPUT

T OUTPUTS FROM THE LPF2 ARE

4 ACCUMULATED (INTEGRATED) IN when the power or energy flow is positive - see Figure 36.
LPF2

CLKIN WAVEFORM
REGISTER THE INTERNAL ACTIVE ENERGY REGISTER
VALUES Conversely if the power is negative the energy register would
under flow to full scale positive (7FFFFFh) and continue
time (nT)
decreasing in value.
By using the Interrupt Enable register, the ADE7753 can be
Figure 35 – ADE7753 Active Energy Calculation configured to issue an interrupt (IRQ) when the Active
The discrete time sample period (T) for the accumulation Energy register is half-full (positive or negative) or when an
register in the ADE7753 is 1.1µs (4/CLKIN). As well as over/under flow occurs.
calculating the Energy this integration removes any sinusoi- Integration time under steady load
dal components which may be in the Active Power signal. As mentioned in the last section, the discrete time sample
period (T) for the accumulation register is 1.1µs (4/CLKIN).
–20– REV. PrF 10/02
 PRELIMINARY TECHNICAL DATA
ADE7753
With full-scale sinusoidal signals on the analog inputs and the output pulse is generated when (CFDEN+1)/(CFNUM+1)
WGAIN register set to 000h, the average word value from number of pulses are generated at the DFC output. Under
each LPF2 is CCCCDh - see Figure 31. The maximum steady load conditions the output frequency is proportional to
positive value which can be stored in the internal 47-bit the Active Power.
register is 246 - 1 or 7FFF,FFFF,FFFFh before it overflows, The maximum output frequency, with AC input signals at
the integration time under these conditions with WDIV=0 is full-scale and CFNUM=00h & CFDEN=00h, is approxi-
calculated as follows: mately 23 kHz.
The ADE7753 incorporates two registers, CFNUM[11:0]
3FFF , FFFF, FFFFh and CFDEN[11:0], to set the CF frequency. These are
Time = × 1.12 µs = 187.5s = 3.12 min s unsigned 12-bit registers which can be used to adjust the CF
CCCCDh
frequency to a wide range of values. These frequency scaling
When WDIV is set to a value different from 0, the integration registers are 12-bit registers which can scale the output
time varies as shown on Equation 8. frequency by 1/212 to 1 with a step of 1/212.
Time = TimeWDIV=0 x WDIV (8) If the value zero is written to any of these registers, the value
POWER OFFSET CALIBRATION one would be applied to the register. The ratio (CFNUM+1)/
The ADE7753 also incorporates an Active Power Offset (CFDEN+1) should be smaller than one to assure proper
register (APOS[15:0]). This is a signed 2’s complement 16- operation. If the ratio of the registers (CFNUM+1)/
bit register which can be used to remove offsets in the active (CFDEN+1) is greater than one, the register values would
power calculation—see Figure 33. An offset may exist in the be adjust to a ratio (CFNUM+1)/(CFDEN+1) of one.
power calculation due to cross talk between channels on the For example if the output frequency is 1.562kHz while the
PCB or in the IC itself. The offset calibration will allow the contents of CFDENare zero (000h), then the output frequency
contents of the Active Power register to be maintained at zero can be set to 6.1Hz by writing FFh to the CFDEN register.
when no power is being consumed. Note that for values where CFDEN>CFNUM, the
Two hundred fifty six LSBs (APOS=0100h) written to the performance of the CF frequency is not guaranteed. CFNUM
Active Power Offset register are equivalent to 1 LSB in the should always be set to a value less than CFDEN.
Waveform Sample register. Assuming the average value The output frequency will have a slight ripple at a frequency
outputs from LPF2 is CCCCDh (838,861 in Decimal) when equal to twice the line frequency. This is due to imperfect
inputs on Channels 1 and 2 are both at full-scale. At -60dB filtering of the instantaneous power signal to generate the
down on Channel 1 (1/1000 of the Channel 1 full-scale Active Power signal – see Active Power Calculation. Equation 3
input), the average word value outputs from LPF2 is 838.861 gives an expression for the instantaneous power signal. This
(838,861/1,000). 1 LSB in the LPF2 output has a measure- is filtered by LPF2 which has a magnitude response given by
ment error of 1/838.861 × 100% = 0.119% of the average Equation 9.
value. The Active Power Offset register has a resolution
1
equal to 1/256 LSB of the Waveform register, hence the H (f ) =
power offset correction resolution is 0.00047%/LSB (0.119%/ f2
256) at -60dB. 1+
8 .9 2
ENERGY TO FREQUENCY CONVERSION (9)
ADE7753 also provides energy to frequency conversion for The Active Power signal (output of LPF2) can be rewritten
calibration purposes. After initial calibration at manufactur- as.
ing, the manufacturer or end customer will often verify the
energy meter calibration. One convenient way to verify the  
 
meter calibration is for the manufacturer to provide an output  
 ⋅ cos(4π fl t )
VI
= −
p(t ) VI 
frequency which is proportional to the energy or active power
  2fl  
2
(10)
under steady load conditions. This output frequency can  1 +  8.9  
provide a simple, single wire, optically isolated interface to  
external calibration equipment. Figure 37 illustrates the where fl is the line frequency (e.g., 60Hz)
Energy-to-Frequency conversion in the ADE7753. From Equation 6
11 CFNUM[11:0] 0
 
 
 
 ⋅ sin(4π fl t )
VI
Energy DFC CF E (t ) = VIt − 
23 AENERGY[23:0] 0   2fl  
2 (11)
 4π fl 1 +  8.9  
 
11 CFDEN[11:0] 0

Figure 37– ADE7753 Energy to Frequency Conversion

From Equation 11 it can be seen that there is a small ripple
A Digital to Frequency Converter (DFC) is used to generate in the energy calculation due to a sin(2ωt) component. This
the CF pulsed output. The DFC generates a pulse each time is shown graphically in Figure 38. The Active Energy
one LSB in the Active Energy register is accumulated. An calculation is shown by the dashed straight line and is equal
REV. PrF 10/02 –21–
 PRELIMINARY TECHNICAL DATA
ADE7753
to V x I x t. The sinusoidal ripple in the Active Energy calibration is invalid and should be ignored. The result of all
calculation is also shown. Since the average value of a subsequent line cycle accumulation is correct.
sinusoid is zero, this ripple will not contribute to the energy From Equations 6 and 10.
calculation over time. However, the ripple can be observed
in the frequency output, especially at higher output frequen-  
 
cies. The ripple will get larger as a percentage of the   nT
 ⋅ ∫ cos(2π f t ) dt
nT
VI
frequency at larger loads and higher output frequencies. The E (t ) = ∫ VI dt − 
  f 2  0 (12)
 1 +  8.9  
0
reason is simply that at higher output frequencies the integra-
tion or averaging time in the Energy-to-Frequency conversion  
process is shorter. As a consequence some of the sinusoidal
where n is a integer and T is the line cycle period. Since the
ripple is observable in the frequency output. Choosing a
sinusoidal component is integrated over a integer number of
lower output frequency at CF for calibration can significantly
line cycles its value is always zero.
reduce the ripple. Also averaging the output frequency by
using a longer gate time for the counter will achieve the same
Therefore:
results.
E = ∫ VIdt + 0
nT
(13)
E(t) 0
VIt
E(t) = VInT (14)

+ 46 0
Σ
Output from
LPF2
+

−
R
S VI U
V
sin(4. F. f . t )
l
WDIV[7:0]
ACCUMULATE ACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE

T4. F . f (1+
l 2. f / 8.9Hz)
l
W 23 0
THE LAENERGY REGISTER
AT THE END OF LINECYC
LINE-CYCLES
LPF1 LAENERGY[23:0]
FROM
t CHANNEL 2
ADC
ZERO CROSS
DETECTION
CALIBRATION
CONTROL

Figure 38 – Output frequency ripple

LINECYC[14:0]

LINE CYCLE ENERGY ACCUMULATION MODE Figure 39 – Energy Calculation in Line Cycle Energy Accu-
In Line Cycle Energy Accumulation mode, the energy mulation Mode
accumulation of the ADE7753 can be synchronized to the
Channel 2 zero crossing so that active energy can be accumu- Note that in this mode, the 16-bit LINECYC register can
lated over an integral number of half line cycles. The hold a maximum value of 65,535. In other words, the line
advantage of summing the active energy over an integer energy accumulation mode can be used to accumulate active
number of half line cycles is that the sinusoidal component energy for a maximum duration over 65,535 half line cycles.
in the active energy is reduced to zero. This eliminates any At 60Hz line frequency, it translates to a total duration of
ripple in the energy calculation. Energy is calculated more 65,535 / 120Hz = 546 seconds.
accurately and in a shorter time because integration period
can be shortened. By using the line cycle energy accumula- POSITIVE ONLY ACCUMULATION MODE
tion mode, the energy calibration can be greatly simplified In Positive Only Accumulation mode, the energy accumula-
and the time required to calibrate the meter can be signifi- tion is done only for positive power, ignoring any occurrence
cantly reduced. The ADE7753 is placed in line cycle energy of negative power above or below the no load threshold as
accumulation mode by setting bit 7 (CYCMODE) in the shown in Figure 40. The ADE7753 is placed in positive only
Mode register. In Line Cycle Energy Accumulation Mode
the ADE7753 accumulates the active power signal in the
LAENERGY register (Address 04h) for an integral number
of line cycles, as shown in Figure 39. The number of half line
cycles is specified in the LINECYC register (Address 1Ch). Active Energy

The ADE7753 can accumulate active power for up to 65,535

half line cycles. Because the active power is integrated on an No-load
threshold
integral number of line cycles, at the end of a line cycle energy
Active Power
accumulation cycle the CYCEND flag in the Interrupt Status
register is set (bit 2). If the CYCEND enable bit in the No-load
threshold

Interrupt Enable register is enabled, the IRQ output will also

go active low. Thus the IRQ line can also be used to signal IRQ
PPOS PNEG PPOS PNEG PPOS PNEG
the completion of the line cycle energy accumulation. An- Interrupt Status Registers

other calibration cycle will start as long as the CYCMODE Figure 40 – Energy Accumulation in Positive Only
bit in the Mode register is set. Note that the result of the first Accumulation Mode
–22– REV. PrF 10/02
 PRELIMINARY TECHNICAL DATA
ADE7753
accumulation mode by setting the MSB of the MODE Instantaneous Reactive
register (MODE[15]). The default setting for this mode is 90 DEGREE
PHASE SHIFT
Power Signal - Rp(t)

off. Transitions in the direction of power flow, going from

negative to positive or positive to negative, set the IRQ pin I Π
2 MULTIPLIER

to active low if the Interrupt Enable register is enabled. The + 47 0

Σ
+

Interrupt Status Registers, PPOS and PNEG, show which V

transition has occurred. See ADE7753 Register Descriptions. ACCUMULATE ACTIVE
ENERGY IN INTERNAL
REGISTER AND UPDATE
THE LVARENERGY
NO LOAD THRESHOLD 23 0
REGISTER AT THE END OF
LINECYC LINE CYCLES
LVARENERGY[23:0]
The ADE7753 includes a "no load threshold" feature that will FROM
LPF1

ZERO CROSS CALIBRATION

eliminate any creep effects in the meter. The ADE7753 CHANNEL 2
ADC
DETECTION CONTROL

accomplishes this by not accumulating energy if the multi-

plier output is below the "no load threshold". This threshold LINECYC[14:0]

is 0.001% of the full-scale output frequency of the multiplier.

Compare this value to the IEC1036 specification which states
Figure 41 - Reactive Power Signal Processing
that the meter must start up with a load equal to or less than
0.4% Ib. This standard translates to .0167% of the full-scale The features of the Reactive Energy accumulation are the
output frequency of the multiplier. same as the Line Active Energy accumulation. The number
REACTIVE POWER CALCULATION of half line cycles is specified in the LINECYC register.
LINECYC is an unsigned 16-bit register. The ADE7754 can
Reactive power is defined as the product of the voltage and
accumulate Reactive Power for up to 65535 combined half
current waveforms when one of this signal is phase shifted by
cycles. At the end of an energy calibration cycle the CYCEND
90º. The resulting waveform is called the instantaneous
flag in the Interrupt Status register is set. If the CYCEND
reactive power signal. Equation 17 gives an expression for the
mask bit in the Interrupt Mask register is enabled, the IRQ
instantaneous reactive power signal in an ac system when the
output will also go active low. Thus the IRQ line can also be
phase of the current channel is shifted by +90º.
used to signal the end of a calibration. The ADE7753
v (t ) = 2 V sin(ωt + θ ) (15) accumulates the Reactive Power signal in the LVARENERGY
register for an integer number of half cycles, as shown in
π Figure 41.
i( t ) = 2 I sin( ωt ) i' ( t ) = 2 I sin( ωt + ) (16)
2 The Reactive Energy accumulation in the ADE7753 not only
Where θ is the phase difference between the voltage and provides the reactive energy calculated using the phase shift
current channel, V = rms voltage and I = rms current. method, it is also useful to provide the sign of the reactive
power if it is desirable to use triangular method to calculate
Rp (t ) = v (t ) × i ' (t ) reactive power. The ADE7753 also provides an accurate
measurement of the apparent power. The user can choose to
Rp (t ) = VI sin(θ ) + VI sin( 2ωt + θ ) (17)
determine reactive energy through the mathematical rela-
tionship between apparent, active and reactive power. The
The average power over an integral number of line cycles (n) sign of the reactive energy can be found by reading the result
is given by the expression in Equation 18. from the LVARENERGY register at the end of a reactive
1 nT energy accumulation cycle.
RP =
nT
∫ Rp(t )dt = VI sin(θ ) (18)
0 Re active Energy
where T is the line cycle period. = sign(Re active Energy) × Apparent Energy2 − Active Energy2
RP is referred to as the Reactive Power. Note that the reactive
power is equal to the DC component of the instantaneous APPARENT POWER CALCULATION
reactive power signal Rp(t) in Equation 17. This is the Apparent power is defined as the amplitude of the vector sum
relationship used to calculate reactive power in the ADE7753. of the Active and Reactive powers -see Figure 42. The angle
The instantaneous reactive power signal Rp(t) is generated by θ between the Active Power and the Apparent Power generally
multiplying the channel 1 and channel 2. In this case, the represents the phase shift due to non-resistive loads. For
phase of the channel 1 is shifted by +90º. The DC component single phase applications, θ represents the angle between the
of the instantaneous reactive power signal is then extracted by voltage and the current signals. Equation 20 gives an expres-
a low pass filter to obtain the reactive power information. sion of the instantaneous power signal in an ac system with a
Figure 41 shows the signal processing in the Reactive Power phase shift.
calculation in the ADE7753.

REV. PrF 10/02 –23–

 PRELIMINARY TECHNICAL DATA
ADE7753
Apparent writing 7FFh to the Apparent Power Gain register. This can
Power be used to calibrate the Apparent Power (or Energy) calcu-
lation in the ADE7753 -see Apparent Power calculation.
Reactive
Power Apparent Power 100% FS
Apparent Power 150% FS
θ Apparent Power 50% FS

Active
Power
103880h
Figure 42 - Power triangle AD055h
5682Bh

v (t ) = 2 Vrms sin(ωt ) 00000h

000h 7FFh 800h
2 Irms sin(ωt + θ )
(19)
i (t ) = VAGAIN[11:0]
Apparent Power
Calibration Range
p(t ) = v (t ) × i (t ) Voltage and Current channel inputs: 0.5V / GAIN

p(t ) = Vrms I rms cos(θ ) − Vrms I rms cos( 2ωt + θ ) (20) Figure 44- Apparent Power Calculation Output range
The Apparent Power (AP) is defined as Vrms x Irms. This Apparent Power Offset Calibration
expression is independent from the phase angle between the Each RMS measurement includes an offset compensation
current and the voltage. register to calibrate and eliminate the DC component in the
Figure 43 illustrates graphically the signal processing in each RMS value -see Channel 1 RMS calculation and Channel 2 RMS
phase for the calculation of the Apparent Power in the calculation. The channel 1 and channel 2 RMS values are then
ADE7753. multiplied together in the Apparent Power signal processing.
As no additional offsets are created in the multiplication of
Irms Apparent Power the RMS values, there is no specific offset compensation in
Signal - P
Current RMS Signal - i(t) the Apparent Power signal processing. The offset compensa-
AD055h
1C82B3h
tion of the Apparent Power measurement is done by calibrating
00h
MULTIPLIER each individual RMS measurements.

VAGAIN APPARENT ENERGY CALCULATION

Vrms
The Apparent Energy is given as the integral of the Apparent
Voltage RMS Signal - v(t) Power.
Apparent Energy = ∫ Apparent Power (t ) dt
17D338h
00h (21)
The ADE7753 achieves the integration of the Apparent
Power signal by continuously accumulating the Apparent
Figure 43 - Apparent Power Signal Processing Power signal in an internal 48-bit register. The Apparent
The gain of the Apparent Energy can be adjusted by using the Energy register (VAENERGY[23:0]) represents the upper
multiplier and VA Gain register (VAGAIN[11:0]). The gain 24 bits of this internal register. This discrete time accumu-
is adjusted by writing a 2’s complement, 12-bit word to the lation or summation is equivalent to integration in continuous
VAGAIN register. Below is the expression that shows how time. Equation 23 below expresses the relationship
the gain adjustment is related to the contents of the VA Gain ∞ 
register. Apparent Energy = Lim∑ Apparent Power (nT ) × T (22)
T →0  = 
n 0
  VAGAIN 
Output VAGAIN =  Apparent Power × 1 + 
  212  Where n is the discrete time sample number and T is the
For example when 7FFh is written to the VA Gain register sample period.
the Power output is scaled up by 50%. 7FFh = 2047d, The discrete time sample period (T) for the accumulation
2047/212 = 0.5. Similarly, 800h = -2047 Dec (signed 2’s register in the ADE7753 is 1.1µs (4/CLKIN).
Complement) and power output is scaled by –50%. Figure 44 shows a graphical representation of this discrete
The Apparent Power is calculated with the Current and time integration or accumulation. The Apparent Power
Voltage RMS values obtained in the RMS blocks of the signal is continuously added to the internal register. This
ADE7753. Shown in Figure 44 is the maximum code addition is a signed addition even if the Apparent Energy
(Hexadecimal) output range of the Apparent Power signal. remains theoretically always positive.
Note that the output range changes depending on the contents
of the Apparent Power Gain registers. The minimum output
range is given when the Apparent Power Gain register
content is equal to 800h and the maximum range is given by

–24– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
23
VAENERGY[23:0]
0
Integration times under steady load
As mentioned in the last section, the discrete time sample
47 0 period (T) for the accumulation register is 1.1µs (4/CLKIN).
With full-scale sinusoidal signals on the analog inputs and the
VAGAIN register set to 000h, the average word value from
VADIV
Apparent Power stage is AD055h - see Apparent Power output
range. The maximum value which can be stored in the
Apparent Energy register before it over-flows is 2 24 or
T 46 0
APPARENT POWER
Σ
+

+
FF,FFFFh. As the average word value is added to the
internal register which can store 248 - 1 or 7FFF,FFFF,FFFFh
Apparent Power
APPARENT POWER ARE
before it overflows, the integration time under these condi-
Signal - P
T
ACCUMULATED (INTEGRATED) IN
THE APPARENT ENERGY REGISTER tions with VADIV=0 is calculated as follows:
AD055h
7FFF, FFFF,FFFFh
Time = × 1.2µs = 888s = 14.8min
00000h
AD055h
time (nT)
When VADIV is set to a value different from 0, the integra-
tion time varies as shown on Equation 23.
Figure 45- ADE7753 Apparent Energy calculation Time = TimeWDIV=0 x VADIV (23)
The upper 52-bit of the internal register are divided by LINE APPARENT ENERGY ACCUMULATION
VADIV. If the value in the VADIV register is equal to 0 then The ADE7753 is designed with a special Apparent Energy
the internal active Energy register is divided by 1. VADIV is accumulation mode which simplifies the calibration process.
an 8-bit unsigned register. The upper 24-bit are then written By using the on-chip zero-crossing detection, the ADE7753
in the 24-bit Apparent Energy register (VAENERGY[23:0]). accumulates the Apparent Power signal in the LVAENERGY
RVAENERGY register (24 bits long) is provided to read the register for an integral number of half cycles, as shown in
Apparent Energy. This register is reset to zero after a read Figure 47. The line Apparent energy accumulation mode is
operation. always active.
Figure 45 shows this Apparent Energy accumulation for full The number of half line cycles is specified in the LINCYC
scale signals (sinusoidal) on the analog inputs. The three register. LINCYC is an unsigned 16-bit register. The
curves displayed, illustrate the minimum time it takes the ADE7753 can accumulate Apparent Power for up to 65535
energy register to roll-over when the VA Gain registers combined half cycles. Because the Apparent Power is inte-
content is equal to 7FFh, 000h and 800h. The VA Gain grated on the same integral number of line cycles as the Line
register is used to carry out an apparent power calibration in Active Energy register, these two values can be compared
the ADE7753. As shown, the fastest integration time will easily. The active and apparent Energy are calculated more
occur when the VA Gain register is set to maximum full scale, accurately because of this precise timing control and provide
i.e., 7FFh. all the information needed for Reactive Power and Power
VAENERGY[23:0]
Factor calculation. At the end of an energy calibration cycle
the CYCEND flag in the Interrupt Status register is set. If the
FF,FFFFh CYCEND mask bit in the Interrupt Mask register is enabled,
VAGAIN = 7FFh
the IRQ output will also go active low. Thus the IRQ line can
VAGAIN = 000h
VAGAIN = 800h also be used to signal the end of a calibration.
80,0000h
The Line Apparent Energy accumulation uses the same
signal path as the Apparent Energy accumulation. The LSB
40,0000h size of these two registers is equivalent.

+
46 0
20,0000h
Σ
+
Apparent Power

LVAENERGY REGISTER IS
Time VADIV[7:0] UPDATED EVERY LINECYC
00,0000h ZERO-CROSSINGS WITH THE
4.9 7.4 11.1 14.8 (minutes) TOTAL APPARENT ENERGY
LPF1 DURING THAT DURATION

FROM ZERO 0
CALIBRATION 23
CHANNEL 2 CROSSING
ADC DETECTION CONTROL LVAENERGY[23:0]
Figure 46- Energy register roll-over time for full-scale
power (Minimum & Maximum Power Gain)
LINECYC[15:0]
Note that the Apparent Energy register contents roll-over to
full-scale negative (80,0000h) and continue increasing in
value when the power or energy flow is positive - see Figure Figure 47 - ADE7753 Apparent Energy Calibration
46.
By using the Interrupt Enable register, the ADE7754 can be
configured to issue an interrupt (IRQ) when the Apparent
Energy register is half full (positive or negative) or when an
over/under flow occurs.
REV. PrF 10/02 –25–
 PRELIMINARY TECHNICAL DATA
ADE7753
CALIBRATING THE ENERGY METER 2971.4 × 2 × 60
Frequency (CF) = = 1398.3Hz
When calibrating the ADE7753, the first step is to calibrate 255
the frequency on CF to some required meter constant, e.g., Alternatively, the average value from LPF2 under this con-
3200 imp/kWh. dition is approximately 1/16 of the full-scale level. As
A convenient way to to determine the output frequency on CF described previously, the average LPF2 output at full-scale
is to use the line cycle energy accumulation mode. As shown ac input is CCCCD (hex) or 838,861 (decimal). At 1/16 of
in Figure 37, DFC generates a pulse each time a LSB in the full-scale, the LPF2 output is then 52,428.81. Then using
LAENERGY register is accumulated. CF frequency (before Digital to Frequency Conversion, the frequency under this
the CF frequency divider) can be conveniently determined by load is calculated as:
the following expression: 52428.81× 3.579545MHz
Frequency(CF) = = 1398.3Hz
2 27
Content of LAENERGY[23 : 0] Register
CF Frequency = This is the frequency with the contents of the CFNUM and
Elasped Time CFDEN registers equal to 000h. The desired frequency out
is 3.9111Hz. Therefore, the CF frequency must be divided
When the CYCMODE (bit 7) bit in the Mode register is set
by 2797/3.9111Hz or 357.5 decimal. This is achieved by
to a logic one, energy is accumulated over an integer number
of half line cycles. If the line frequency is fixed and the loading the pair of CF Divider registers with the closest
number of half cycles of integration is specified, the total rational number. In this case, the closest rational number is
elasped time can be calculated by the following: found to be 1/358 (or 1h/166h). Therefore, 0h and 165h
should be written to the CFNUM and CFDEN registers
1 respectively. Note that the CF frequency is multiplied by the
Elasped Time = × number of half cycles
2 × fl contents of (CFNUM + 1) / (CFDEN + 1). With the CF
Divide registers contents equal to 1h/166h, the output
For example, at 60Hz line frequency, the elasped time for frequency is given as 2797Hz / 358 = 3.905Hz. This setting
255 half cycles will be 2.125 seconds. Rewriting the above in has an error of -0.1%.
terms of contents of various ADE7753 registers and line
Calibrating CF is made easy by using the Calibration mode
frequencies (fl):
on the ADE7753. The critical part of this approach is that the
LAENERGY[2 3 : 0] × 2 × fl line frequency needs to be exactly known. If this is not
CF Frequency = (24)
LINECYC[15 : 0] possible, the frequency can be measured by using the PE-
where fl is the line frequency. RIOD register of the ADE7753.
Alternatively, CF frequency can be calculated based on the Note that changing WGAIN[11:0] register will also affect
average LPF2 output. the output frequency from CF. The WGAIN register has a
Average LPF2 Output × CLKIN gain adjustment of 0.0244% / LSB.
CF Frequency= (25) Determine the kWHr/LSB Calibration Coefficient
2 27
The Active Energy register (AENERGY) can be used to
Calibrating the Frequency at CF calculate energy. A full description of this register can be
When the frequency before frequency division is known, the found in the Energy Calculation section. The AENERGY reg-
pair of CF Frequency Divider registers (CFNUM and ister gives the user both sign and magnitude information
CFDEN) can be adjusted to produce the required frequency regarding energy consumption. On completion of the CF
on CF. In this example a meter constant of 3200 imp/kWh frequency output calibration, i.e., after adjusting the CF
is chosen as an appropriate constant. This means that under Frequency divider and the Watt Gain (WGAIN) register, the
a steady load of 1kW, the output frequency on CF would be, second stage of the calibration is to determine the kWh/LSB
3200 imp / kWh 3200 coefficient for the AENERGY register. Equation 26 below
Frequency (CF ) = = = 0.8888 Hz shows how LAENERGY can be used to calculate the calibra-
60 min × 60 sec 3600 tion coefficient.
Assuming the meter is set up with a test current (basic
current) of 20A and a line voltage of 220V for calibration, the kWHr/LSB =
load is calculated as 220V × 20A = 4.4kW. Therefore the Calibration Power (in kW) LINECYC[15 : 0]
× (26)
expected output frequency on CF under this steady load 3600 seconds/Hr LAENERGY[23 : 0] × 2 × fl
condition would be 4.4 × 0.8888Hz = 3.9111Hz.
Under these load conditions the transducers on Channel 1 Once the coefficient is determined, the MCU can compute
and Channel 2 should be selected such that the signal on the the energy consumption at any time by reading the AENERGY
voltage channel should see approximately half scale and the contents and multiplying by the coefficient to calculate kWh.
signal on the current channel about 1/8 of full scale (assuming In the above example, at 4.4kW, after 255 half cycles (at
a maximum current of 80A). Assuming at line frequency of 60Hz), the resulting LAENERGY is approximately 2971
60Hz, energy is accumulated over FFh number of half line decimal. The kWHr/LSB can therefore be calculated to be
cycles, the resulting content of the LAENERGY register will 8.74×10-7 kWHr/LSB using the above equation.
be approximately 2971.4 (decimal). CF frequency is there-
fore calculated to be:
–26– REV. PrF 10/02
 PRELIMINARY TECHNICAL DATA
ADE7753
CLKIN FREQUENCY CHECKSUM REGISTER
In this datasheet, the characteristics of the ADE7753 is shown The ADE7753 has a Checksum register (CHECKSUM[5:0])
with CLKIN frequency equals 3.579545 MHz. However, the to ensure the data bits received in the last serial read operation
ADE7753 is designed to have the same accuracy at any are not corrupted. The 6-bit Checksum register is reset
CLKIN frequency within the specified range. If the CLKIN before the first bit (MSB of the register to be read) is put on
frequency is not 3.579545MHz, various timing and filter the DOUT pin. During a serial read operation, when each
characteristics will need to be redefined with the new CLKIN data bit becomes available on the rising edge of SCLK, the
frequency. For example, the cut-off frequencies of all digital bit will be added to the Checksum register. In the end of the
filters (LPF1, LPF2, HPF1, etc.) will shift in proportion to serial read operation, the content of the Checksum register
the change in CLKIN frequency according to the following will equal to the sum of all ones in the register previously
equation: read. Using the Checksum register, the user can determine
if an error has occured during the last read operation.
CLKIN Frequency Note that a read to the Checksum register will also generate
New Frequency = Original Frequency × (27)
3.579545 MHz a checksum of the Checksum register itself.
The change of CLKIN frequency does not affect the timing
DOUT CONTENT OF REGISTER (n-bytes)
characteristics of the serial interface because the data transfer
is synchronized with serial clock signal (SCLK). But one
needs to observe the read/write timing of the serial data +

transfer-see ADE7753 Timing Characteristics. Table III lists Σ CHECKSUM REGISTER ADDR: 3Eh
+
various timing changes that are affected by CLKIN fre-
quency. Figure 48– Checksum register for Serial Interface Read

Table III
Frequency dependencies of the ADE7753 parameters

Parameter CLKIN dependency

Nyquist frequency for CH 1&2 ADCs CLKIN/8

PHCAL resolution (seconds per LSB) 4/CLKIN
Active Energy register update rate (Hz) CLKIN/4
Waveform sampling rate (Number of samples per second)
WAVSEL 1,0 = 0 0 CLKIN/128
0 1 CLKIN/256
1 0 CLKIN/512
1 1 CLKIN/1024
Maximum ZXTOUT period 524,288/CLKIN

SUSPENDING THE ADE7753 FUNCTIONALITY

The analog and the digital circuit can be suspended sepa-
rately. The analog portion of the ADE7753 can be suspended
by setting the ASUSPEND bit (bit 4) of the Mode register
to logic high See Mode Register. In suspend mode, all
waveform samples from the ADCs will be set to zeros. The
digital circuitry can be halted by stopping the CLKIN input
and maintaining a logic high or low on CLKIN pin. The
ADE7753 can be reactivated by restoring the CLKIN input
and setting the ASUSPEND bit to logic low.

REV. PrF 10/02 –27–

 PRELIMINARY TECHNICAL DATA
ADE7753
ADE7753 SERIAL INTERFACE
The Serial Interface of the ADE7753 is made up of four
All ADE7753 functionality is accessible via several on-chip signals SCLK, DIN, DOUT and CS. The serial clock for a
registers – see Figure 49. The contents of these registers can data transfer is applied at the SCLK logic input. This logic
be updated or read using the on-chip serial interface. After input has a schmitt-trigger input structure, which allows slow
power-on or toggling the RESET pin low or a falling edge rising (and falling) clock edges to be used. All data transfer
on CS, the ADE7753 is placed in communications mode. In operations are synchronized to the serial clock. Data is
communications mode the ADE7753 expects a write to its shifted into the ADE7753 at the DIN logic input on the
Communications register. The data written to the communi- falling edge of SCLK. Data is shifted out of the ADE7753 at
cations register determines whether the next data transfer the DOUT logic output on a rising edge of SCLK. The CS
operation will be read or a write and also which register is logic input is the chip select input. This input is used when
accessed. Therefore all data transfer operations with the multiple devices share the serial bus. A falling edge on CS
ADE7753, whether a read or a write, must begin with a write also resets the serial interface and places the ADE7753 in
to the Communications register. communications mode. The CS input should be driven low
for the entire data transfer operation. Bringing CS high
during a data transfer operation will abort the transfer and
DIN COMMUNICATIONS REGISTER
place the serial bus in a high impedance state. The CS logic
IN
input may be tied low if the ADE7753 is the only device on
DOUT REGISTER # 1 OUT
the serial bus. However with CS tied low, all initiated data
transfer operations must be fully completed, i.e., the LSB of
REGISTER ADDRESS

IN
REGISTER # 2 OUT
each register must be transferred as there is no other way of
DECODE

REGISTER # 3 IN
OUT bringing the ADE7753 back into communications mode
without resetting the entire device, i.e., using RESET.

ADE7753 Serial Write Operation

REGISTER # n-1 IN The serial write sequence takes place as follows. With the
OUT
ADE7753 in communications mode (i.e. the CS input logic
REGISTER # n
IN
OUT low), a write to the communications register first takes place.
The MSB of this byte transfer is a 1, indicating that the data
transfer operation is a write. The LSBs of this byte contain
Figure 49– Addressing ADE7753 Registers via the
the address of the register to be written to. The ADE7753
Communications Register
starts shifting in the register data on the next falling edge of
SCLK. All remaining bits of register data are shifted in on the
The Communications register is an eight bit wide register.
falling edge of subsequent SCLK pulses – see Figure 51.
The MSB determines whether the next data transfer opera-
As explained earlier the data write is initiated by a write to the
tion is a read or a write. The 5 LSBs contain the address of
communications register followed by the data. During a data
the register to be accessed. See ADE7753 Communications Register
write operation to the ADE7753, data is transferred to all on-
for a more detailed description.
chip registers one byte at a time. After a byte is transferred
Figure 50 and 51 show the data transfer sequences for a read
into the serial port, there is a finite time before it is transferred
and write operation respectively.
to one of the ADE7753 on-chip registers. Although another
On completion of a data transfer (read or write) the ADE7753
byte transfer to the serial port can start while the previous byte
once again enters communications mode.
is being transferred to an on-chip register, this second byte
CS transfer should not finish until at least 4µs after the end of the
previous byte transfer. This functionality is expressed in the
SCLK
timing specification t6 - see Figure 51. If a write operation is
COMMUNICATIONS REGISTER WRITE
DIN
aborted during a byte transfer (CS brought high), then that
0 0 0 ADDRESS
byte will not be written to the destination register.
DOUT MULTIBYTE READ DATA Destination registers may be up to 3 bytes wide – see ADE7753
Register Descriptions. Hence the first byte shifted into the serial
port at DIN is transferred to the MSB (Most significant Byte)
Figure 50– Reading data from the ADE7753 via the serial of the destination register. If the addressed register is 12 bits
interface wide, for example, a two-byte data transfer must take place.
CS The data is always assumed to be right justified, therefore in
this case, the four MSBs of the first byte would be ignored and
SCLK
the 4 LSBs of the first byte written to the ADE7753 would be
COMMUNICATIONS REGISTER WRITE
the 4MSBs of the 12-bit word. Figure 52 illustrates this
DIN 1 0 0 ADDRESS MULTIBYTE WRITE DATA
example.
Figure 51– Writing data to the ADE7753 via the serial inter-
face
A data transfer is complete when the LSB of the ADE7753
register being addressed (for a write or a read) is transferred
to or from the ADE7753.

–28– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
t8
CS
t1 t2 t3 t6
t7 t7
SCLK
t4
t5

DIN 1 0 0 A4 A3 A2 A1 A0 DB7 DB0 DB7 DB0

Command Byte Most Significant Byte Least Significant Byte

Figure 52 – Serial Interface Write Timing Diagram

SCLK

DIN X X X X DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Most Significant Byte Least Significant Byte

Figure 53—12 bit Serial Write Operation

ADE7753 Serial Read Operation

During a data read operation from the ADE7753 data is output enters a high impedance state on the falling edge of the
shifted out at the DOUT logic output on the rising edge of last SCLK pulse. The read operation may be aborted by
SCLK. As was the case with the data write operation, a data bringing the CS logic input high before the data transfer is
read must be preceded with a write to the Communications complete. The DOUT output enters a high impedance state
register. on the rising edge of CS.
With the ADE7753 in communications mode (i.e. CS logic When an ADE7753 register is addressed for a read operation,
low) an eight bit write to the Communications register first the entire contents of that register are transferred to the serial
takes place. The MSB of this byte transfer is a 0, indicating port. This allows the ADE7753 to modify its on-chip
that the next data transfer operation is a read. The LSBs of registers without the risk of corrupting data during a multi
this byte contain the address of the register which is to be byte transfer.
read. The ADE7753 starts shifting out of the register data on Note when a read operation follows a write operation, the
the next rising edge of SCLK – see Figure 54. At this point read command (i.e., write to communications register)
the DOUT logic output leaves its high impedance state and should not happen for at least 4µs after the end of the write
starts driving the data bus. All remaining bits of register data operation. If the read command is sent within 4µs of the write
are shifted out on subsequent SCLK rising edges. The serial operation, the last byte of the write operation may be lost.
interface also enters communications mode again as soon as The is given as timing specification t9.
the read has been completed. At this point the DOUT logic

CS
t1 t13
t9 t10
SCLK

DIN 0 0 0 A4 A3 A2 A1 A0
t11 t11 t12

DOUT DB7 DB0 DB7 DB0

Command Byte Most Significant Byte Least Significant Byte

Figure 54– Serial Interface Read Timing Diagram

REV. PrF 10/02 –29–

 PRELIMINARY TECHNICAL DATA
ADE7753 ADE7753 REGISTER LIST
Address Name R/W # of Bits Default Description

01h WAVEFORM R 24 bits 0h The Waveform register is a read-only register. This register
contains the sampled waveform data from either Channel 1,
Channel 2 or the Active Power signal. The data source and the
length of the waveform registers are selected by data bits 14 and
13 in the Mode Register - see Channel 1 & 2 Sampling.
02h AENERGY R 24 bits 0h The Active Energy register. Active Power is accumulated
(Integrated) over time in this 24-bit, read-only register. The
energy register can hold a minimum of 6 seconds of Active
Energy information with full scale analog inputs before it
overflows - see Energy Calculation.
03h RAENERGY R 24 bits 0h Same as the Active Energy register except that the register is
reset to zero following a read operation
04h LAENERGY R 24 bits 0h Line Accumulation Active Energy register. The instantaneous
active power is accumulated in this read-only register over the
LINCYC number of half line cycles.
05h VAENERGY R 24 bits 0h Apparent Energy register. Apparent power is accumulated over
time in this read-only register.
06h RVAENERGY R 24 bits 0h Same as the VAENERGY register except that the register is reset
to zero following a read operation.
07h LVAENERGY R 24 bits 0h Apparent Energy register. The instantaneous real power is
accumulated in this read-only register over the LINECYC
number of half line cycles
08h LVARENERGY R 24 bits 0h Reactive Energy register. The instantaneous reactive power is
accumulated in this read-only register over the LINECYC
number of half line cycles.
09h MODE R/W 16 bits 000Ch The Mode register. This is a 16-bit register through which most
of the ADE7753 functionality is accessed. Signal sample rates,
filter enabling and calibration modes are selected by writing to
this register. The contents may be read at any time—see Mode
Register.
0Ah IRQEN R/W 16 bits 40h Interrupt Enable register. ADE7753 interrupts may be
deactivated at any time by setting the corresponding bit in this 8-
bit Enable register to logic zero. The Status register will
continue to register an interrupt event even if disabled. However,
the IRQ output will not be activated—see ADE7753 Interrupts.
0Bh STATUS R 16 bits 0h The Interrupt Status register. This is an 8-bit read-only register.
The Status Register contains information regarding the source of
ADE7753 interrupts - see ADE7753 Interrupts.
0Ch RSTSTATUS R 16 bits 0h Same as the Interrupt Status register except that the register
contents are reset to zero (all flags cleared) after a read
operation.
0Dh CH1OS R/W 8 bits 00h Channel 1 Offset Adjust. Bit 6 is not used. Writing to bits 0 to 5
allows offsets on Channel 1 to be removed – see Analog Inputs
and CH1OS Register. Writing a logic one to the MSB of this
register enables the digital integrator on Channel 1, a zero
disables the integrator. The default value of this bit is zero.
0Eh CH2OS R/W 8 bits 0h Channel 2 Offset Adjust. Bit 6 and 7 not used. Writing to bits 0
to 5 of this register allows any offsets on Channel 2 to be
removed - see Analog Inputs.
0Fh GAIN R/W 8 bits 0h PGA Gain Adjust. This 8-bit register is used to adjust the gain
selection for the PGA in Channel 1 and 2 - see Analog Inputs.

–30– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
Address Name R/W # of Bits Default Description

10h PHCAL R/W 6 bits 0Dh Phase Calibration register. The phase relationship between
Channel 1 and 2 can be adjusted by writing to this 6-bit register.
The valid content of this 2's compliment register is between 1Dh
to 21h. At line frequency of 60Hz, this is a range from -2.06 to
+0.7 degrees. —see Phase Compensation.
11h APOS R/W 16 bits 0h Active Power Offset Correction. This 16-bit register allows small
offsets in the Active Power Calculation to be removed – see
Active Power Calculation.
12h WGAIN R/W 12 bits 0h Power Gain Adjust. This is a 12-bit register. The Active Power
calculation can be calibrated by writing to this register. The
calibration range is ±50% of the nominal full scale active power.
The resolution of the gain adjust is 0.0244% / LSB—see Channel
1 ADC Gain Adjust.
13h WDIV R/W 8 bits 0h Active Energy divider register. The internal active energy register
is divided by the value of this register before being stored in the
AENERGY register.
14h CFNUM R/W 12 bits 3Fh CF Frequency Divider Numerator register. The output frequency
on the CF pin is adjusted by writing to this 12-bit read/write
register – see Energy to Frequency Conversion.
15h CFDEN R/W 12 bits 3Fh CF Frequency Divider Denominator register. The output
frequency on the CF pin is adjusted by writing to this 12-bit
read/write register – see Energy to Frequency Conversion.
16h IRMS R 24 bits 0h Channel 1 RMS value (current channel).
17h VRMS R 24 bits 0h Channel 2 RMS value (voltage channel).
18h IRMSOS R/W 12 bits 0h Channel 1 RMS offset correction register
19h VRMSOS R/W 12 bits 0h Channel 2 RMS offset correction register
1Ah VAGAIN R/W 12 bits 0h Apparent Gain register. Apparent power calculation can be
calibrated by writing this register. The calibration range is 50%
of the nominal full scale real power. The resolution of the gain
adjust is 0.02444% / LSB.
1Bh VADIV R/W 8 bits 0h Apparent Energy divider register. The internal apparent energy
register is divided by the value of this register before being stored
in the VAENERGY register.
1Ch LINECYC R/W 15 bits FFFh Line Cycle Energy Accumulation Mode Line-Cycle register.
This 15-bit register is used during line cycle energy
accumulation mode to set the number of half line cycles for
energy accumulation - see Line Cycle Energy Accumulation Mode.
1Dh ZXTOUT R/W 12 bits FFFh Zero-cross Time Out. If no zero crossings are detected on
Channel 2 within a time period specified by this 12-bit register,
the interrupt request line (IRQ) will be activated. The maximum
time-out period is 0.15 second - see Zero Crossing Detection.
1Eh SAGCYC R/W 8 bits FFh Sag line Cycle register. This 8-bit register specifies the number
of consecutive line cycles the signal on Channel 2 must be below
SAGLVL before the SAG output is activated - see Voltage Sag
Detection
1Fh SAGLVL R/W 8 bits 0h Sag Voltage Level. An 8-bit write to this register determines at
what peak signal level on Channel 2 the SAG pin will become
active. The signal must remain low for the number of cycles
specified in the SAGCYC register before the SAG pin is
activated—see Line Voltage Sag Detection.
20h IPKLVL R/W 8 bits FFh Channel 1 Peak Level threshold (current channel). This register
sets the level of the current peak detection. If the channel 1 input
exceeds this level, the PKI flag in the status register is set.

REV. PrF 10/02 –31–

 PRELIMINARY TECHNICAL DATA
ADE7753
Address Name R/W # of Bits Default Description

21h VPKLVL R/W 8 bits FFh Channel 2 Peak Level threshold (voltage channel). This register
sets the level of the voltage peak detection. If the channel 2 input
exceeds this level, the PKV flag in the status register is set.
22h IPEAK R 24 bits 0h Channel 1 peak register. The maximum input value of the
Current channel since the last read of the register is stored in this
register.
23h RSTIPEAK R 24 bits 0h Same as Channel 1 peak register except that the register contents
are reset to 0 after read.
24h VPEAK R 24 bits 0h Channel 2 peak register. The maximum input value of the
Voltage channel since the last read of the register is stored in this
register.
25h RSTVPEAK R 24 bits 0h Same as Channel 2 peak register except that the register contents
are reset to 0 after a read.
26h TEMP R 8 bits 0h Temperature register. This is an 8-bit register which contains the
result of the latest temperature conversion – see Temperature
Measurement.
27h PERIOD R 15 bits 0h Period of the channel 2 (volatge channel) input estimated by
Zero-crossing processing.
28h-
3Ch Reserved
3Dh TMODE R/W 8 bits - Test mode register
3Eh CHKSUM R 6 bits 0h Checksum Register. This 6-bit read only register is equal to the
sum of all the ones in the previous read – see ADE7753 Serial Read
Operation.
3Fh DIEREV R 8 bits - Die Revision Register. This 8-bit read only register contains the
revision number of the silicon.

ADE7753 REGISTER DESCRIPTIONS

All ADE7753 functionality is accessed via the on-chip registers. Each register is accessed by first writing to the
communications register and then transferring the register data. A full description of the serial interface protocol is given in
the Serial Interface section of this data sheet.

Communications Register
The Communications register is an 8-bit, write-only register which controls the serial data transfer between the ADE7753
and the host processor. All data transfer operations must begin with a write to the communications register. The data written
to the communications register determines whether the next operation is a read or a write and which register is being accessed.
Table IV below outlines the bit designations for the Communications register.
Table V. Communications Register

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

W/R 0 A5 A4 A3 A2 A1 A0

Bit Bit Description

Location Mnemonic

0 to 5 A0 to A5 The six LSBs of the Communications register specify the register for the data transfer
operation. Table III lists the address of each ADE7753 on-chip register.
6 RESERVED This bit is unused and should be set to zero.
7 W/ R When this bit is a logic one the data transfer operation immediately following the write to
the Communications register will be interpreted as a write to the ADE7753. When this bit
is a logic zero the data transfer operation immediately following the write to the
Communications register will be interpreted as a read operation.

–32– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
Mode Register (09H)
The ADE7753 functionality is configured by writing to the MODE register. Table VI below summarizes the functionality
of each bit in the MODE register .
Table VI : Mode Register
Bit Bit Default
Location Mnemonic Value Description

0 DISHPF 0 The HPF (High Pass Filter) in Channel 1 is disabled when this bit is set.
1 DISLPF2 0 The LPF (Low Pass Filter) after the multiplier (LPF2) is disabled when this bit is set.
2 DISCF 1 The Frequency output CF is disabled when this bit is set
3 DISSAG 1 The line voltage Sag detection is disabled when this bit is set
4 ASUSPEND 0 By setting this bit to logic one, both ADE7753's A/D converters can be turned off. In
normal operation, this bit should be left at logic zero. All digital functionality can be
stopped by suspending the clock signal at CLKIN pin.
5 TEMPSEL 0 The Temperature conversion starts when this bit is set to one. This bit is automatically
reset to zero when the Temperature conversion is finished.
6 SWRST 0 Software chip reset. A data transfer should not take place to the ADE7753 for at least 18µs
after a software reset.
7 CYCMODE 0 Setting this bit to a logic one places the chip in line cycle energy accumulation mode.
8 DISCH1 0 ADC 1 (Channel 1) inputs are internally shorted together.
9 DISCH2 0 ADC 2 (Channel 2) inputs are internally shorted together.
10 SWAP 0 By setting this bit to logic 1 the analog inputs V2P and V2N are connected to ADC 1 and
the analog inputs V1P and V1N are connected to ADC 2.
12, 11 DTRT1,0 00 These bits are used to select the Waveform Register update rate
DTRT 1 DTRT0 Update Rate
0 0 27.9kSPS (CLKIN/128)
0 1 14kSPS (CLKIN/256)
1 0 7kSPS (CLKIN/512)
1 1 3.5kSPS (CLKIN/1024)
14, 13 WAVSEL1,0 00 These bits are used to select the source of the sampled data for the Waveform Register
WAVSEL1,0 Length Source
0 0 24 bits Active Power signal (output of LPF2)
0 1 Reserved
1 0 24 bits Channel 1
1 1 24 bits Channel 2
15 POAM 0 Writing a logic one to this bit will allow only positive power to be accumulated in the
ADE7753. The default value of this bit is 0.
MODE REGISTER*

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 ADDR: 09H

POAM DISHPF
(Positive Only Accumulation) (Disable HPF in Channel 1)
WAVSEL DISLPF2
(Wave form selection for sample mode) (Disable LPF2 after multiplier)
00 = LPF2
01= Reserved DISCF
10 = CH1 (Disable Frequency output CF)
11 = CH2 DISSAG
DTRT (Disable SAG output)
(Waveform samples output data rate) ASUSPEND
00 = 27.9kSPS (CLKIN/128)
(Suspend CH1&CH2 ADC’s)
01 = 14.4 kSPS (CLKIN/256)
10 = 7.2 kSPS (CLKIN/512) STEMP
11 = 3.6 kSPS (CLKIN/1024) (Start temperature sensing)
SWRST
SWAP
(Software chip reset)
(Swap CH1 & CH2 ADCs)
CYCMODE
DISCH2
(Line Cycle Energy Accumulation Mode)
(Short the analog inputs on Channel 2)

DISCH1
(Short the analog inputs on Channel 1)

*Register contents show power on defaults

REV. PrF 10/02 –33–

 PRELIMINARY TECHNICAL DATA
ADE7753
Interrupt Status Register (0BH) / Reset Interrupt Status Register (0CH) /Interrupt Enable Register (0Ah)
The Status Register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs
in the ADE7753, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is logic
one in the Interrupt Enable register, the IRQ logic output goes active low. When the MCU services the interrupt it must first
carry out a read from the Interrupt Status Register to determine the source of the interrupt.

Table VII: Interrupt Status Register, Reset Interrupt Status Register & Interrupt Enable Register
Bit Interrupt
Location Flag Description

0h AEHF Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active
Energy register (i.e. the AENERGY register is half full)
1h SAG Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were
detected.
2h CYCEND Indicates the end of energy accumulation over an integer number of half line cycles as
defined by the content of the LINECYC Register—see Line Cycle Energy Accumulation Mode
3h WSMP Indicates that new data is present in the Waveform Register.
4h ZX This status bit reflects the status of the ZX logic ouput—see Zero Crossing Detection
5h TEMP Indicates that a temperature conversion result is available in the Temperature Register.
6h RESET Indicates the end of a reset (for both software or hardware reset). The corresponding
enable bit has no function in the Interrupt Enable Register, i.e. this status bit is set at
the end of a reset, but it cannot be enabled to cause an interrupt.
7h AEOF Indicates that the Active Energy register has overflowed.
8h PKV Indicates that waveform sample from Channel2 has exceeded the VPKLVL value.
9h PKI Indicates that waveform sample from Channel1 has exceeded the IPKLVL value.
Ah VAEHF Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Apparent
Energy register (i.e. the VAENERGY register is half full)
Bh VAEOF Indicates that the Apparent Enrgy register has overflowed.
Ch ZXTO Indicates that an interrupt was caused by a missing zero crossing on the line voltage for the
specified number of line cycles—see Zero Crossing Time Out
Dh PPOS Indicates that the power has gone from negative to positive.
Eh PNEG Indicates that the power has gone from positive to negative.
Fh RESERVED Reserved

–34– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753

OUTLINE DIMENSIONS
Dimensions shown in inches and (mm)

20-Shrink Small Outline Package

(RS-20)

0.295 (7.50)
0.271 (6.90)

20 11

0.301 (7.64)

0.212 (5.38)
0.205 (5.21)
0.311 (7.9)
1 10

0.078 (1.98) PIN 1 0.07 (1.78)

0.068 (1.73) 0.066 (1.67)

8° 0.037 (0.94)
0.008 (0.203) 0.0256 0° 0.022 (0.559)
SEATING 0.009 (0.229)
(0.65)
0.002 (0.050) PLANE 0.005 (0.127)
BSC

REV. PrF 10/02 –35–

 PRELIMINARY TECHNICAL DATA
ADE7753
ADE7753 ERRATA (REV 1.0)
The following is a list of known issues with the first revision
of the ADE7753 silicon (rev 1.0). These issues will be
resolved in the next version. Samples of this version of the
silicon can be identified from the content of the DIEREV
regsiter (Address 3Fh). The content of DIEREV register is
2 for Rev 1.2 silicon. In addition, the branding on top of the
package for Rev 1.2 should be as shown below:
20 11

AD7753
XRS
0240
K58207
1 10

ERRATA

1. SAGCYC
The contents of SAGCYC register is equivalent to
(SAGCYC-1). For example, if the desired number of
linecycles for SAG detection is 20d line cycles, one should
write 21d to the SAGCYC Register. This is not a silicon
bug.
2. CFNUM and CFDEN
CFNUM should always be less than CFDEN. The behav-
ior of the output frequency is not guaranteed for CF. This
is not a silicon bug.

–36– REV. PrF 10/02

 PRELIMINARY TECHNICAL DATA
ADE7753
REVISION HISTORY
The main reason for revising the datasheet from version Pr.D Page 26
to Pr.F is to correct some of the mistakes contained in the 1. Equation 25 changed to have 2^27 bits for the denomina-
Pr.D and Pr.E version. In addition, changes were made to the tor.
silicon to fix bugs noted in the Errata list and to modify the 2. Content of LAENERGY register is 2971.4, and the CF
product definition. The list below highlights the important frequency output in the example calculation is 1398.3 Hz.
changes from Pr.D to Pr.F. Note that all page numbers are
referring to that of Pr.F. 3. The calculation of CFNUM and CFDEN changed
according to the effect of the abovementioned changes.
Page 4
Read timing t9 is determined to be 3.1us. Page 31
1. The definition of the SAGCYC a register has changed to
Page 12 full line cycles. LINECYC corrected to say 15 bits and
The SAGCYC register value represents full-line cycles and remains half line cycles.
not half-line cycles. The line voltage SAG detection section 2. The PHCAL register description changed to reflect the
text was changed to reflect this design update. Figure 13 new effective length and resolution of the register and default
shows 3 line cycles, 3h in the SAGCYC register, changed value of 0D.
from 6 half line cycles, 6h in the SAGCYC register. The
section explaining Figure 13 has also changed accordingly.
Page 13
Peak Level record section was changed to show that the
quantity stored in VPEAK register is 2 times the absolute
value of the WAVEFORM register contents for CH2. IPEAK
is 1 times the absolute value of the CH1 Waveform.

Page 18
1. The phase calibration register resolution has changed to
0.048 from 0.024. This section calculations have been
changed to reflect this new resolution.
2. Figure 27 updated with new PHCAL range and delay
block rate.

Page 20
Figure 36 Timing was updated.

Page 21
1. The internal active energy accumulation register is 47 bits
instead of 53 bits. The equation also shows this change. This
change is also implemented in the equations of page 25 as
well as Figures 45 and 47 on page 25.
2. The maximum output frequency is changed to 23Hz.
3. Text added to explain CFNUM must be less than
CFDEN.

Page 22
1. Figure 39 shows the actual internal register length to be 47
bits. This change is also on page 23, Figure 41.
2. Line Cycle Energy accumulation mode section changed to
15 bits for LINECYC Register.

REV. PrF 10/02 –37–

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