TWO-STAGE MILLER

COMPENSATION OTA PROJECT

Jaewoo Kim
02/17/2025
1. Introduction
The purpose of this project is understanding and performing two-stage Miller
compensation OTA by using Cadence Virtuoso, TSMC 130nm technology. By designing two-
stage Miller compensation OTA and making test benches, it is required to understand the
structural characteristics of Miller compensation OTA, confirm fundamental features of the
analog circuits like overdrive margin, saturation margin or offset and different types of circuit
analysis like DC, AC or transient analysis. The specification of the two-stage Miller
copmensation OTA is presented and guidance is provided by Amit Bar, analog IC design
engineer.
Differential pair op-amp is widely used in real industries. Since two different inputs’
offset noise can be eliminated, it has more stable and noiseless output. Among differential pair
op-amp, 5T OTA has tail current. The tail MOSFET has many positive features. One of the main
pros of using tail MOSFET is that it is much better to provide current source using current-mirror,
and the other one is that the tail current source can provide better common-mode rejection and
stable bias.
Even though the 5T OTA has higher gain than the op-amp without tail-current source, 2nd
stage circuit is applied for better gain. Also, compensation circuit is implemented to the 2nd stage
of the Miller compensation OTA. The compensation circuit provides 2 poles which are very close
to each other make it far from each other and become stable system. So the table of the two-stage
Miller compensation OTA specification is shown below.

Features Value
VDD 1.8 V
Vref 1.2 V
UGB > 1M Hz
Cload 1p F
DC gain > 75 dB
Quiescent Current < 10u A
Phase Margin > 55°
Table. Two-stage Miller compensation OTA Specification
2. DC Analysis
To start analysis, it is required to make circuits and test benches. The two-stage Miller
copmensation OTA circuit for this project is shown below. It consists of current-mirror source,
tail-current, differential input stage, and 2nd stage with compensation circuit. The basic aspect
ratio of the each transistor is W=350nm/L=350nm for nmos and W=300nm/L=350nm for pmos
transistors. The compensation circuit C and R are set as conventional figures, like 1p F and 1k
Ohm.

Fig.1. 2-stage 5T OTA

After two-stage Miller compensation OTA circuit is generated, it is necessary to make

test bench which OTA symbol will be applied. There are 2 inputs of OTA. One of the input
voltage is dc voltage and the other one is connected to the output. The load capacitance is at the
output. Ibias for current-mirror source goes to the OTA. At first time, the VDD = 1.8 V, Vref =
1.2 V, Cload = 1p F, and the current bias is 2u A. After the test bench is generated, the corner is
set. Since the model is different from each technologies, The model set is shown below.
 Fig.2. Test Bench & Corner Setup

In DC analysis, operating point of each transistors, overdrive margin, saturation margin,

offset, and ICMR values are estimated. The operating point of each transistor is easily
discriminated by the operating parameter annotation, ‘region’ (If the region = 2, the transistor is
in saturation region). The overdrive margin is the value of (Vgs – Vth). It will determine the
operating point. The saturation margin is the value of (Vds - Vdsat). It will determine the voltage
difference at saturation region. The smaller the better. The offset value is the voltage difference
between positive input and negative input. Micro-unit voltage is typical range of the offset. And
ICMR is ‘input common-mode range’. It will determine the range of the input offset.
The multiplier of each transistor is set as 2. Since the current-mirror need to transfer the
current from the source to the other stages, the L parameter would be larger, for example 800um.
The overdrive margin should be larger than 10m, and the saturation margin should be larger than
50m. The acceptable value of the offset is less than few hundreds micro volt. After the width and
multiplier of the M7 increase to 500nm and 4, the offset becomes decrease. The final operating
annotation and design parameter of the 5T OTA are shown below.
 Fig.3. Current Mirror Design Parameter.

Fig.4. Design Parameter & Operating Parameter of the OTA after DC Analysis
 Fig.5. Output Voltage, Offset, Overdrive Margin, Saturation Margin, and ICMR

The ICMR minimum and maximum values determine the range of the input offset. The transistors of
input differential pair are used to get ICMR values.

ICMR.min = Vgs.input + Vdsat.tail

ICMR.max = Vdd – Vgs.p + Vth

3. STB & AC Analysis

There are 2 ways to start to ac analysis. One is ‘stb’ analysis and the other one is ‘ac’
analysis. The first trial of the ‘stb’ analysis bode plot is shown below. By using ‘stb’ analysis GM
(gain margin) and PM (phase margin) are easily confirmed. In the test bench for ‘stb’ analysis,
iprobe is applied to the feedback. According to the first trial bode plot, DC gain is 71 dB which is
not enough and PM is also small.
To get large phase margin, compensation circuit adjustment is required. Typically the
compensation capacitance is 0.22 times larger than the load capacitance (Cc > 0.22*Cl), and the
compensation resistance is larger than the input resistance (Rc > 1/gm2). Since the required load
capacitance is 1p F, the compensation capacitance should be larger than 220f F. Also, the
compensation resistance is larger than 30k Ohm. In this project, Cc = 1.3f F and Rc = 30k Ohm.
Since TSMC 130nm technology usually use crtmom cap, the correct size of the capacitor was set.
 Fig.6. STB Analysis Test Bench

Fig.7. Phase Margin

To increase the DC gain, which is loop gain, gm or output resistance should increase. To
increase gm, drain current or aspect ratio increase or the current bias should decrease. For
example, the bias current decrease from 2u A to 1u A. Since the quiescent current should be
smaller than 10u A, it is okay to use 1u A bias current. Also, to increase the trans-conductance,
pmos multiplier decrease from 2 to 1.
 Fig.8. Design Parameter & Operating Parameter of the OTA after STB Analysis

PSR, power supply ratio, can also be estimated. In this case, the ac signal is applied to the
VDD. The test bench for PSR and its plot result are shown below.

Fig.9. Test Bench for PSR

 Fig.10. PSR Result

The other way to perform ac analysis is ‘AC’ analysis. Since it requires ac signal, ac
component of the input voltage applied, and inductance and capacitance instances are applied to
feedback circuit. By doing so, it shows bode plot, gain margin, phase margin, and unity gain
bandwidth. To increase the unity gain bandwidth, the compensation capacitance decreases. Since
it is required to block ac noise from output to input and the noise should be bypassed to the VSS,
the inductance is serially connected to the feedback and the capacitor is connect between the
feedback and VSS. The unity gain bandwidth increases by decreasing Cc.

Fig.11. Test Bench for AC Analysis

Fig.12. Design Parameter & Operating Parameter of the OTA after AC Analysis
 Fig.13. Increased DC Gain, PM, and UGB

4. Transient & Noise Analysis

Transient analysis shows the input and output voltage with respect to time. Since it is
performed in time domain, Vsin instance is applied to the input. In this project, 100k Hz
frequency input is used. Also, the test bench for transient analysis doesn’t have feedback.
According to the plot, the output signal is amplified and fortunately it is not clipped. On the other
hand, the noise analysis test bench has dc input and feedback. To get output referred noise it is
necessary to select the output noise node first and then get input referred noise dividing it by gain.

Fig.14. Test Bench for Transient Analysis

 Fig.15. Test Bench for Noise Analysis

Fig.16. Transient Plot, Output Referred Noise, Input Referred Noise

5. Conclusion
By performing different types of analysis, which are dc, stb, ac, transient, and noise
analysis, it was helpful to design 2-stage Miller compensation OTA, where the supply voltage is
1.8 V, reference voltage is 1.2 V, unity gain bandwidth is 1.129M Hz, load capacitance is 1p F,
DC gain is 75.7 dB, quiescent current is 4.06u A, and phase margin is 71.88°. To meet the
requirement, it was essential to adjust the width, length, compensation circuit, bias current, and
multipliers. It was easy to confirm that the flow of the analysis could critically affect the results of
the system.