Advanced Digital Circuit Design
- Test Benches
for Combinational Circuits
Prof. Dr. Berna Örs Yalçın
Istanbul Technical University
Faculty of Electrical and Electronics Engineering
Department of Electronics and Communication
Engineering
[email protected] 1
Test Benches
• A test bench is an HDL program for applying stimulus to an HDL
model and observe its response.
• A good test bench should be written to exercise as many
functional features of a circuit as possible.
• process begin ... end process; phrase is used to provide
stimulus to a circuit to be tested.
• An process begin ... end process; phrase is executed only once,
starting at time 0.
• An process begin ... end process; block includes operations
that are delayed by a given number of time units.
2
The process Block
process
begin
A = 0; B=0;
wait for 10 ns;
A=1;
wait for 20 ns;
A=0; B=1;
end process;
3
Stimulus for Generation for
Combinational Circuits
process
begin
D = 000;
for i in 1 to 7 loop
wait for 10 ns;
D = D + 001;
end loop;
end process;
The above code can be used to generate stimulus for a 3 input
combinational circuit and obtain its truth table.
4
Writing a Test Bench for an Entity under Test
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; • A test bench entity is written as
USE ieee.numeric_std.ALL; any other VHDL entity but it has
use ieee.std_logic_arith.all; no inputs or outputs.
...
ENTITY entity_name_tb IS
END entity_name_tb; • The signals that are applied as
ARCHITECTURE behavioral OF entity_name_tb IS inputs to the entity under test are
// Declare the design entity under test. declared as signal data type.
COMPONENT entity_name PORT( ...);
END COMPONENT;
• The outputs of the entity under
// Declare local signals test are declared in the test
SIGNAL input ports module as signal data type.
SIGNAL output ports
CONSTANT period : time := 10 ns;
BEGIN
// Instantiate the design module under test.
UUT: entity_name PORT MAP(...);
// Generate stimulus
stim_proc: process BEGIN
input signal <= value;
WAIT FOR period;
....
WAIT;
end process;
END;
5
Interaction Between Stimulus and Design Entities
library IEEE; library IEEE;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ripple_carry_adder_tb is
entity ripple_carry_adder is generic (n : integer := 8);
generic (n : integer := 8); end ripple_carry_adder_tb;
Port ( A : in std_logic_vector (n-1 downto 0); architecture Behavioral of ripple_carry_adder_tb is
B : in std_logic_vector (n-1 downto 0); component ripple_carry_adder is
C0 : in std_logic; generic (n : integer := 8);
Port ( A : in std_logic_vector (n-1 downto 0);
S : out std_logic_vector (n downto 0));
B : in std_logic_vector (n-1 downto 0);
end ripple_carry_adder; C0 : in std_logic;
S : out std_logic_vector (n downto 0));
architecture Gate_Level of ripple_carry_adder is end component;
component full_adder is signal A_t,B_t : std_logic_vector (n-1 downto 0);
Port ( x : in std_logıc; signal C0_t : std_logic;
signal S_t : std_logic_vector (n downto 0);
y : in std_logic;
constant one : std_logic_vector (n-1 downto 0) := "00000001";
z : in std_logic; begin
S : out std_logic; DUT: ripple_carry_adder generic map(n)
C : out std_logic); Port map (A_t,B_t,C0_t,S_t);
end component; process begin
signal C : std_logic_vector (n downto 0); A_t <= "00000000"; B_t <= "00000000";
C0_t <= '0';
begin
for i in 0 to n-1 loop
C(0) <= C0; wait for 4 ns; A_t <= A_t + one;
GEN_FA: for i in 0 to n-1 generate for j in 0 to n-1 loop
FA: full_adder Port map(A(i),B(i),C(i),S(i),C(i+1)); wait for 4 ns; B_t <= B_t + one;
end generate GEN_FA; end loop;
S(n) <= C(n); end loop;
end process;
end Gate_Level;
end Behavioral;
Simulation Results for the 4-bit Adder Entity
7
Check results with “assertions”
process
begin
A_t <= "00000000"; B_t <= "00000000"; C0_t <= '0';
for i in 0 to n-1 loop
wait for 4 ns; A_t <= A_t + one;
for j in 0 to n-1 loop
wait for 4 ns; B_t <= B_t + one;
assert (S_t = A_t + B_t) report "Error message" severity NOTE;
end loop;
end loop;
end process;
• Match data types for S_t, A_t, B_t
• Print “Error message” if assert condition FALSE
• (condition is not what we expected)
• Specify one of four severity levels:
• NOTE, WARNING, ERROR, FAILURE
• Simulator allows selection of severity level to halt simulation
• ERROR generally should stop simulation
• NOTE generally should not stop simulation
8
Test Bench with Text-IO
• Stimulus for DUT is read from an input file and modified in the source component
• The response modified is in the sink and written to the output file
Libraries, remember to declare the textio-library!
library IEEE;
use IEEE.std_logic_1164.all;
use std.textio.all;
use IEEE.std_logic_textio.all;
Arto Perttula, Tampere University of 9
Technology
Test Bench with Text-IO
• Create process and declare the input and process
output files (VHDL’87) FILE file_in : TEXT IS IN "datain.txt";
FILE file_in : TEXT IS IN "datain.txt"; FILE file_out : TEXT IS OUT "dataout.txt";
FILE file_out : TEXT IS OUT "dataout.txt"; VARIABLE line_in : LINE;
• File paths are relative to simulation VARIABLE line_out : LINE;
directory VARIABLE input_tmp : std_logic_vector(7 downto 0);
• Variables for one line of the input and output VARIABLE output_tmp : std_logic_vector(8 downto 0);
files begin
VARIABLE line_in : LINE; while not endfile(file_in) loop
VARIABLE line_out : LINE; readline(file_in, line_in);
• Value of variable is updated read(line_in, input_tmp);
immediately. Hence, the new value is A_t<= input_tmp;
visible on the same execution of the read(line_in, input_tmp);
process (already on the next line) B_t<= input_tmp;
• Variables for the value in one line wait for 4 ns;
VARIABLE input_tmp : INTEGER; write(line_out, S_t);
VARIABLE output_tmp : INTEGER; writeline(file_out,line_out);
writeline(OUTPUT,line_out);
end loop;
datain.txt dataout.txt wait;
00000000 00000000 000000000 end process;
00000000 00000001 000000001 end Behavioral;
00000000 00000010 000000010
00000000 00000011 000000011
00000000 00000100 000000100
Arto Perttula, Tampere University of
Technology 10
