.

Unit-I Computer architecture and organization, computer generations, von Neumann model,
CPU organization, CPU organization, Register organization, Various CPU register, Register
Transfer, Bus and Memory Transfers, Arithmetic, Logic and Shift micro-operations, Arithmetic
logic shift unit.

Unit–II The arithmetic and logic unit, Fixed-Point representation: integer representation,
signmagnitude, 1’s and 2’s complement and range, Integer arithmetic: negation, addition and
subtraction, multiplication, division, Floating-Point representation, Floating-Point arithmetic,
Hardwired micro-programmed control unit, Control memory, Micro-program sequence.

Unit–III Central Progressing Unit (CPU), Stack Organization, Memory Stack, Reverse Polish
Notation. Instruction Formats, Zero, One, Two, Three- Address Instructions, RISC Instructions
and CISC Characteristics, Addressing Modes, Modes of Transfer, Priority Interrupt, Daisy
Chaining, DMA, Input-Output Processor (IOP).

Unit–IV Computer memory system, Memory hierarchy, main memory: RAM, ROM chip,
auxiliary and associative memory, Cache memory: associative mapping, direct mapping,
setassociative mapping, write policy, cache performance, Virtual memory: address space,
memory space, address mapping, paging and segmentation, TLB, page fault, effective access
time, replacement algorithm.

Unit–V Parallel Processing, Pipelining General Consideration, Arithmetic Pipeline, and

Instruction Pipeline, Vector Operations, Matrix Multiplication, and Memory Interleaving,
Multiprocessors, Characteristics of Multiprocessors.

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Computer generations are periods marked by significant
advancements in technology, with each generation characterized by new
components, increased capabilities, and improved efficiency. Here's a brief
overview:
Generations of Computers:

First Generation (1940-1956): Used vacuum tubes, were large, power-hungry,

and unreliable.

Second Generation (1956-1963): Introduced transistors, leading to smaller,

faster, and more reliable computers.

Third Generation (1964-1971): Integrated circuits (ICs) enabled further

miniaturization, increased speed, and reduced costs.

Fourth Generation (1971-present): Microprocessors and VLSI technology led to

the development of personal computers and widespread computing.

Fifth Generation (1980s-present): Focus on Artificial Intelligence (AI) and parallel

processing.
The first computers had fixed programs and changing a computer program required
physically rewiring or redesigning the machine. This meant that re-repurposing an
computer was a difficult, expensive and time-consuming process.

The Mathematician John Von-Neuman designed the specification for the first
programmable computer in 1954, where the programs themselves could be stored in
memory, not just data.

Instructions are stored in memory and are retrieved and processed by the Central
Processing Unit one by one. This blueprint is known as the Von-Neumann Architecture.

The Von-Neuman Architecture is based on the principle of:

● Fetch an Instruction
● Decode the Instruction
● Execute the Instruction
The process above is repeated indefinitely, and is known as the fetch, decode, execute
cycle.

The job of the control unit is to coordinate and control all the other parts of the CPU. It
tells the registers & ALU what to do with an instruction that is passed to them.

The CU decodes the instructions retrieved from memory and instructs the ALU to
perform an arithmetic or logic instruction on the data from the decoded instruction.

Arithmetic Logic Unit

The job of the ALU is to perform the calculations or logic that the CU has decoded.

Common processes include:

● Addition
● Subtraction
● Division
● Multiplication
● Selection / Branching
● Repetition / looping.

Registers

The registers form part of the CPU Cache, temporarily storing data ready for processing
or send to the RAM.
PC – Program Control Register

The program control register stores the address of the current instruction. Once the
current instruction has been fetched and decoded, the program control register
changes to the address of the next instruction.

IR – Instruction Register

The instruction register contains the current instruction itself, retrieved from it’s stored
address.

MAR – Memory Address Register

The memory address register contains the memory location of either the next instruction
to be fetched or the location of where the results of the current process are to be stored.

MDR – Memory Data Register

The memory data register contains either the data retrieved from memory (either an
instruction or an operand) during the current fetch cycle at the address stipulated in the
MAR, or the data the is due to be written to memory.

ACC – Accumulator

The accumulator receives the results of the current process from the ALU and stores it
for the use in the next Fetch-Decode-Execute cycle.

IX – Index Register

This register is used when performing operations involving index addressing.

Buses

Buses are the physical wires along which data is passed, both within the CPU itself and
across the motherboard.
CPU Bus

The CPU bus is used to pass data around the CPU between the CU,ALU and registers.

Control Bus

The Control bus sends signals to the RAM, indicating whether to initiate a read or write
on the address received along the address bus

Address Bus

The address bus is the wire along which the address of the memory location in RAM
required for the read/write is sent.

Data Bus

The data bus is the wire along which the data is sent either to or from the RAM
(depending whether a read or write has been initiated.

Types of CPU Organizations

1. Single Accumulator Organization
2. General Register Organization
3. Stack organization
Single Accumulator Organization (Not Important)

● We are familiar with the general format of a register, which is utilized for
storing and manipulating data. A register typically consists of a mode, opcode,
and operand.
1. Mode: Specifies the address mode.
2. Opcode: Indicates the operation to be performed.
3. Data: Contains the actual data.
● This type of register is employed in computer architectures.
● Now, let's delve into the Single Accumulator Organization: Basic computers
often adopt the single accumulator organization, where the accumulator
serves as a dedicated register.
● Operations are executed within the Arithmetic Logic Unit (ALU), which resides
inside the Central Processing Unit (CPU). The CPU is directly linked to the
register, ensuring high-speed data transfer.
● The input data for the ALU is sourced from the accumulator register, and the
result of the ALU calculation is then stored back in the accumulator.
● Single Accumulator Organization is chosen when cost-effectiveness is a
priority. By minimizing the number of registers, we reduce the overall system
cost.
● Registers are the fastest form of memory, and connecting them directly to the
CPU ensures rapid data exchange, contributing to high system performance.
The more registers used, the higher the cost. To achieve cost-effectiveness, a
single accumulator register is employed.
● Definition of Single Accumulator Organization: In this architecture, a single
accumulator register is designated for arithmetic and logic operations. It
optimizes cost by limiting the number of registers, emphasizing efficiency in
simple computing systems.
General Architecture of Single Accumulator Organization

● In this architecture, we have a Program Counter (PC) responsible for storing

addresses, and it is connected to the memory. Additionally, there is an
Accumulator (AC) connected to the Arithmetic Logic Unit (ALU).
● The data stored in memory is retrieved and transferred to the Instruction
● Register (IR), from where it is moved to the Accumulator (AC) and
subsequently processed in the Arithmetic Logic Unit (ALU).
● The ALU and memory components are interconnected through a common
bus, facilitating the exchange of data between them.

This type of organization supports single-address instructions. As an example, consider

the instruction sequence for the operation C = A + B:
 ● LDA A: Load the content of memory location A into the Accumulator (AC).
● ADD B: Add the content of memory location B to the data in the Accumulator
(AC).
● Store C: Store the result in the Accumulator (AC) back to the memory location
designated for C.

General Register Organization

● To understand General Register Organization, it's essential to grasp the major

components within a CPU:
1. Storage Components: These include registers and flip-flops, serving as
temporary storage for data.
2. Execution Components: The Arithmetic Logic Unit (ALU) is responsible
for carrying out calculations and logical operations.
3. Transfer Components: The bus facilitates the transfer of data between
storage and execution components.
4. Control Component: The control unit oversees and directs the
functioning of other components within the CPU.
● Memory locations play a crucial role in storing various data types such as
pointers, counters, return addresses, temporary results, and partial products.
However, accessing memory is a time-consuming task. To enhance
efficiency, intermediate values are stored in processor registers. These
registers are interconnected through a common bus system, allowing
seamless communication not only for direct data transfer but also for
coordinating various microoperations.
● Definition of General Register Organization: In computing, General Register
Organization refers to the systematic arrangement and utilization of registers
within the CPU. These registers serve as high-speed, temporary storage for
 data and play a vital role in enhancing computational efficiency by minimizing
the need for frequent memory access.

A Bus Organization for Seven CPU Registers

● The depicted bus organization features seven CPU registers, and its
functionality is detailed as follows:
 ● The output of each register is linked to two multiplexers (MUX), both of which
play a crucial role in transferring register data into the Arithmetic Logic Unit
(ALU).
● Two buses, A and B, are utilized for data transfer. The selection lines in each
multiplexer determine whether to choose data from a register or from input
data. Data is transmitted to the ALU via buses A and B.
● The OPR (Operation) signal serves to define the type of operation to be
executed by the ALU.
● The result of the operation conducted by the ALU can be directed to other
units within the system or stored in any of the processor registers.
● A decoder is employed to select the register where the result will be stored.
The decoder activates one of the register load inputs, specifying the
destination register for storing the result.

Example, Let we want to perform the operation R1 ← R2 + R3

● To do this operation, Control Unit generates following singal (Control Word).

Control Word
 ● A control word, designed for the aforementioned CPU organization, consists
of four fields as illustrated below:

● The three bits of SEL A are dedicated to transferring the contents of a

register into BUS A.
● The three bits of SEL B are assigned to transferring the contents of a register
into BUS B.
● The three bits of SELD are utilized for selecting a destination register. This
facilitates the decision of whether to store the result in a register or to
transmit it outside the ALU.
● The five bits of OPR define the type of operation to be performed by the
ALU. This field governs the arithmetic or logical operation executed by the
ALU based on the specified opcode.

Code for for Register Selection

Operation Code for ALU

Stack Organization

● The memory of a CPU can be organized as a STACK, a structure where

information is stored in a Last-In-First-Out (LIFO) manner. This means that the
item last stored is the first to be removed or popped.
● To manage the items, a stack uses a stack pointer (SP) register. The stack
pointer stores the address of the last item in the stack, essentially pointing to
the topmost element. Stack operations involve two main actions:
1. Insertion (Push): When an item is added to the stack, it is referred to as
insertion or a push operation.
2. Deletion (Pop): When an item is removed from the stack, it is known as
deletion or a pop operation.
● There are two main types of stacks:
 1. Register Stack: Utilizes processor registers to create a stack structure,
enhancing speed and efficiency in certain operations.
2. Memory Stack: Involves using dedicated memory locations to
implement the stack structure.

Register Stack
 ● When processor registers are organized in a stack-like fashion, it is termed a
register stack. The diagram above illustrates a 64-word register stack.
● The stack pointer (SP) contains the address of the topmost element in the
stack.
● When the stack is empty, the EMPTY flag is set to 1, and when the stack is
full, the FULL flag is set to 1.
● The DR (Data Register) contains the data either being popped from or
pushed into the stack.
● Additional benefits of a register stack include faster access times and
reduced memory bus contention, making it suitable for certain computing
tasks requiring high-speed data manipulation.
● For example, in the figure, three items (A, B, and C) are placed in the stack,
with item C at the top. Thus, the stack pointer (SP) holds the address of C
(SP = 3).

PUSH Operation:

● When performing a PUSH operation to add an element (let's say E) to the

stack, the following steps are executed:
○ Step 1: Increment the Stack Pointer (SP) by 1 so that it points to an
empty slot.

SP ← SP + 1 [Increment stack pointer]

○ Step 2: Store the value of the Data Register (DR) at the address
pointed to by SP.

M[SP] ← DR [Write the item on top of the stack]

 ○ Step 3: Check boundary conditions.

If (SP = 0), then set FULL ← 1 indicating the stack is full.

EMPTY ← 0 signifies that the stack is not empty.

POP Operation:

● When performing a POP operation to remove an element from the stack, the
following steps are executed:
○ Step 1: Retrieve the data from the address stored in the Stack Pointer
(SP) and store it in the Data Register (DR).

DR ← M[SP] [Fetch item from the top of the stack]

○ Step 2: Decrement the Stack Pointer (SP) by 1.

SP → SP - 1

○ Step 3: Check boundary conditions.

if (SP = 0) then (EMPTY ← 1) [Check if the stack is

empty]

FULL ← 0 [Mark the stack as not full]

Memory Stack

● When primary memory (RAM) is organized in the form of a stack, it is

referred to as a Memory Stack.
 ● The Program Counter (PC) indicates the address of the next instruction in
the program.
● The Address Register (AR) points to an array of data within the memory
stack.
● The Stack Pointer (SP) identifies the top of the stack.
● In the illustrated figure, the initial value of SP is 4001, and the stack grows
with decreasing addresses. Consequently, the first item stored in the stack is
at address 4000, the second item at address 3999, and the last item at
address 3000.

PUSH Operation
SP → SP - 1

M[SP] ← DR

POP Operation

DR ← M[SP]

SP → SP + 1

● The PUSH operation involves decrementing the Stack Pointer (SP) to

allocate space for a new item and storing the value from the Data Register
(DR) at the address pointed to by the updated SP.
● The POP operation retrieves the item from the top of the stack by copying
the data from the address indicated by SP to DR. Subsequently, SP is
incremented to free up space in the stack.

Addressing Modes
An instruction format is a collection of bits that defines the type of instruction,
operands, and the type of operation. The instruction format is represented by a
rectangular box, and a basic instruction format includes the following fields: Opcode,
Mode, and Address.

● Opcode: Defines the type of operation to be performed, such as add, subtract,

complement, and shift.
● Address field: Defines the address of operands.
● Mode (or addressing mode) field: Defines the method by which operands are
fetched, modifying the address field of the instruction to determine the actual
address of the data.
Addressing Modes:

● 1. Implied Addressing Mode: The zero-address instruction and all instructions

using the accumulator are implied-mode instructions. For example, the
"complement accumulator" instruction is implied-mode because the operand is
in the accumulator.
● 2. Immediate Addressing Mode: In this mode, the operand is specified in the
instruction itself, having an operand field instead of an address field.

For example: ADD 10, 20.

● 3. Register Addressing Mode: Used when data is stored in processor registers,

and the address part of the instruction contains the address of the processor
register.

For example: SUB R1, R2.

● 4. Register Indirect Addressing Mode: The instruction has the address of a

processor register, which contains the address of the operand in memory.
● 5. Direct Address Mode: The instruction has the address of a memory cell where
the data is stored, and the effective address is the address stored in the
instruction.
● 6. Indirect Address Mode: The address field of the instruction has a memory
address where the data is stored.
● 7. Autoincrement or Autodecrement Address Mode: Used when fetching a series
of data, and the address part of the instruction gives the starting address,
which is incremented or decremented to fetch the next data from memory.
● 8. Relative Address Mode: The content of the program counter is added to the
address part of the instruction to obtain the effective address of data.
● 9. Indexed Addressing Mode: The content of an index register is added to the
address part of the instruction to obtain the effective address, useful for
accessing data arrays in memory.
 ● 10. Base Register Addressing Mode: Similar to indexed addressing mode, the
content of a base register is added to the address part of the instruction to
obtain the effective address.

Data Transfer Instructions

Data transfer and manipulation are fundamental aspects of computer architecture,
integral to the execution of instructions within a computing system.

● These instructions are typically categorized into three main types:

1. Data Transfer Instructions
2. Data Manipulation Instructions
3. Program Control Instructions

Data Transfer Instructions

Data transfer instructions facilitate the movement of data from one location to
another within the computer system. These instructions are essential for controlling
the flow of information, including:

● Data transfer between memory and processor registers

● Data transfer between processor registers and input or output devices
● Data transfer between different processor registers

The table below presents a list of eight common data transfer instructions widely
utilized across various computer architectures:
Data Manipulation Instructions

Data manipulation instructions play a critical role in performing operations on data

within a computer system. These instructions can be broadly categorized into three
types:

1. Arithmetic Instructions
2. Logical and Bit Manipulation Instructions
3. Shift Instructions

Arithmetic Instructions

Arithmetic instructions encompass fundamental operations such as addition,

subtraction, multiplication, and division. The table below provides a list of typical
arithmetic instructions:
Logical and Bit Manipulation Instructions

Logical instructions are designed to perform binary operations on data stored in

registers. These instructions consider each bit of the operand individually. Here are
some common logical and bit manipulation instructions:

Shift Instructions
Shift instructions move bits within a register either to the left or right. Logical shifts
insert 0 to the end bit position. The table below illustrates various types of shift
instructions:

Program Control Instructions

In a computer system, instructions are typically stored in successive memory

locations, and the execution of a program involves fetching instructions from these
consecutive memory locations. As each instruction is fetched, the program counter is
incremented to contain the address of the next instruction in sequence. Program
control instructions play a crucial role in directing the flow of a program and
managing the execution process.

General program control instructions encompass a variety of operations that dictate

the execution flow. Some of these instructions are outlined in the table below:
Parallel Processing
● In older computers, only a single instruction used to be executed at a time,
leading to the wastage of ALU time and an inability to fully utilize processing
capabilities. To address this inefficiency, the concept of parallel processing was
introduced.
● Parallel processing involves the simultaneous execution of multiple
instructions, allowing for concurrent data processing and faster execution
times. Instead of processing instructions sequentially, parallel processing
techniques enable more efficient use of computing resources. For example:
○ While an instruction is being executed in the ALU, the next instruction
can be read from memory.
○ A system may have two or more ALUs, capable of executing multiple
instructions simultaneously.
○ Multiple processors may operate concurrently, enhancing overall
system performance.
● The primary purpose of parallel processing is to accelerate computer
capabilities by leveraging increased hardware resources.
● Parallel processing can be examined at various levels of complexity:
○ At a lower level, the distinction between parallel and serial operations is
based on the type of registers used.
○ Shift registers operate in a serial fashion, processing one bit at a time,
while registers with parallel load operate with all bits of the word
simultaneously.
○ At a higher level of complexity, parallel processing can involve a
multiplicity of functional units performing identical or different operations
simultaneously.
The following diagram illustrates a processor with multiple functional units,
showcasing the additional components added to increase productivity and enable
parallel processing:

Parallel processing can be classified in various ways, one of which is introduced by

M.J. Flynn. Flynn's classification divides computers into four major groups based on
the sequence of instructions read from memory and the operations performed in the
instruction and data streams:

1. Single Instruction Stream, Single Data Stream (SISD): In SISD architecture, a

single instruction stream is executed on a single data stream. This is the
traditional von Neumann architecture where one instruction is processed at a
time.
2. Single Instruction Stream, Multiple Data Streams (SIMD): SIMD architecture
involves the processing of a single instruction simultaneously on multiple data
streams. This is commonly seen in vector processors, where the same
operation is applied to multiple data elements concurrently.
3. Multiple Instruction Streams, Single Data Stream (MISD): MISD architecture,
although rare in practice, involves multiple instruction streams operating on a
single data stream. This concept is not widely implemented due to its
complexity and limited applicability.
 4. Multiple Instruction Streams, Multiple Data Streams (MIMD): MIMD architecture
allows for the simultaneous execution of multiple instruction streams on
multiple data streams. This is a versatile and widely used parallel processing
architecture found in modern multi-core processors and parallel computing
systems.

Pipelining
● Pipelining involves dividing a process into several suboperations, with each
suboperation associated with a segment.
● The output of each segment is stored in a register, and this register information
is passed to the next segment, facilitating a continuous flow of data.
● Each segment operates independently, allowing for concurrent execution of all
segments in the pipeline.
● The term "pipelining" is derived from the sequential transfer of information from
one segment to another.

Example: Performing Ai * Bi + Ci; for i = 1 to 7.

Segment 1: R1 ← Ai, R2 ← Bi
Segment 2: R3 ⇆ R1 * R2, R4 ← Ci
Segment 3: R5 ← R3 + R4
Pipelining is an efficient technique that allows for the overlap of different stages of
instruction execution, thereby improving overall throughput. Each segment operates
concurrently, enabling the processor to handle multiple instructions simultaneously.
This approach significantly enhances the speed and efficiency of data processing in
modern computer architectures.
What is the General Register
Organization?
In General Register Organization, the CPU uses a set of general-purpose registers to

store data temporarily during program execution. These registers are small, high-speed

storage locations within the CPU. Unlike accumulator-based architectures, where data

is temporarily stored in a single accumulator, this organization uses multiple registers,

each capable of storing different types of data such as integers, floating-point numbers,

addresses, and control information.

The use of these general-purpose registers allows for faster data processing since

accessing data from registers is significantly faster than fetching it from memory.

Additionally, many CPU instructions are designed to operate directly on data stored in

registers, which further accelerates computation.

Features of General Register

Organization
Here are the features of the General Register Organization:

1. Registers
In the General Register Organization, the CPU contains several general-purpose

registers. These registers are essential for storing data that is actively being processed,

providing fast access compared to slower memory storage. This feature is fundamental
in optimizing performance, especially when dealing with frequently accessed variables

and intermediate results.

2. Operand Access
The CPU directly accesses operands from the registers, which eliminates the need to

access slower memory constantly. By using the registers, data retrieval and

manipulation become faster, which in turn speeds up program execution. The general-

purpose registers act as intermediate storage for operands used in arithmetic and

logical operations.

3. Data Processing
In this architecture, the CPU can perform arithmetic and logical operations directly on

data stored in registers, bypassing the need for intermediate memory transfers. This

approach reduces the time spent in data movement, improving overall execution speed.

4. Instruction Format
The instruction format in General Register Organization usually includes fields that

specify the operation to be performed and the operands (which are typically register

addresses). These instructions are designed to be compact, allowing efficient use of the

CPU’s available registers.

5. Context Switching
One critical feature of General Register Organization is its ability to support context

switching. When the CPU switches between processes, it saves the contents of its

general-purpose registers to memory and later restores them when the process is
resumed. This mechanism allows multiple processes to share the CPU while preserving

each process's state.

Types of General Register

Organization
There are two main types of General Register Organization in CPU design:

1. Register - Memory Reference

Architecture
In this type of organization, the CPU has a relatively smaller number of registers. One

operand must always be located in a register, while the second operand can either be in

a register or memory. This organization typically uses two-address instruction formats,

where one address refers to a register and the other may refer to either a register or a

memory location.

2. Register - Register Reference

Architecture
This organization utilizes a larger number of general-purpose registers and typically

employs three-address instruction formats. In this case, all operands involved in the

arithmetic or logical operation must be in the registers. The results of computations are

also stored in registers. This type of organization enhances performance by minimizing

memory access, as all operations are conducted between registers.

Advantages of General Register
Organization
Here are the advantages of General Register Organization:

● With registers, programs can be written to be more compact, resulting in reduced

program size.
● Compilers can optimize code more effectively when using registers, as they can
identify opportunities to reuse registers and reduce memory accesses.
● Registers provide a temporary storage location for data, allowing for fast access
to data.
● Using a large number of registers increases the efficiency of the CPU, as it
reduces the need for memory references, resulting in faster program execution.

Disadvantages of General Register

Organization
Here are the disadvantages of General Register Organization:

● It can speed up execution by reducing memory access, but it can be limiting in

terms of flexibility.
● The need for a larger set of general-purpose registers increases the overall
hardware cost of the CPU.
● A large number of registers are used, it’s essential to avoid unnecessary register
usage.
Real-World Applications of General
Register Organization
One of the real-world applications of systems that use General Register Organization

includes the IBM 360 and PDP-11 computer architectures. These systems are known

for their efficient use of registers and their ability to perform complex operations with

reduced demand on memory, making them highly effective for a range of computing

tasks.

Conclusion
In conclusion, general register organization is a powerful CPU design approach that

enhances performance by utilizing a set of general-purpose registers instead of relying

on a single accumulator. As, it plays a critical role in modern CPU designs, particularly

for systems that require high-speed data processing.

When we are using multiple general-purpose registers, instead of a single
accumulator register, in the CPU Organization then this type of organization
is known as General register-based CPU Organization. In this type of
organization, the computer uses two or three address fields in their
instruction format. Each address field may specify a general register or a
memory word. If many CPU registers are available for heavily used variables
and intermediate results, we can avoid memory references much of the time,
thus vastly increasing program execution speed, and reducing program size.
For example:
MULT R1, R2, R3

This is an instruction of an arithmetic multiplication written in assembly

language. It uses three address fields R1, R2, and R3. The meaning of this
instruction is:
R1 <-- R2 * R3

This instruction also can be written using only two address fields as:
MULT R1, R2

In this instruction, the destination register is the same as one of the source
registers. This means the operation
R1 <-- R1 * R2

The use of a large number of registers results in a short program with limited
instructions.
Some examples of General register-based CPU Organizations are IBM 360
and PDP- 11.

Features of a General Register based CPU organization:

Registers: In this organization, the CPU contains a set of registers, which are
small, high-speed memory locations used to store data that is being
processed by the CPU. The general-purpose registers can be used to store
any type of data, including integers, floating-point numbers, addresses, and
control information.
Operand access: The CPU accesses operands directly from the registers,
rather than having to load them from memory each time they are needed.
This can significantly improve performance, as register access is much faster
than memory access.
Data processing: The CPU can perform arithmetic and logical operations
directly on the data stored in the registers. This eliminates the need to
transfer data between the registers and memory, which can further improve
performance.
Instruction format: The instruction format used in a General Register based
CPU typically includes fields for specifying the operands and operation to be
performed. The operands are identified by register numbers, rather than
memory addresses.
Context switching: Context switching in a General Register based CPU
involves saving the contents of the registers to memory, and then restoring
them when the process resumes. This is necessary to allow multiple
processes to share the CPU.
The advantages of General register-based CPU organization –
● The efficiency of the CPU increases as large number of registers are

used in this organization.

● Less memory space is used to store the program since the

instructions are written in a compact way.

The disadvantages of General register based CPU organization –

● Care should be taken to avoid unnecessary usage of registers. Thus,

compilers need to be more intelligent in this aspect.

● Since a large number of registers are used, thus extra cost is

required in this organization.

General register CPU organization of two types:
1. Register-memory reference architecture (CPU with less register) –

In this organization Source 1 is always required in the register,

source 2 can be present either in the register or in memory. Here

two address instruction formats are compatible instruction formats.

2. Register-register reference architecture (CPU with more register) –

In this organization, ALU operations are performed only on

registered data. So operands are required in the register. After

manipulation, the result is also placed in a register. Here three

address instruction formats are the compatible instruction format.

Different Classes of CPU Registers

Last Updated : 01 Feb, 2025
CPU registers are high-speed memory units essential for efficient program

execution, enabling quick access to frequently used values involved in

processing. They play a crucial role in data manipulation, memory

addressing, and tracking processor status. While accessing instructions from

RAM is faster than from a hard drive, it’s still not quick enough for the CPU,

which is why registers are used to store and retrieve data faster. They work

in coordination with the CPU’s memory to optimize processing, with cache

memory being the next step in speed, though still slower than registers. Each

class of CPU registers, from general-purpose to status and control registers,

supports specific tasks to ensure smooth and rapid execution of operations.

Different Types Of CPU Registers

There are several types of registers available in the CPU for different

purposes let’s discuss each one by one:

● Accumulator : This is the most frequently used register used to

store data taken from memory. It is indifferent numbers in different

microprocessors.

● Memory Address Registers (MAR) : It holds the address of the

location to be accessed from memory. MAR and MDR (Memory Data

Register) together facilitate the communication of the CPU and the

main memory.

● Memory Data Registers (MDR) : It contains data to be written into

or to be read out from the addressed location.

● General Purpose Registers : These are numbered as R0, R1,

R2….Rn-1, and used to store temporary data during any ongoing

operation. Its content can be accessed by assembly programming.

Modern CPU architectures tend to use more GPR so that register-

to-register addressing can be used more, which is comparatively

faster than other addressing modes .

● Program Counter (PC) : Program Counter (PC) is used to keep the

track of the execution of the program. It contains the memory

address of the next instruction to be fetched. PC points to the

address of the next instruction to be fetched from the main memory

when the previous instruction has been successfully completed.

 Program Counter (PC) also functions to count the number of

instructions. The incrementation of PCs depends on the type of

architecture being used. If we are using a 32-bit architecture, the PC

gets incremented by 4 every time to fetch the next instruction.

● Instruction Register (IR): The IR holds the instruction which is just

about to be executed. The instruction from the PC is fetched and

stored in IR. As soon as the instruction is placed in IR, the CPU starts

executing the instruction, and the PC points to the next instruction

to be executed.

● Stack Pointer (SP): The stack PCs pointer points to the top of the

stack, which is a part of the memory used to store function calls and

other operations.

● Flag Register: A flag register , also known as a status register or

condition code register, is a special type of register in a computer’s

central processing unit (CPU) used to indicate the status of the CPU

or the outcome of various operations such as Zero Flag, Carry flag,

Sign Flag, Overflow Flag, Parity Flag, Auxiliary Carry Flag, and

Interrupt Enable Flag.

● Condition code register ( CCR ): Condition code registers contain

different flags that indicate the status of any operation. For instance,

let’s suppose an operation caused the creation of a negative result

or zero, then these flags are set high accordingly. and the flags are
 1. Carry C: Set to 1 if an add operation produces a carry or a subtract

operation produces a borrow; otherwise cleared to 0.

2. Overflow V: Useful only during operations on signed integers.

3. Zero Z: Set to 1 if the result is 0, otherwise cleared to 0.

4. Negate N: Meaningful only in signed number operations. Set to 1 if a

negative result is produced.

5. Extend X: Functions as a carry for multiple precision arithmetic

operations.

These are generally decided by ALU.

So, these are the different registers that are operating for a specific purpose.

Size of CPU Register

The number and size of the register in the CPU depend on the processor

design and can have an important impact on its performance and capabilities

on the CPU. Now, let’s discuss the different sizes of the register available in

the CPU:

● 8-bit registers: These can store 8 bits of data, which is the same as

1 byte. They are used for simple arithmetic and data manipulation.

● 16-bit registers: These hold 16 bits of data, or 2 bytes. These

registers are found in older processors or certain systems that need

16-bit operations.
 ● 32-bit registers: These can store 32 bits of data or 4 bytes. They

are common in many processors and can handle larger data sizes

and more complex calculations than 8-bit or 16-bit registers.

● 64-bit registers: These hold 64 bits of data, or 8 bytes. Modern

processors often use these, providing more computational power

and better memory-addressing capabilities.

Most modern computers use 32-bit or 64-bit registers, and that’s why we

call them 32-bit or 64-bit processors. This terminology refers to the width of

the processor’s registers and how much data it can handle at once.

In some specialized processors, you might see even larger registers like 128-

bit or 256-bit. These are used for specific tasks such as vector processing or

cryptography where dealing with large data sets and parallel processing is

important.

Purpose of Registers

Registers play a very important role in computers, and they are used by CPU

for various purposes.

● Storing Instruction: Registers are used to store the instruction from

programs before the CPU follows them. This helps the computer

quickly find and follow the steps it needs to take.

 ● Holding Answer: When the computer does math calculations or

other tasks, the register stores the temporary answer.

● Quick Access to Important Stuff: Registers are like the computer’s

quick-access shelves. They keep important things nearby, so the

computer can grab them fast without going far away to get them.

It’s like keeping your favorite tools on a shelf right next to you,

instead of in a faraway closet.

So, registers are like the computer’s quick-access memory, helping it work

faster and smarter.

What is Register Transfer?

Registers define the storage area that influences the data and instructions. It
can send data and instructions from one register to another register, memory to
register, and memory to memory, the register transfer approach is used. This
register is used in the transmission of data and instructions between memory
and processors to implement the particular tasks.

The data transfer from one register to another is named in representative

design using a replacement operator. The statement is

R2←R1
It indicates a transfer of the content of register R1 into register R2. It labelled a
replacement of the content of R2 by the content of R1. The content of the
source register R1 does not shift after the transfer.

A statement that specifies a register transfer involves that circuits are

accessible from the outputs of the source register to the inputs of the
destination register and that the destination register has a corresponding load
efficiency.

We need the transfer to appear only under a fixed control condition. This can be
displayed using an if-then statement.

If (P = 1) then (R2 ← R1)

where P is a control signal created in the control area. A control function is a

Boolean variable that is similar to 1 or 0. The control function is contained in the
statement as follows −

P: R2 ← R1

The control condition is terminated with a colon. It represents the specification

that the transfer operation is implemented by the hardware only if P = 1. Each
statement written in a register transfer notation indicates a hardware structure
for executing the transfer.

The diagram demonstrates the block diagram that shows the transfer from R1 to
R2. The n outputs of register R1 are linked to the n inputs of register R2. The
letter n can denote any number of bits for the register. It will be restored by an
actual number when the duration of the register is established.

Register R2 has a load input that is activated by the control variable P. It is

considered that the control variable is synchronized with the equivalent clock
like the one used to the register.

As displayed in the timing diagram, P is activated in the control area by the

increasing edge of a clock pulse at time t. The next positive transition of the
clock at time t + 1 discovers the load input active and the data inputs of R2 are
then loaded into the register in parallel. P can go back to 0 at time t + 1. The
transfer will appear with each clock pulse transition while P stays active.

The clock is not contained as a variable in the register transfer statements. It is

considered that all transfers appear during a clock edge transition. The control
condition including P becomes active only after time t, the actual transfer does
not appear until the register is triggered by the next positive transition of the
clock at time t + 1.

Bus and Memory Transfers

A digital system composed of many registers, and paths must be provided to
transfer information from one register to another. The number of wires
connecting all of the registers will be excessive if separate lines are used
between each register and all other registers in the system.

A bus structure, on the other hand, is more efficient for transferring information
between registers in a multi-register configuration system.

A bus consists of a set of common lines, one for each bit of register, through
which binary information is transferred one at a time. Control signals determine
which register is selected by the bus during a particular register transfer.

The following block diagram shows a Bus system for four registers. It is
constructed with the help of four 4 * 1 Multiplexers each having four data inputs
(0 through 3) and two selection inputs (S1 and S2).
We have used labels to make it more convenient for you to understand the input-
output configuration of a Bus system for four registers. For instance, output 1 of
register A is connected to input 0 of MUX1.

The two selection lines S1 and S2 are connected to the selection inputs of all
four multiplexers. The selection lines choose the four bits of one register and
transfer them into the four-line common bus.

When both of the select lines are at low logic, i.e. S1S0 = 00, the 0 data inputs of
all four multiplexers are selected and applied to the outputs that forms the bus.
This, in turn, causes the bus lines to receive the content of register A since the
outputs of this register are connected to the 0 data inputs of the multiplexers.
Similarly, when S1S0 = 01, register B is selected, and the bus lines will receive the
content provided by register B.

The following function table shows the register that is selected by the bus for
each of the four possible binary values of the Selection lines.

Note: The number of multiplexers needed to construct the bus is equal to the
number of bits in each register. The size of each multiplexer must be 'k * 1' since
it multiplexes 'k' data lines. For instance, a common bus for eight registers of 16
bits each requires 16 multiplexers, one for each line in the bus. Each multiplexer
must have eight data input lines and three selection lines to multiplex one
significant bit in the eight registers.

A bus system can also be constructed using three-state gates instead of

multiplexers.

The three state gates can be considered as a digital circuit that has three gates,
two of which are signals equivalent to logic 1 and 0 as in a conventional gate.
However, the third gate exhibits a high-impedance state.
The most commonly used three state gates in case of the bus system is a buffer
gate.

The graphical symbol of a three-state buffer gate can be represented as:

The following diagram demonstrates the construction of a bus system with

three-state buffers.
 ○ The outputs generated by the four buffers are connected to form a single bus
line.

○ Only one buffer can be in active state at a given point of time.

○ The control inputs to the buffers determine which of the four normal inputs will
communicate with the bus line.

○ A 2 * 4 decoder ensures that no more than one control input is active at any given
point of time.

Memory Transfer
Most of the standard notations used for specifying operations on memory
transfer are stated below.

○ The transfer of information from a memory unit to the user end is called a Read
operation.

○ The transfer of new information to be stored in the memory is called a Write

operation.

○ A memory word is designated by the letter M.

○ We must specify the address of memory word while writing the memory transfer
operations.

○ The address register is designated by AR and the data register by DR.

○ Thus, a read operation can be stated as:

Read: DR ← M [AR]

○ The Read statement causes a transfer of information into the data register (DR)
from the memory word (M) selected by the address register (AR).

○ And the corresponding write operation can be stated as:

Write: M [AR] ← R1
○ The Write statement causes a transfer of information from register R1 into the
memory word (M) selected by address register (AR).
Arithmetic Micro-operations
In general, the Arithmetic Micro-operations deals with the operations performed
on numeric data stored in the registers.

The basic Arithmetic Micro-operations are classified in the following categories:

1. Addition
2. Subtraction
3. Increment
4. Decrement
5. Shift

Some additional Arithmetic Micro-operations are classified as:

1. Add with carry

2. Subtract with borrow
3. Transfer/Load, etc.

The following table shows the symbolic representation of various Arithmetic

Micro-operations.

Symbolic Representation Description

R3 ← R1 + R2 The contents of R1 plus R2 are

transferred to R3.

R3 ← R1 - R2 The contents of R1 minus R2 are

transferred to R3.

R2 ← R2' Complement the contents of R2 (1's

complement)

R2 ← R2' + 1 2's complement the contents of R2

 (negate)

R3 ← R1 + R2' + 1 R1 plus the 2's complement of R2

(subtraction)

R1 ← R1 + 1 Increment the contents of R1 by one

R1 ← R1 - 1 Decrement the contents of R1 by one

Note: The increment and decrement micro-operations are symbolized by '+ 1'
and '? 1' respectively. Arithmetic operations like multiply and divide are not
included in the basic set of micro-operations.
omputers work mainly based on instructions. These are simple commands that tell the

system what to do, such as adding and subtracting or multiplying and dividing. Every

operation a computer performs starts with data stored in registers. But how does this

data get processed? That’s where micro-operations come in.

Micro operations are the smallest tasks the CPU performs, directly manipulating data in

registers. They handle everything from transferring data between registers to performing

calculations. In this blog, we look deeper into logic micro-operations, how they work,

their types, and why they are essential.

What are Logic Micro-Operations in

Computer Organisation?
Logic micro-operations involve binary operations performed on registers containing

strings of bits. Each bit within the register is treated individually and functions as an

independent binary variable. This bitwise approach allows for a total of 16 distinct logic

operations that can be performed:

Before going into the different logic micro-operations, it’s important to understand their

truth tables. The table below illustrates the truth table for all 16 logic micro-operations.
In the table, x and y represent the variables or registers where the data is stored. F0,

F1…., F15 denote the outputs produced after each logic micro-operation is applied.

Truth Table of 16 logic micro-operators

So, what does each logic micro-operation do? Let’s take a look:

1. Clear: This logic micro-operation sets all bits in the register to 0. Hence, it’s
effectively resetting the data. It’s used to initialize or erase the contents of a
register.
2. AND: The AND operation performs a bitwise AND between corresponding bits of
two registers. The output bit is 1 only if both input bits are 1. Otherwise, it is 0.
3. Transfer A: Transfer A copies the contents of register A directly to the output
without any changes.
4. Transfer B: The Transfer B operation copies the contents of register B directly to
the output without any changes.
5. Exclusive OR: The Exclusive OR (XOR) performs a bitwise comparison
between two registers. The output bit is 1 if the corresponding bits of the inputs
are different, and it is 0 if they are the same.
6. OR: The OR performs a bitwise OR between corresponding bits of two registers.
The output bit is 1 if at least one of the input bits is 1, otherwise it is 0.
 7. NOR: This operation performs a bitwise OR operation followed by negation. The
output bit is 1 only if both input bits are 0. Otherwise, the output is 0. It’s used to
invert the result of an OR operation.
8. Exclusive NOR: The Exclusive NOR operation performs a bitwise comparison
between two registers. It produces an output of 1 when the corresponding bits
are the same and 0 when they are different.
9. Complement B: Complement B inverts all the bits in register B. It changes 1s to
0s and 0s to 1s. This is for performing negation or generating the complement of
the data.
10. Complement A: The Complement A operation inverts all the bits in register A. It
changes 1s to 0s and 0s to 1s.
11. NAND: The NAND logic micro-operation performs a bitwise AND operation
between two registers and then negates the result. The output bit is 0 only if both
input bits are 1. Otherwise, the output is 1. It’s the inverse of the AND operation.

Set to all 1’s: operation sets all the bits in a register to 1. This is used to initialize a

register.

Implementing logic micro-operations in hardware involves using logic gates for each bit

or pair of bits in the registers to carry out the desired logic function. Although there are

16 possible logic micro-operations, most computers rely on just four: AND, OR, XOR

(Exclusive OR), and NOT.

Hardware Implementation
Logic Diagram of Hardware Implementation of Logic Circuit

The hardware implementation, as shown in the diagram, consists of a single stage that

generates the four basic logic micro-operations. It uses four logic gates and a

multiplexer. Each gate performs one of the required logic functions: AND, OR, XOR, or

NOT. Their outputs are fed into the multiplexer’s data inputs.

The multiplexer then uses two selection inputs, S1 and S0, to choose which data input

to pass to the output. This configuration represents one stage, and for a circuit handling

n bits, this setup would be replicated n times to accommodate all the bits.

Advantages of Logic Micro-

operations
● Low Power Consumption: Because they’re designed to be energy efficient,
logic micro operations can be used to build systems that consume less power.
 ● Scalable Processing: Logic micro-operations can easily scale to handle larger
datasets without slowing down. It has applications in systems that need to
manage increasing amounts of data over time.
● Simplified Computation: Logic microoperations break down complex tasks into
smaller components. That makes computations easier to manage and optimize.
● Fast Data Processing: Logic micro-operations are very fast. It allows systems to
handle huge volumes of data without lagging This makes them ideal for high-
performance computing, real-time data processing, and complex simulations.
● Versatility: Logic micro-operations are highly flexible. They can be combined in
countless ways to carry out different types of computations. They can do
everything from basic arithmetic operations to more complex algorithms and logic
functions.

Applications of Logic Micro-

operations
micro-operations play a key role in optimising memory usage in data storage and

compression algorithms.

1. Cryptography and Image Processing

In cryptography, logic micro-operations allow precise manipulation of individual bits for

secure data encryption and decryption. Similarly, in image processing, they are used to

control pixel-level operations.

2. Machine Learning
Logic micro-operations are used in machine learning algorithms to manipulate data and

make decisions based on patterns in the dataset. These operations are crucial for tasks

like image recognition, voice recognition, and natural language processing, where fast

and accurate data handling is needed.

3. Arithmetic Circuits

Logic micro-operations are fundamental in constructing arithmetic circuits, such as

adders and subtracters. They combine XOR, AND, and OR operations to perform key

arithmetic functions like addition and subtraction.

Conclusion
In conclusion, understanding logic micro-operations is crucial for anyone pursuing a

career in software engineering or related fields. These fundamental operations form the

backbone of data manipulation, optimization, and efficient system design. A solid grasp

of logic micro operations is important for technical expertise and also ensures your job-

ready with the fundamentals equipped to tackle real-world challenges.

Arithmetic Logic Shift Unit in Computer
Architecture
Arithmetic Logic Shift Unit (ALSU) is a member of the Arithmetic Logic

Unit (ALU) in a computer system. It is a digital circuit that performs logical,

arithmetic, and shift operations. Rather than having individual registers

calculating the micro operations directly, the computer deploys a number of

storage registers which is connected to a common operational unit known as

an arithmetic logic unit or ALU.

Now, to implement the micro operation, the contents of specified registers are
allocated in the inputs of the common Arithmetic Logic Unit. The Arithmetic
Logic Unit performs an operation that leads as a result and gets transferred to
a destination register. Arithmetic Logic Unit may be a combinatory circuit in
order that the complete register transfer operation from the supply registers
through the ALU and into the destination register is performed throughout one
clock pulse amount. Sometimes, the shift micro operations are performed in a
separate unit, but sometimes it is made as a part of full ALU.
 One stage of ALSU

We can combine and make one ALU with common selection variables by
adding arithmetic, logic, and shift circuits. We can see the, One stage of an
arithmetic logic shift unit in the diagram above. Some particular micro
operations are selected through the inputs S1 and S0.

4 x 1 multiplexer at the output chooses between associate arithmetic output

between Ei and a logic output in Hi. The data in the multiplexer are selected
through inputs S3 and S2 and the other two data inputs to the multiplexer
obtain the inputs Ai – 1 for the shr operation and Ai + 1 for the shl operation.
Note: The output carry Ci + 1 of a specified arithmetic stage must be attached
to the input carry Ci of the next stage in the sequence.

The circuit whose one stage is given in the below diagram provides 8
arithmetic operations, 4 logic operations, and 2 shift operations, and Each
operation is selected by the 5 variables S3, S2, S1, S0, and Cin.

The below table shows the 14 operations perform by the Arithmetic Logic Unit:

1. The first 8 are arithmetic operations which are selected by S3 S2 =

00
2. The next 4 are logic operations which are selected by S3 S2 = 01
3. The last two are shift operations which are selected by S3 S2 = 10 &
11

Function table of ALSU

Basic Structure of Computer: Structure of Desktop Computers, CPU: General Register
Organization-Memory Register, Instruction Register, Control Word, Stack Organization,
Instruction Format, ALU, I/O System, bus,CPU and Memory Program Counter, Bus Structure,
Register Transfer Language-, addressing modes. Control Unit Organization: Basic Concept of
Instruction, Instruction Types, Micro Instruction Formats, Fetch and Execution cycle, Hardwired
control unit, Microprogrammed Control unit microprogram sequencer Control Memory,
Sequencing and Execution of Micro Instruction.