Part I.
1. Multilayered structure.
Typically refers to the organization of computer systems into layers that abstract
different functionalities. This can allow for better management of complexity,
separation of concerns, and modular design. Commonly identified layers include the
hardware layer, operating system layer, and application layer, each providing services
to the layers above it while relying on the services from the layers below it.
2. Computer architecture
Computer architecture refers to the design, structure, and organization of a computer’s
hardware components and the way they interact to execute instructions. It
encompasses both the physical elements, such as processors and memory, and the way
software interacts with hardware. Key aspects include instruction set architecture
(ISA), microarchitecture, and system design.
3. Storage Program Computer
A Von Neumann architecture computer. It is basically instruction-driven. Programs
are pre-stored in the computer memory, and once the machine is started, it can
execute these programs in the logical order specified by the program, automatically
completing the processing work described by the program.
4. Amdahl’s law
When a component of a system is improved, the improvement in overall system
performance that can be obtained is limited by the percentage of the total execution
time of that component.
5. Locality pinciple of program access
The memory addresses accessed during program execution are not randomly
distributed, but are relatively clustered including temporal and spatial locality.
6. RISC
Reduced Instruction Set Computer (RISC) is a CPU design strategy that uses a small,
highly-optimized set of instructions, rather than a more specialized set of instructions
often found in other types of architectures. The main philosophy behind RISC is to
simplify the processor design, which leads to a high performance, low power
consumption, and small chip size.
7. Dynamic pipeline
Refer to a technique used in modern CPUs to improve instruction throughput by
allowing multiple instructions to be processed at different stages simultaneously.
8. Data correlation
Typically refers to the relationship between different system components or their
performance metrics, which can help in optimizing system design and operation.
9. Superscalar
Superscalar architecture refers to a type of microprocessor design that allows multiple
instruction pipelines to execute more than one instruction during a single clock cycle.
10. Super pipeline
Break pipeline stages into smaller stages to reduce clock period and increase
instruction throughput.
Part II.
1. A computer with main frequency of 400 MHz executes a standard test program.
The type of instructions, the number of executions and the average number of clock
cycles in the program are given as follows:
Instruction type Number of instructions executed Average Clock Cycle Number
Integer 45000 1
Data transfer 75000 2
Floating point arithmetic 8000 4
Branch operating 1500 2
Calculate the effective CPI, MIPS and program execution time of the computer.
2. There are three parts in the computer system that can be improved. The acceleration
ratio of the three parts is: Component acceleration ratio 1=30; Component
acceleration ratio 2=20; Component acceleration ratio 3=10.
a. If the proportion of part 1 and 2 can be improved is 30%, then what the proportion
of part 3 can be improved when the system acceleration ration can reach 10?
b. If the three parts can be improved at 30%, 30% and 20% respectively, and the three
parts can be improved at the same time, what is the proportion of the execution time
of the non-acceleratedpart in the total execution time of the system?
3. A single-function pipeline consists of four functional segments. The delay time of
each functional segment is equal to ∆t. The first five tasks, it requires that one ∆t will
paused after each taks is input, and then the next task is input. When fiv tasks are
input, two ∆t are paused, then repeat. Calculate the actual Throuhput, Acceleration
ratio and Efficiency of the pipeline.
4. There is a dynamic multi-function pipeline consisting of 5 segments, 1, 2, 3, 4, 5
for addition, 1, 2, 5 for multiplication. The delay time of the fourth paragraph is ∆t,
and that of the other sections is ∆t. The output of the pipeline can be directly returned
to the input or temporarily stored in the corresponding pipeline register. If the
4
following formula is calculated on the pipeline: ∑ ( A i x B i )
i=1
Calculate the Troughput, Acceleration Ratio and Efficiency of the pipeline.
Addition
Multiplication
5. Assume there is a two-level Cache system: the first level Cache is L1, and
thesecond level Cache is L2.
a. Assume that in 1000 accesses, L1 misses 40 times and L2 misses 20 times
Calculate all kinds of local and global miss rates.
b. Assume that the hit time of L2 is 10 clock cycles, the Miss cost of L2 is 100clock
cycles, and the hit time of L1 is one clock cycle, with an average of 1.5 accesses per
instruction, regardless of the impact of write operations. Question: What is the
average access time? What is the uverage pause time of each instruction?
