Measurement: Sensors 38 (2025) 101418

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Measurement: Sensors
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Digital to analog converter based on pulse-width adding

A R T I C L E I N F O A B S T R A C T

Keywords: This paper presents a digital-to-analog converter (DAC) based on the pulse width created naturally by the binary
Digital-to-analog converter counting sequence. The concept involves combining the counting impulses of the bits to form a pulse-width
DAC modulated signal, where the mean voltage is proportional to the input digital code. We propose a circuit
Pulse width
capable of achieving this using general-purpose components. Although our design targets 8 bits, it is scalable for
PWM
any number of nibbles.
The paper details simulations conducted to verify the proper functioning of the circuit and to evaluate its per-
formance. Tests were performed to determine the static characteristics of the converter, measure its differential
nonlinearity (DNL), and observe its step response.
In static terms, the converter exhibited negligible gain and offset errors, with a DNL below 1 LSB (least significant
bit). The converter operated correctly without any missing codes.
In dynamic terms, the converter demonstrated a bandwidth of 10 kHz and behaved like a second-order low-pass
filter with critical damping.

1. Introduction a total current proportional to the input digital code:

VREF VREF VREF
A digital-to-analog converter (DAC) is a circuit that transforms a I= × an− 1 + × an− 2 + … + n × ao ⇔
2R 4R 2 R
digital code (a set of n bits) into an analog quantity, usually an electrical
voltage. DAC circuits are used in various applications, including analog- IREF ( n− 1 )
to-digital conversion, digitally controlled signal generators, and auto- I= × 2 an− 1 + 2n− 2 an− 2 + … + 20 a0 ⇔
2n
matic control systems, among others [1–4]. Fig. 1 shows the DAC’s
electrical symbol, including supply voltages (VDD and VSS ) and the IREF
I= ×D (1)
reference voltage input (VREF ), which serves as a reference for the con- 2n
verter’s operation. where IREF = VREF
R is the current supplied by the reference voltage, and D

The two most common architectures for DACs are the R-2R ladder is the decimal value of the input digital code. Finally, the current is
network and the delta-sigma (ΔΣ) structure. The following paragraphs converted to a voltage by the operational amplifier, resulting io an
review these architectures to better contextualize our work. output voltage given by:
VREF
VO = − R × I = − ×D (2)
2n
1.1. R-2R resistor ladder network

The R-2R ladder network is probably the most popular structure for 1.2. Delta-sigma (ΔΣ) structure
DACs [5,6]. Fig. 2 presents the overall view of the R-2R network, and
Fig. 3 shows the details of a single node. The delta-sigma (ΔΣ) structure [7–9] has gained popularity in recent
Each node in the R-2R network sees to its right an equivalent resis- years. It employs oversampling techniques to achieve high resolution,
tance whose value is always 2R. Therefore, the current that reaches the albeit at the expense of increased latency and reduced bandwidth.
node is divided in half, with one half going down to the electronic Fig. 4 shows the working diagram of a delta-sigma (ΔΣ) DA con-
switch, and the other half continuing downstream where it will be verter. The input is a digital code (represented by the thickest line), and
divided in half again. The bits of the input digital code control the the output is an analog voltage. For explanatory purposes, we will as-
switches so that each bit contributes twice the current of the previous sume a signed representation is subtracted from a full-scale positive or
bit, from the most significant bit (MSB) on the left to the least significant negative number using the same number of bits. For example, an 8-bit
bit (LSB) on the right. The currents from all bits are summed to produce incoming digital code, ranging from − 128 to +127 as a signed

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Available online 22 December 2024

V. Viegas and J.M.D. Pereira Measurement: Sensors 38 (2025) 101418

The main contribution of this paper is the proposal of a new type of

DA converter that leverages the pulse width created naturally by the
binary counting sequence. Our approach is likely closer to the ΔΣ
structure, as it does not require a reference voltage and takes several
clock cycles to complete a conversion. Additionally, it is simpler to
understand and easier to implement, making it a valuable contribution
to the state of the art.
The paper is organized as follows: Section 2 presents the new DA
circuit and explains its operation. Section 3 describes the experimental
tests conducted to validate our prototype and discusses the results ob-
tained. Finally, Section 4 summarizes the main conclusions of the work.

2. Methods and procedures

Fig. 1. Electrical symbol of a DAC.
The proposed circuit, shown in Fig. 5, takes advantage of the pulse
width created naturally by the binary counting sequence. The circuit is
based on nibbles because it uses a 4-bit binary counter (4516).
If we examine the binary counting sequence shown in Fig. 6, we
observe that the width of the pulses varies according to the bit’s weight.
In general, all bits have a pulse width of 50 %, but this value is achieved
through narrower pulses for the least significant bits and wider pulses
for the more significant bits. The idea is to filter the first pulse of each bit
(only the first occurrence) and combine them into a single signal. The
result will be a binary-weighted pulse that can be used for digital-to-
Fig. 2. R-2R ladder network. analog conversion.
The filtering can be made by a simple logical circuit. For example,
the narrower the pulse, corresponding to the LSB, will be filtered if the
corresponding input bit (A0 ) is true AND the output of the binary
counter is Q3 Q2 Q1 Q0 = 0001. This leads to the logical circuit shown in
Fig. 7a, where the signal X0 pulses with a width of Tclk if A0 = 1 (where
Tclk is the clock period of the binary counter).
The same applies for the remaining bits:

• The 2Tclk pulse is filtered if the corresponding input bit (A1 ) is true
AND the output of the binary counter is Q3 Q2 Q1 Q0 = 001X, leading
to the circuit shown in Fig. 7b.
• The 4Tclk pulse is filtered if A2 is true AND the output of the binary
counter is Q3 Q2 Q1 Q0 = 01XX, leading to the circuit shown in Fig. 7c.
Fig. 3. Detail of single node of the R-2R ladder network. • The 8Tclk pulse is filtered if A3 is true AND the output of the binary
counter is Q3 Q2 Q1 Q0 = 1XXX, leading to the circuit shown in
Fig. 7d.

In the end, we combine all the filtered pulses with a OR gate, leading
to the output line PWM shown in Fig. 7e. After some optimizations to
reduce the number of gates, we arrive at the circuit shown in Fig. 8. This
circuit is contained within the block labelled “Pulse Filter” in Fig. 5.
For an 8-bit converter, we need to combine the outputs of two pulse
filters, one for each nibble. This is achieved through the summing stage
U3, which assigns a unitary weight to the most significant nibble and a
weight of 1/16 to the least significant nibble. Additionally, the stage
incorporates a first-order low-pass filter with a cutoff frequency of 2πR12 C2
Fig. 4. ΔΣ DAC. Hz, used to extract the average voltage from the pulses. A final stage
(U4) can be used to apply further filtering and get a positive output
voltage.
integer, would be subtracted from either − 128 or +127, depending on The pulse filters take 16 clock periods to complete their work. With a
the state of the feedback. clock frequency of 4 MHz on the main counter, they generate 250 kHz
The difference is applied to the input of an accumulator (the z− 1 signals, which are filtered by R2 C2 and R5 C3 (10 kHz cutoff frequency)
block). If the difference is a positive, the output of the accumulator resulting in a smoothed analog voltage at the output. It should be
ramps up; if the difference is a negative, the output of the accumulator emphasized that the pulse filters work in parallel, not sacrificing
ramps down. The MSB block selects the most significant bit of the word excessively the speed of operation of the circuit. The pair R1 C1 generates
(the sign bit) and toggles the feedback state (and the output) whenever a brief pulse that resets the counter at power-up.
the accumulator causes the sign to change. This results in a pulse-
density-modulated (PDM) output waveform, whose mean value is pro-
portional to the input digital code. Averaging can be achieved with a 2.1. Example of operation
simple low-pass filter.
Let’s examine how the circuit functions by considering an example.

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V. Viegas and J.M.D. Pereira Measurement: Sensors 38 (2025) 101418

Fig. 5. 8-bit DAC based on pulse-width adding. The input digital word is S7 − S0, with S7 being the most significant bit (MSB) and S0 the least significant bit (LSB).
The analog output is taken at the output of U4.

Fig. 6. Output of the binary counter. The width of the pulses increases as a
power of 2.

Suppose the circuit in Fig. 5 receives the input digital code 0100 0010.
The switches S6 (MSB) and S1 will be connected to VDD , while all the
other switches will be grounded. The pulse filter SC2 will process the
nibble A3 A2 A1 A0 = 0100, and the pulse filter SC1 will process the
nibble A3 A2 A1 A0 = 0010.
Inside the pulse filter SC2, the signals X3, X1 and X0 will remain low
because A3 = A1 = A0 = 0. However, the signal X2 will pulse high
when Q3 = 0 and Q2 = 1; in other words, it will contain the first hight
pulse of Q2 (only the first occurrence). Consequently, the output (PWM
line) will be square wave with a pulse-width equal to 4Tclk and a mean
voltage equal to 14 × VDD .
The same explanation applies to the pulse filter SC1, but in this case, Fig. 7. Pulse filtering from the LSB (X0 ) to the MSB (X3 ) followed by adding
only the first high pulse of Q1 passes to the output. The result will be (OR gate).

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V. Viegas and J.M.D. Pereira Measurement: Sensors 38 (2025) 101418

Table 1
Key values of the static characteristic.
Input binary combination Mean output voltage (mV) RMS output voltage (mV)

0000 0000 0 0
0000 0001 19.531 0.054
0000 0010 39.062 0.096
0000 0100 78.123 0.155
0000 1000 156.246 0.218
0001 0000 312.494 0.869
0010 0000 624.987 1.538
0100 0000 1250 2.484
1000 0000 2500 3.493
1111 1111 4980 0.835

Fig. 8. Pulse filter sub-circuit.

square wave with a pulse-width equal to 2Tclk and a mean voltage equal
to 18 × VDD .
The U3 stage sums the mean voltage of both pulse filters, giving a
weight 1/16 to the least significant nibble. The final output will be an
( ) ( )
analog voltage equal to 14 × VDD + 16 1
× 18 × VDD , which leads to
1289 mV assuming VDD = 5 V.

3. Results and discussion

This section describes the simulations carried out to verify the proper Fig. 9. Static characteristic.
functioning of the circuit and evaluate its performance. The simulations
were done using NI Multisim v14.3 running on a computer characterized
by Intel(R) Core(TM) i7-8550U CPU @ 1.80GHz, 16 GB RAM, and
Windows 11 Home 64 bits. The simulations included the following tests:

• Static characteristic (output voltage versus input digital code in

steady state).
• Differential nonlinearity (DNL).
• Step response.

Each of these tests will be explained in more detail in a dedicated

section.

3.1. Static characteristic

The static characteristic of the DA converter was obtained by

Fig. 10. Noise figure.
applying all the binary combinations at the input and recording the
corresponding voltages at the output, once they had stabilized.
Table 1 shows the mean output voltages obtained for several input the maximum value of noise is 3.5 mV RMS, which is much smaller that
binary combinations (all zeros, all ones, and powers of 2). Fig. 9 shows the LSB.
the plot of the static characteristic, with the horizontal axis representing
the input digital code (integer value) and the vertical axis representing 3.2. Differential nonlinearity (DNL)
the mean output voltage. The characteristic is well adapted (R = 1) by a
straight line with slope equal to 19.531 mV/LSB and an offset equal to The DNL measures the difference between the measured and the
84.2 μV. Looking at these values, we see that the slope matches the ideal output voltages for successive digital codes [10]:
theoretical value (5/256) and that the offset error is negligible (0.0043
LSB). Vout (i + 1) − Vout (i)
DNL(i) = − 1 (3)
We also measured the RMS value of the output voltage to have an Ideal LSB
idea of the noise generated by the circuit (see the last column of Table 1 The DNL thus defined is expressed as a fraction of the LSB, but it can
and Fig. 10). also be expressed as a voltage or a percentage of full scale.
The noise level at the output is related to the number of edges of the In the present case, our converter’s DNL was obtained from the
PWM signals. For low values of the digital code, the PWM signal of the values of the static characteristic (considering mean output voltages in
most significant nibble rests at 0 V most of the time. Conversely, for high steady state). The result, shown in Fig. 11, uses the definition of equation
values of the digital code, it rests at 5 V most of the time. For interme- (3).
diate values, it oscillates between 0 and 5 V thus generating more noise. We observe that the DNL is well below 1 LSB, meaning that the
This explains the hump observed in Fig. 10. It is important to note that converter has no missing codes.

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V. Viegas and J.M.D. Pereira Measurement: Sensors 38 (2025) 101418

If we look again to the circuit of Fig. 12, we see that the main clock
frequency (4 MHz) is successively divided 2, 4, 8 and 16 by the binary
counter, reaching a minimum value of 250 kHz. In other words, the
PWM signals have frequencies of 250 kHz and above. By designing the
second-order low-pass filter with a cutoff frequency of 10 kHz, two or-
ders of magnitude lower, we ensure that the output voltage is smoothed
sufficiently to not compromise the performance of the converter, as
confirmed by the simulations. If we want to increase the bandwidth of
the converter, we will need to increase the frequency of the main clock
proportionally.

4. Conclusions

The paper presented a DA converter that leverages the pulse width

naturally created by the binary counting sequence. The core idea is to
Fig. 11. DNL. combine the counting pulses of the bits to form a pulse-width-modulated
signal, whose mean voltage is proportional to the input digital code. We
introduced a circuit capable of performing this task using general-
purpose components. While the circuit was designed for 8 bits, it is
scalable to accommodate any number of nibbles. However, it is impor-
tant to note that increasing the number of nibbles will result in longer
processing times and reduced bandwidth.
The converter was tested to ensure proper functionality and to
evaluate its performance. Tests were conducted to determine the static
characteristics of the converter and to measure its step response.
In static terms, the converter was characterized by negligible gain
and offset errors, and a DNL below 1 LSB. The converter worked prop-
erly without missing codes.
In dynamic terms, the converter was characterized by a bandwidth of
10 kHz, and a behaviour of a second-order low-pass filter with critical
damping. The dynamic behaviour of the circuit is mostly determined by
Fig. 12. Step response. the active filters at the output.
In the future, we intend to work at a lower level by implementing the
digital part of the circuit using MOSFET transistors to save hardware and
increase velocity. We are also thinking in replacing the analog part (the
3.3. Step response
two active filters) by a purely digital output based on pulse width.

The step response is a valuable method for identifying the dynamic

characteristics of a system [11]. Following this approach, we applied a Acknowledgments
sharp change to the input, shifting from code 0000 0000 to code 1000
0000, and recorded the output voltage over time. The result is shown in This research did not receive any specific grant from funding
Fig. 12. agencies in the public, commercial, or not-for-profit sectors.
We observe that the dynamics of the converter are dominated by the
second-order low-pass filter formed by U3 and U4. The converter ex-
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Corresponding author. CINAV – Centro de Investigação Naval, Escola
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Vítor Viegasa,c,*, J.M. Dias Pereirab,c E-mail addresses: [email protected] (V. Viegas),
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CINAV – Centro de Investigação Naval, Escola Naval, Almada, Portugal [email protected] (J.M.D. Pereira).

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