Memory Organization & 8085 Assembly Language

Programming
Part 1: Memory Organization

Memory organization deals with how computer memory is structured, accessed, and managed
to store and retrieve data and instructions efficiently.

1. Serial Access Memory

Serial access memory is a type of memory where data is accessed sequentially, one after
another, starting from the beginning. To access a particular piece of data, all preceding data
must be read or skipped.

● Characteristics:
o Sequential Access: Data items are accessed in a specific linear order.
o High Latency for Random Access: Accessing data at the end of the sequence
takes much longer than accessing data at the beginning.
o Cost-Effective for Large Storage: Historically used for large, low-cost
storage where speed was not the primary concern.
● Examples:
o Magnetic Tapes: Oldest form, still used for archival storage. Data is stored
linearly on the tape.
o Magnetic Disks (HDDs): While offering "direct" access to sectors, accessing
data within a sector is serial, and the entire track must be read as the disk spins
under the read/write head.
o Shift Registers: Digital circuits where data bits are shifted in and out serially.

Conceptual Diagram: Magnetic Tape Access

+----------------------------------+
| |
| [Data 1] [Data 2] [Data 3] ... [Data N]
| |
+----------------------------------+
^ ^
| |
Read/Write Head (Moves sequentially)

To access Data N, the head must pass over Data 1 through Data N-1.

2. Random Access Memories (RAM)

Random Access Memory (RAM) allows data to be accessed directly and in any random
order, irrespective of its physical location. This means that the time taken to access any
specific byte or word of data is constant, regardless of where it is stored in the memory.

● Characteristics:
o Direct Access: Any memory location can be accessed directly using its unique
address.
 Volatile: Data is lost when the power supply is turned off.
o
Read/Write Capability: Data can be both read from and written to RAM.
o
High Speed: Faster than serial access memories for general-purpose
o
computing.
● Types of RAM:
o SRAM (Static RAM):
▪ Uses latches (typically 6 transistors per bit) to store data.
▪ Does not need to be refreshed periodically.
▪ Faster, more expensive, and consumes more power than DRAM.
▪ Used for cache memory (CPU cache).
o DRAM (Dynamic RAM):
▪ Uses capacitors and transistors to store data (1 capacitor + 1 transistor
per bit).
▪ Needs to be refreshed periodically (to replenish charge in capacitors,
preventing data loss).
▪ Slower, less expensive, and consumes less power than SRAM.
▪ Used for main memory (system RAM).

Conceptual Diagram: RAM Addressing

Address Bus (e.g., 16 bits for 64KB)

|
V
+---------------------------------+
| Memory Decoder |
| (Translates address to |
| select a specific row/column) |
+---------------------------------+
|
V
+---------------------------------+
| |
| Memory Array |
| (Grid of storage cells, each |
| with a unique address) |
| |
| [0x0000] [0x0001] [0x0002]... |
| [0x0010] [0x0011] [0x0012]... |
| ... |
| [0xFFFF] |
| |
+---------------------------------+
^
| Data Bus (e.g., 8 bits)
V
Data (Read/Write)

3. Read Only Memories (ROM)

Read-Only Memory (ROM) is a type of non-volatile memory from which data can be read,
but not easily, or not at all, written to. The data stored in ROM is permanent and remains
even when the power is off.

● Characteristics:
 Non-Volatile: Data persists even without power.
o
Read-Only (mostly): Primarily designed for reading, writing is difficult or
o
impossible after manufacturing.
o Used for Firmware: Stores bootstrap loaders (BIOS/UEFI), firmware for
embedded systems, lookup tables, etc.
● Types of ROM:
o PROM (Programmable ROM): Blank when manufactured, can be
programmed once by the user using a special device (PROM programmer).
o EPROM (Erasable Programmable ROM): Can be erased by exposing it to
strong UV light, then reprogrammed.
o EEPROM (Electrically Erasable Programmable ROM): Can be erased and
reprogrammed electrically, byte by byte. Slower write/erase times than Flash.
o Flash Memory: A type of EEPROM that can be erased and reprogrammed in
blocks rather than individual bytes. Widely used in USB drives, SSDs, and
camera memory cards.

Conceptual Diagram: ROM Usage

CPU
| (Address Bus)
V
+---------------------+
| ROM Decoder |
+---------------------+
|
V
+---------------------+
| ROM Chip |
| (Stores BIOS/Firmware)|
| (Pre-programmed data)|
+---------------------+
^
| (Data Bus - Read Only)
|
Instruction/Data Read

4. Virtual Memory

Virtual memory is a memory management technique used by operating systems (OS) to

provide an application with an illusion of a contiguous, large memory space, even if the
physical memory (RAM) is fragmented or smaller than required.

● How it Works:
o Page/Segment Swapping: The OS divides the virtual memory space into
fixed-size blocks called pages (or variable-size blocks called segments).
o Page Table: A data structure maintained by the OS that maps virtual
addresses to physical addresses.
o Swapping: When a required page is not in physical RAM, it's retrieved from a
secondary storage device (like an HDD/SSD, often called swap space or page
file). An existing page in RAM might be moved to swap space to make room.
This process is called paging or swapping.
 oMemory Management Unit (MMU): A hardware component (often part of
the CPU) that translates virtual addresses generated by the CPU into physical
addresses.
● Advantages:
o Allows programs to be larger than physical memory.
o Enables multitasking (multiple programs sharing limited RAM).
o Provides memory protection (isolates processes from each other).
o Simplifies memory management for programmers.
● Disadvantages:
o Performance Overhead: Swapping to disk is significantly slower than RAM
access, leading to "thrashing" if too much swapping occurs.
o Requires complex hardware (MMU) and OS support.

Conceptual Diagram: Virtual Memory System

+---------------------+ +---------------------+
+---------------------+
| | | | |
|
| Virtual Addresses | --> | MMU (Page Table) | --> | Physical
Addresses |
| (CPU generates) | | | | (in RAM)
|
+---------------------+ +---------------------+
+---------------------+
| ^ |
| (If page not in RAM) | V
V |
+------------------+
+---------------------+ | | Physical RAM
|
| Hard Disk / SSD |<----------------+------------------| (Main
Memory) |
| (Swap Space/ |
+------------------+
| Page File) |
+---------------------+

5. Cache Memory

Cache memory is a small, high-speed type of SRAM located closer to the CPU than main
memory (DRAM). Its purpose is to store frequently accessed data and instructions, reducing
the average memory access time and improving CPU performance.

● Principle: Based on the principle of locality of reference:

o Temporal Locality: If a data item is accessed, it's likely to be accessed again
soon.
o Spatial Locality: If a data item is accessed, nearby data items are also likely
to be accessed soon.
● Levels of Cache: Modern CPUs typically have multiple levels of cache:
o L1 Cache (Level 1): Smallest, fastest, located directly on the CPU die, often
split into instruction cache (L1i) and data cache (L1d).
o L2 Cache (Level 2): Larger and slightly slower than L1, also on the CPU die.
 oL3 Cache (Level 3): Largest and slowest of the caches, often shared among
multiple CPU cores.
● Cache Hit/Miss:
o Cache Hit: When the CPU requests data, and it's found in the cache. Fast
access.
o Cache Miss: When the CPU requests data, and it's not in the cache. The data
must then be fetched from a slower memory level (e.g., L2, L3, or main
memory) and brought into the cache.

Conceptual Diagram: Memory Hierarchy with Cache

+------------------+
| CPU Cores |
+------------------+
|
V (Very Fast Access)
+------------------+
| L1 Cache | (Smallest, Fastest SRAM)
+------------------+
|
V (Fast Access)
+------------------+
| L2 Cache | (Larger, Slower SRAM)
+------------------+
|
V (Slower Access)
+------------------+
| L3 Cache | (Largest, Shared SRAM)
+------------------+
|
V (Much Slower Access)
+------------------+
| Main Memory | (DRAM - Largest, Slowest)
+------------------+
|
V (Even Slower Access)
+------------------+
| Secondary | (HDD/SSD - Virtual Memory Swap)
| Storage |
+------------------+

Part 2: Introduction to 8085 Assembly Language Programming

The Intel 8085 is an 8-bit microprocessor, widely used for teaching fundamental
microprocessor concepts due to its relatively simple architecture. Assembly language
programming for the 8085 involves writing programs using mnemonics (short codes) that
directly map to the microprocessor's machine instructions.

1. The 8085 Programming Model

The programming model of a microprocessor describes the architecture from a programmer's

perspective, primarily focusing on the accessible registers and memory organization.
 ● Registers: The 8085 has a set of 8-bit and 16-bit registers used for storing data,
addresses, and status information.
o General Purpose Registers (8-bit):
▪ B, C, D, E, H, L: These are six 8-bit registers that can be used
individually or in pairs to form 16-bit register pairs:
▪ BC (B-high, C-low)
▪ DE (D-high, E-low)
▪ HL (H-high, L-low): This pair is special; it's often used as a
memory pointer (holds a 16-bit memory address) for
operations involving memory.
o Accumulator (A):
▪ An 8-bit register. It's the primary register for arithmetic and logic
operations. Most ALU operations implicitly use the Accumulator as
one operand and store the result back into it.
o Flag Register (F):
▪ An 8-bit register where only 5 bits are used as "flags" to indicate the
status of the last arithmetic or logical operation. (Same as Status
Registers discussed earlier in Processor Logic Design).
▪ S (Sign Flag): Set if MSB of result is 1.
▪ Z (Zero Flag): Set if result is 0.
▪ AC (Auxiliary Carry Flag): Set if there's a carry from D3 to D4 bit.
(Used in BCD arithmetic).
▪ P (Parity Flag): Set if result has even parity (even number of 1s).
▪ CY (Carry Flag): Set if there's a carry out of D7 (most significant
bit).
o Program Counter (PC):
▪ A 16-bit register that stores the memory address of the next
instruction to be fetched and executed. It is automatically
incremented after each instruction fetch.
o Stack Pointer (SP):
▪ A 16-bit register that points to the top of the stack in memory. The
stack is a LIFO (Last-In, First-Out) data structure used for temporary
storage, subroutine calls, and interrupt handling.
● Memory: The 8085 can address 64 KB (65,536 bytes) of memory, as it has a 16-bit
address bus. Memory locations are 8-bit wide (byte-addressable).

Conceptual Diagram: 8085 Programming Model

+---------------------+
| Accumulator (A) | (8-bit)
+---------------------+
+---------------------+
| Flag Register | (8-bit, 5 flags used: S Z AC P CY)
+---------------------+
+---------------------+
| General Purpose |
| Registers (8-bit) |
| B C D E H L |
+---------------------+
+---------------------+
| Program Counter (PC)| (16-bit)
+---------------------+
+---------------------+
| Stack Pointer (SP) | (16-bit)
+---------------------+

<------------>
16-bit Address Bus (to 64KB Memory)
<------------>
8-bit Data Bus (to Memory/I/O)

2. Instruction Classification

8085 instructions are typically classified into five major groups based on their function:

1. Data Transfer Instructions: Move data between registers, between a register and
memory, or load immediate data into registers. They do not affect flags.
o Examples: MOV (Move), MVI (Move Immediate), LXI (Load Register Pair
Immediate), LDA (Load Accumulator Direct), STA (Store Accumulator Direct),
LHLD (Load H and L Direct), SHLD (Store H and L Direct).
2. Arithmetic Instructions: Perform arithmetic operations (addition, subtraction,
increment, decrement). They affect flags based on the result.
o Examples: ADD (Add to Accumulator), ADC (Add with Carry), SUB (Subtract
from Accumulator), SBB (Subtract with Borrow), INR (Increment
Register/Memory), DCR (Decrement Register/Memory), DAA (Decimal Adjust
Accumulator).
3. Logical Instructions: Perform bitwise logical operations (AND, OR, XOR, NOT)
and compare operations. They affect flags.
o Examples: ANA (AND with Accumulator), ORA (OR with Accumulator), XRA
(XOR with Accumulator), CMA (Complement Accumulator), CMP (Compare
with Accumulator), RLC (Rotate Left Accumulator), RRC (Rotate Right
Accumulator).
4. Branching Instructions: Change the flow of program execution (jump, call, return).
o Conditional Jumps: JNZ (Jump if Not Zero), JZ (Jump if Zero), JNC (Jump if
No Carry), JC (Jump if Carry), etc.
o Unconditional Jumps: JMP (Jump).
o Call and Return: CALL (Call Subroutine), RET (Return from Subroutine).
o RST (Restart - software interrupt).
5. Machine Control Instructions: Control the CPU's operation, stack, or I/O.
o Examples: PUSH (Push to Stack), POP (Pop from Stack), IN (Input from Port),
OUT (Output to Port), HLT (Halt CPU), NOP (No Operation), EI (Enable
Interrupts), DI (Disable Interrupts).

3. Instruction Format

8085 instructions vary in length: 1-byte, 2-byte, or 3-byte instructions.

● 1-byte Instruction: Contains only the opcode.

o Example: MOV A, B (Move content of B to A), HLT (Halt).
● 2-byte Instruction: Contains the opcode followed by an 8-bit immediate data or port
address.
o Example: MVI A, 32H (Move immediate value 32H to Accumulator), IN 01H
(Input from port 01H).
 ● 3-byte Instruction: Contains the opcode followed by a 16-bit immediate data or a 16-
bit memory address.
o Example: LXI H, 2050H (Load HL with 2050H), LDA 4000H (Load
Accumulator from memory address 4000H).

Example Instruction Breakdown (3-byte): LDA 4000H

● Byte 1 (Opcode): 3A (Hex for LDA instruction)

● Byte 2 (Low-order address): 00 (Low byte of 4000H)
● Byte 3 (High-order address): 40 (High byte of 4000H)

Note: In 8085, multi-byte data/addresses are stored in memory in little-endian format (low
byte first, then high byte).

4. How to Write, Assemble, and Execute a Simple Program

The process involves several steps:

1. Writing the Program (Source Code):

o Use an assembly language editor (a simple text editor will do).
o Write the program using 8085 mnemonics.
o Each line typically has: [Label:] Mnemonic [Operand(s)] [; Comment]
o Example: Add two numbers and store the result

Code snippet

; Program to add two 8-bit numbers (05H and 03H)

; and store the result in memory location 2050H

MVI A, 05H ; Move immediate 05H to Accumulator

MVI B, 03H ; Move immediate 03H to Register B
ADD B ; Add content of B to Accumulator (A =
A + B)
STA 2050H ; Store Accumulator content at memory
address 2050H
HLT ; Halt the processor

2. Assembling the Program:

o An Assembler is a software tool that translates the assembly language source
code into machine code (binary instructions) that the 8085 can understand.
o The assembler generates an object file (containing machine code) and often a
listing file (showing assembly code alongside generated machine code and
addresses).
o Process: assembly_program.asm (Source Code) --(Assembler)-->
assembly_program.obj (Object Code)
3. Executing the Program:
o Loading: The machine code (from the object file) needs to be loaded into the
8085's memory at a specific starting address. This is typically done using:
▪ Microprocessor Kit: Manually entering the opcodes into memory
using a keypad, or using a serial interface to load from a PC.
 ▪ Simulator/Emulator: Software that simulates the behavior of the
8085. You load the object file directly into the simulator's virtual
memory.
o Running: Once loaded, the Program Counter (PC) is set to the starting
address of your program, and the CPU is instructed to "Go" or "Execute." The
CPU then fetches, decodes, and executes instructions sequentially.
o Debugging: Observing register values, memory contents, and flag states
during execution to verify correctness or find errors.

5. Overview of the 8085 Instruction Set

The 8085 instruction set is comprised of 246 opcodes, but many of these are variations of the
same instruction (e.g., MOV has many forms depending on source/destination). Key
instructions you should be familiar with include:

● Data Transfer:
o MOV Rd, Rs: Move data from source register (Rs) to destination register (Rd).
o MOV Rd, M: Move data from memory (addressed by HL) to register (Rd).
o MOV M, Rs: Move data from register (Rs) to memory (addressed by HL).
o MVI R, data: Move immediate 8-bit data to register R.
o MVI M, data: Move immediate 8-bit data to memory (addressed by HL).
o LXI Rp, 16-bit data: Load register pair Rp (BC, DE, or HL) with 16-bit
data.
o LDA addr: Load Accumulator with content of memory at addr.
o STA addr: Store Accumulator content at memory addr.
o LHLD addr: Load H and L with content of memory at addr and addr+1.
o SHLD addr: Store H and L content at memory addr and addr+1.
o XCHG: Exchange contents of DE and HL register pairs.
o SPHL: Move HL content to Stack Pointer.
o PCHL: Move HL content to Program Counter.
● Arithmetic:
o ADD R: Add content of register R to Accumulator.
o ADC R: Add content of register R with Carry to Accumulator.
o SUB R: Subtract content of register R from Accumulator.
o SBB R: Subtract content of register R with Borrow from Accumulator.
o ADI data: Add immediate 8-bit data to Accumulator.
o SUI data: Subtract immediate 8-bit data from Accumulator.
o INR R: Increment content of register R by 1.
o DCR R: Decrement content of register R by 1.
o INR M: Increment content of memory (addressed by HL) by 1.
o DCR M: Decrement content of memory (addressed by HL) by 1.
o INX Rp: Increment register pair Rp by 1.
o DCX Rp: Decrement register pair Rp by 1.
o DAD Rp: Add content of register pair Rp to HL.
● Logical:
o ANA R: Logical AND Accumulator with register R.
o ORA R: Logical OR Accumulator with register R.
o XRA R: Logical XOR Accumulator with register R.
o ANI data: Logical AND Accumulator with immediate data.
 o ORI data: Logical OR Accumulator with immediate data.
o XRI data: Logical XOR Accumulator with immediate data.
o CMA: Complement Accumulator (1's complement).
o CMC: Complement Carry flag.
o STC: Set Carry flag.
o CMP R: Compare Accumulator with register R (sets flags, doesn't change A).
o CPI data: Compare Accumulator with immediate data.
o RLC: Rotate Accumulator Left (through carry).
o RRC: Rotate Accumulator Right (through carry).
o RAL: Rotate Accumulator Left through Carry.
o RAR: Rotate Accumulator Right through Carry.
● Branching:
o JMP addr: Unconditional jump to addr.
o JZ addr: Jump to addr if Zero Flag is set.
o JNZ addr: Jump to addr if Zero Flag is reset.
o JC addr: Jump to addr if Carry Flag is set.
o JNC addr: Jump to addr if Carry Flag is reset.
o (Similar conditional jumps for Sign, Parity flags)
o CALL addr: Call subroutine at addr (pushes PC onto stack).
o RET: Return from subroutine (pops PC from stack).
o RST n: Restart (software interrupt to specific addresses).
● Stack, I/O & Machine Control:
o PUSH Rp: Push register pair Rp onto the stack.
o POP Rp: Pop register pair Rp from the stack.
o IN port-address: Input data from port-address to Accumulator.
o OUT port-address: Output data from Accumulator to port-address.
o HLT: Halt processor execution.
o NOP: No operation (does nothing, takes 4 clock cycles).
o EI: Enable Interrupts.
o DI: Disable Interrupts.