Understanding the Intel 8086 Microprocessor – A Detailed Guide
INTRODUCTION
Introduced in 1978 by Intel, the 8086 microprocessor is one of the most
influential chips in the history of computing. It laid the foundation for x86
architecture, which remains dominant even today. Despite being over four
decades old, learning about the 8086 is still relevant for students and
engineers to understand how modern microprocessors evolved from
simpler architectures.
CHAPTER 1: BASIC SPECIFICATIONS OF 8086
The 8086 is a 16-bit microprocessor designed using NMOS technology.
It has:
16-bit data bus (can process 16 bits of data at once)
20-bit address bus (can address up to 1 MB of memory)
Clock speeds ranging from 5 MHz to 10 MHz
29,000 transistors approximately
40-pin DIP (Dual Inline Package)
8086 was designed as a CISC (Complex Instruction Set Computer)
with over 100 instructions in its set.
CHAPTER 2: ARCHITECTURE OVERVIEW
The architecture of 8086 is divided into two main units:
1. Bus Interface Unit (BIU)
o Handles all data, address, and control bus interactions
o Performs address generation and prefetching
instructions
2. Execution Unit (EU)
o Executes instructions fetched by the BIU
o Contains Arithmetic and Logic Unit (ALU), registers, and
control circuitry
The BIU and EU operate simultaneously, allowing pipelining — while
the EU executes one instruction, the BIU fetches the next. This improves
performance.
CHAPTER 3: REGISTER ORGANIZATION
8086 features several types of registers, all of which are 16-bit:
a) General Purpose Registers
AX – Accumulator
BX – Base Register
CX – Counter Register
DX – Data Register
Each can also be accessed as 8-bit halves (AH/AL, BH/BL, etc.)
b) Segment Registers
CS – Code Segment
DS – Data Segment
SS – Stack Segment
ES – Extra Segment
These are used for memory segmentation, a unique feature of 8086.
c) Pointer and Index Registers
SP (Stack Pointer)
BP (Base Pointer)
SI (Source Index)
DI (Destination Index)
d) Flag Register
Contains status and control flags (e.g., Zero, Carry, Sign, Overflow).
CHAPTER 4: MEMORY SEGMENTATION
The 8086 uses a memory segmentation model to access its 1MB address
space using 16-bit registers.
A segment is a 64 KB block of memory
The physical address is calculated using:
Physical Address = Segment × 10h + Offset
Advantages:
Simplifies addressing
Enables multitasking
Supports modular programming
Disadvantages:
Complexity in managing segments
Can lead to overlapping memory regions
CHAPTER 5: INSTRUCTION SET OVERVIEW
8086 has a rich set of instructions, broadly classified into:
Data Transfer – MOV, PUSH, POP, XCHG
Arithmetic – ADD, SUB, MUL, DIV, INC, DEC
Logical – AND, OR, XOR, NOT, TEST
Control Transfer – JMP, CALL, RET, JZ, JNZ
String Instructions – MOVS, LODS, STOS
Flag Manipulation – CLC, STC, CLI, STI
The variable-length instruction format provides flexibility but adds
decoding complexity.
CHAPTER 6: INTERRUPTS AND DMA
8086 supports 256 interrupt vectors, each 4 bytes (2 for segment, 2 for
offset). Interrupts are classified into:
Hardware Interrupts – Initiated by external devices (via INTR or
NMI pins)
Software Interrupts – Triggered via the INT instruction
Exceptions – Errors like divide-by-zero
The 8086 also supports Direct Memory Access (DMA) via external
controllers, though it doesn't have built-in DMA hardware.
CHAPTER 7: ADDRESSING MODES
Addressing modes define how the operand is accessed in an instruction.
8086 supports the following:
1. Immediate – Operand is a constant value (e.g., MOV AX, 5)
2. Register – Operand is in a register
3. Direct – Uses a specific memory address
4. Register Indirect – Uses register as pointer (e.g., [BX])
5. Based – Combines base register and offset
6. Indexed – Uses index register with offset
7. Based Indexed – Combines base + index
8. Relative – Used in jumps and calls
These modes provide great flexibility in accessing data.
CHAPTER 8: MINIMUM AND MAXIMUM MODE
The 8086 can operate in two modes:
Minimum Mode – Used for single-processor systems. The 8086
controls all bus signals directly.
Maximum Mode – Used in multi-processor systems. Requires an
external bus controller (Intel 8288).
Mode selection is done using the MN/MX pin. The choice affects which
signals are active and how the CPU interacts with other devices.
CHAPTER 9: TYPICAL INSTRUCTION CYCLE
Each instruction in 8086 is processed in a cycle:
1. Fetch – Instruction is fetched by BIU from memory
2. Decode – EU decodes the instruction
3. Execute – ALU performs the operation
4. Writeback – Result is stored
Because of instruction prefetching, execution is faster. The BIU can fetch
up to 6 bytes in advance using its instruction queue.
CHAPTER 10: APPLICATIONS AND LEGACY
Though obsolete in commercial systems today, the 8086 remains widely
used in:
Educational microprocessor labs
Embedded systems with legacy designs
Historical emulators
Boot code development (many BIOS implementations are 8086-
compatible)
Its architectural philosophy deeply influenced later x86 processors,
including 80286, 80386, and modern Intel CPUs.
CONCLUSION
Understanding the 8086 microprocessor offers valuable insights into how
computers were built during the early days of personal computing. It
blends simplicity with power, making it an ideal learning platform for
budding engineers.
The design principles introduced in 8086 — segmentation, register-based
architecture, and CISC instruction sets — are still echoed in today’s
computing systems.
By studying this chip, you gain more than technical knowledge — you gain
a historical appreciation for the digital age we live in.
