AD& DIA

CONVERTERS
110INTRODUCTION
Itis important for a system to convert the available signal into digital form and vice-versa

There are basic two types of converters named as A/D converter and D/A coaverter.

Covener.
The process of conversion from an analog signal to digital signal is refered to as an Analog to Digtai
ADC or AD converter).
fed to D/A converer o ge
Whenever, the output of the system required to be in analog form then the digital inpats
are

ack the original analog signal. For this purpose Digital to Analog Converter
(DAC or D/A Coaverter) is used

1.1 DIGITAL TO ANALOG (D/A) CONVERTERS

Types of D/A converters are
1. Binary Weighted Resistance D/A converter

2.R-2R Ladder D/A converter

Binary Weighted Resistance D/A Converter 11.1.

shown in ñg.
for 3-bit input datais
as
resistance DAC
1OCk diagram of binary weighted

20LSB)
Resistance Analog
Ourput
Digital
Inputs 2
Divider
Circuit
2

(MSB)
Converter.
Weighted DA
Functionalblock
diagram of Binary
g. 11.1

843
 DESIGN
CIRCUITS & LOGIC
DIGITAL
844 Table 11.1 shows digital inputs and their corresponding analog oupu
TABLE 11.1

Analog Outputs
Digital Inputs
OV
0 0
+1V
0
0 +2V
+3V
0
+4V
0
+5V

+6V

1 1 +7V
1

Table 1. Shows digital inputs and their corresponding outputs

for an input of 001 the output will be +1V.
Let us assume that the digital input levels are 0 OV and 1 +7V. Now,
=

of 100 will provide an output of +4V. The digital

Similarly, an input of 010 will provide an output of +2V, and an input
input 011 is seen to be a combination of signals 001 and 010.
If the +1V from the 20 bit is added to the +2V from the 2l bit, the desired +3V output for the 011 input is achieved
Desired output levels are shown in table. 11.1.
Thus, the resistive divider circuit must do two things in order to change the digital input into an equivalent analog

output voltage.
1. The 20 bit must be changed to +1V and 21 bit must be changed to +2V, and 22 bit must be changed to + 4V.
2. These three voltages represents the digital bits and they must be summed together to form the analog output
voltage.
Its internal structure is as shown in fig. 11.2 for a 3-bit digital input.

Digital Inputs
22 2 0
(MSB) LSB)

Ro

Analog Output (VA)

RLRo

Fia. 11.2 Internal structure of Binary Welghted Resistan D/A Converter.

Tt can be solved by using Millman's theorem. According to Milman's theorem equation is given by

-Y/Ro +V/R+V2/R, +V, /R t..

e***
1/R +1/R, +1/R, +1/R, t..********
 example
t a k e
an 845
us
Let MSB LSB
input
is 01 i.e., V2V,Vo= 001
fdigital

us a s s u m e logic 0 = 0V
Let
logic 1=+7V

circuit is as shown in fig. 11.3.

quivalant
Is

Vi No +7V=1
OV OV

4
R2 =R. RRo

VA

RL>Ro

input (001)2
Converter for given
Resistance DA
a. 11.3 Equivalent circult of Binary Weighted
ACcording to Millman's theorem V, =
V, =0V)
/R,14)
V/R,/2)+V,
Vo7V,

A =R +
, +1/(R/2)+1/R,14)
1/R
V

7/R+0+0 1/Ro
o=+1V
4
+

Ro Bo Ro
So, the output is
alog+1V.
t will
be mo anotherdata.
more clear if we consider

he
digital data is 011, we have
logic 0= OV data)
[Assumed
+7V
1=
logic
846 Its
DIGITAL CIRCUITS& LOGIC DESIGN
equivalent circuit is as shown in fig. 114.
V2 V
+7V 1 Vo N 1

OV

Ro4 R2 Ro
2 R Ro

VA

RL>Ro

Fig. 11.4 Internal structure of Binary Weighted Resistance D/A converter for given input data(001)
According to Millman's theorem

,= g + Y/R,/2) + V,(R,/4) Vo+7 V, V, = +7 V, V2 =0V)

.
Ro (R/2) (R,/4)
7/R+7/(R/2)+0
2+4
Ro Ro Ro
714
Rg Ro-7+14 2 =+3V
Ro
Thus, analog output is +3V.

[Link] Drawbacks or Disadvantages of Binary Welghted Reslstance D/A Converter

There are two drawbacks of resistive divider or binary weighted resistance DIA converter

1. Each resistor in the network have a different value.

2. More resistors are used thus much greater currents are needed.
For Example LSB

In 10-bit system, the current through the MSB resistor is approximately 500 times as large as the current througn

resistor.
Due to these drawbacks second types of reslstive network is used called as 'R-2R ladder' network
Converter
11.1.2 R-2R Ladder D/A r make

l tovercomes the drawbacks of resistive network in which different values of resistances are used. R-2R ladder
f only two values of resistor 1.e. K and 2K. It 1s as shown in fig. 11.5 for a 4-bit digital input.
 VERTTERS
ERTERS
Digital Inputs
847
(LSB)
(MSB)

2R 2R
2R R

w ww
2R A
w w
R B R C R D
D
VA
Analog
Ci 11.5 Internal structure of R-2R
Output
Ladder digital to
the formula analog converter.
I uSes

Vo 2+V 2 +V, 22 +V, 23 +.

2n
Lets take an example
f digital data is 0101 i.e., 4-bit data
Let us assume logic 0 = OV
logic 1 = +16V
2 =
I6 for 4-bit
LSB MSB
Digital Inputs = 0101

2 2 2 2
n=
Number of bits.
Here, n =
4(as data is 4-bit)
2R 2R 2R 2R

w w- ww VA
2R A R B R C R D Analog
Output
v,Yox20 +V 2 +Va 22 +V, 2 16x1+0x2+16x4
16
+0x8 16+6480
16
us, the analog
outputis +5V.
imilarly, if the iven data is 1000, we get
v. - Ox20+0x2
VA +0x22 +16x2 16x8
16x8= 8V
Thus, nalog output is 2
16
8V for binary 1000.
Performance
1.
Rer
esolution
Characteristice of D/A Converters discrete steps in the D/A outputs. Thus, resolution
number of
:
Reso.
on the number Solution is the reciprocal of the
following equation
bits
Or in a digital system. It is given by

where. N = Number of bits.

R N -1
 LOGIC DESIGN
DIGITAL CIRCUITS&
848
Percentage resolution is given by %R= 100
Put N = 1, 2,3 . . we get the appropriate percentage resolution.
and expected output. It is given as a percentan
. Accuracy: It is a measure of the difference between actual output
of the maximum output voltage. If the maximum output voltage i.e. full scale deflection 1s >V and accuracy is t0.1% then
n.
the maximum error is xS = 0.005 V or 5mV. Ideally the accuracy should be better than t 0.5 of LSB.
100
In an 8-bit converter LSB is= or 0.39% of full scale. The accuracy should be better than 0.2%

3. Linearity: The linearity of the converter specifies the accuracy with which the ideal performance is followed
Output of D/A Converter must be each step up (down) in the digital input so as to cause an increase (decrease) in the analog

output. The linearity should be at least equal to or better then 4LSB

4. Setting Time: Whenever a digital input is applied to D/A converter, sometimes output sets to a value within some

specified limit of the final value. The limit range is -LSB or less. This parameter tells the speed of D/A converter and
it can be calculated by use of switches, amplifier, resistors etc. in the device.
EXAMPLE 11.1 A 6-bit R-2R ladder D/A converter has reference voltage of 6.5 V. It meets standard linearity.
Calculate 1. Resolution in Volts and Percentage 2. Full Scale Voltage 3. Output for O11100
4. Range in output for (0) 5. Quantization error
1
SOLUTION: 1. Resolution 2

AS, n =6 (for 6-bit) .. % Resolution = xl00=x100 or T%R 1.578

63

Resolution in Volts = Ref==0.3=0 1V

2n

2. Full scale voltage (FSV) is given by FSV=VRef =6.s =6.5x=6.398 =6.4V

3. Output for 011100 is given by

Vout Vo 20+V 2+V,22 +Va,23 +V,2 +V,25

2

Here, datais
0
1 0
MSB Vs V4 V V2 V Vo LSB

and n = 6 (for six bit data) 0+0+1x22 +1x23 +1x24 +0

or, out 26
Here, Logic 1 = +6.5 V
Logic 0 = 00v Because, reference voltage V, =6.3

out
6.5x2+6.5x 23 +6.5x24
64

also, Vo65x284 V 04
 A/D AND D/A
CONVERTERS
is specifiedby linearity which is
m deviation LSB
Matun
849
LSB =
Resolution is Volts =
0.1 V

Therefore,
LSB =+0.05 V
Range = 2.84 +0.05 V
Thus
Qvantization error is given by

Q.E. =
LSB 0.05_0.05
2
2-1 26-1630.00079
9% Q.E. = 0.079 %

ANALOG TO DIGITAL (A/D) CONVERTERS

2 AN.
converters are:
Tipes of A/D
[Link] or Flash or Parallel Comparator A/D converter (Parallel A/D converter).flas
Continuous Counter A/D Converter or Up/Down Counter A/D converter
(Counter type A/D converter)
3. Single slope A/D converter.
A Dual slope A/D converter
. Seccessive approximation A/D converter.

11.2.1 Simultaneous or Flash or Parallel Comparator AD Convertex

The process of converting analog voltage to digital is known as A/D conversion. The simplest method used for its
vesion is simultaneous method. For this simultaneous A/D converter is used.
i consists of number of operational amplifiers. For three bit (i.e., X X1 Xo). (N - 1) op-amps are used. Where.
N=qumber of possible combinations. (from formula 2 =N, ie., n= number ofbits and N= number of possiblecombinations)
used here.
Thus, for3-bit we have 23 =8. Hence, (8- 1) 7 op-amps are used. Op-amp as
=
acomparator is
There is one reference voltage which is different for different op-amps. The analog andreferencevoltages are compared
slot of 1V starting from 0.5V. For
u p u t of op-amp. For simplicity reference voltages are in the 1.5V, for difference
r " op-amp V,= reference voltage 0.5V, for 2nd op-amp the = V,= 3 op-amp V, =2.5V and so on.
is less than 0.5V, comparator outputs are
'0'. If analog signal is equal to 0.5V and greater than
SV but leeeE gnal the range of analog inputs,
1.5V, than 1st comparator output is High and others are Low. Similarly,
U han the
are as shown in
table 11.2.
TESponding comparator puts and digital or binary inputs
TABLE 11.2
Binary Outputs
Analog Inputs Comparator Outputs
2nd 1st
Vs (Volts) 7th 6th 5th 4th 3rd
0 0
0
Vs<0.5 0 0 0
1 0 1
05 s Vs<1.5 0 0
1 0
15 Vs<2.5 0 1 1
25 s Vs<3.5
0 1
3.5 s Vs<4.5 0
4.5 Vs< 5.5 1 1
0 0
S.5 Vs< 6.5 1
1
1
Vs26.5 1
 & LOGIC DESIGN
DIGITAL CIRCUITS
voltage V, is less than the reference vol.
850 voltage. If the input
with reference than V, then it is taken as "
Comparator compares the input voltage Low ie. 0'. If V, V, or greater =
ie.
Le. ,<V, then, the output of comparator goes
with reference voltage and thus, gives the outn t in
the input voltage
of
output High. So, it compares
comparator goes
1's. It is shown in fig. 11.6.
digital form ie. in 0's and as

V, Voltage Y(Output)
Comp
(Inputs,Voltage
and V, voltages.
Fig. 11.6 Comparator with V,
can be designed. The
table gives following points
From table 11.2 the circuit diagram
is high.
(1)
X is high ie.. '1' only when, 4th comparator output

high for 6th comparator +(2ndx 4h)

is comparator
2) X,
(3) Xg is high for comparators 7th + 1st 2nd 3rd 4th +5th6th
is shown in figure 11.7.
Simultaneous or Flash or Parallel AD Converter
as

6.5V

5.5V

4.5V

3.5V

Digital
Xi Outputs
2.5V
D
1.5V Xo

0.5V

Analog Reference
Input (V) Voltage (V)
Voltage
Fig. 11.7 Internal structure of parallel AD Converter
Lets take an example -»
Let V. analog Input = 5V

The output should be 101 in digital.

 A/D AND D/A CONVERTERS
851
11.8 as shown.
rfrom the figure

öclear

5V
OV<V
SV6SV

6
O(V,<V,

SVSVv

1(:V>V
sv4SV

0
V,>V
S v 3 S V 0 X D i g i t a l

X1 Outputs
1:V,>V, 0

sv 2.5V

2
iV,>V,
S V S V v

1(V,>VN

0.5V

Analog Reference (V)

InputVoltage
Vs 5V
5 V.
voltage V,
converter
for analoginput
parallel
A/D
of
Fig.11.8 Internal structure ture
101
=

From figure 11.8, we get output X2 X1

(MSB) LSB)

Converter
Thus, Vs = 5V = (101)2
up/down)
Counter
AD

1.2.2 Continuous Counter A Converter (or c o n v e r t e r

are

of this
comnponents

make use of D/A onverter in it. The main

[Link] converter
[Link]
[Link]-down counter
[Link] unit and
[Link].
 CIRCUITS & LOGIC DESIGN
DIGITAL
852 It is as shown in figure 11.9

Analog
Input V Control
Logic
V, Comparator

Up Down Command
Command Clock
Reference
Voltage Do Q0
D/A
Di Qi Up/Down
Converters D2 - Q2 Counter

D3

Latches

Digital Output
converter.
Fig. 11.9 Black diagram of counter type A/D
i.e. op-amp at its non-inverting input. The
The analog input which is to be viewed as digital is given to the comparator
If the
reference voltage V, which is to be compared with the analog input V; comparator.
at
output of D/A converter is the 'l' and due to
the output of comparator goes High i.e.
reference voltage V, is less than the analog input V; ie. V,< Vi,
counter gives the binary counts and an analog reference output
which the counter is in up mode via control logic. Thus, the
with the analog voltage Vi. Whenever, the V, i.e. reference
is obtained from the D/A converter which is then compared
of Low i.e. '0' and the counter comes in the
voltage becomes equal to V; i.e. analog voltage then the output comparator goes 15
starts counting up and if input
down mode through control logic. If the analog input is increasing then the counter
decreasing, the counter continues to count back i.e. down. It is as shown in figure 11.10.

12 Continuous
11 Analog Signal
10-
9
8
7 D/A Converter Output
Magnitude 6

Time ()
Flg. 11.10 Input-output waveforms for counter type A/D converter
 AD AND D/A CONVERTERS
If the input is 853
constant, the counter backs down
on count when a
count, the reference voltage comparison takes
place t ooes High and coun
V,becomes a bit less than
goes to p analog output
again. So, if the input is constant, this back and forth voltage V, the comparator ou e t Such type of
output waveforms. action continuous and due to wicn v 8
112.4 Dual Slope A/D Converter
Dual slope AD convertor is used because it is free from the noise which is not overcome by single slope A/D convert
It uses op-amp as integrator amplifier for ramp generator. It is called dual slope because it uses afixed slope as well as
vanable slope ramp. It is as shown in figure 11.12.

Integrator Unit Gain

Analog R
Input
W- Amplifier as a Comparator
V;=Vin Integrating
Amplifier
Nref
Reference Electronic
Switch
Voltage Control
Logic

R
Counter

Clock

Latches

D3 D2 D1
Doj
Digital Outputs
Fig. 11.12 Black diagram of Dual Slope AD Converter.
 A/D AND D/A CONVERTERS
he integrating op-amp uses a capacitor in the feedback path as clearly shown in figure 855
Output voltage of integrating op-amp is given by -

o-i d=-Vd RC

Thus, the output voltage is integral ofanalog input voltage. IfVin is constant we get an output-Vi which is a

fxed ramp. If Vin is varying we get a ramp fixed as well as variable slope at its output.
Let the output ofintegrator be zero and initially the counter be reset i.e. starts from 0000 (for 4-bit counter). A positive
nalog input voltage Vin is applied through electronic switch S, we get a ramp output and the counter starts counting. When
inecounter reaches a specified count, it will be reset again and the control logic switches to the negative reference voltage
-Vthrough switches. At this instant the capacitor'C' is charged to a -ve voltage -V" proportionalto analog input
wdtageofV, When-Veamplifier
isconnected the
capacitor C' starts discharging linearly due to constant currentfrom-V,et The
is now positive fixed slope ramp which starts at -V'.
a
output integrating
As the capacitor discharges, the counter starts from reset state, when the output of integratorbecomes zero due to
the CLK. through AND gate. Thus, the counter stops and the
which the comparator output becomes Low and it disables to
one conversion cycle. The binary count is proportional
digital output can be obtained from latches. This completes
analog input Voltage Vin or V

11.2.5 Successive Approximation A/D Converter

than the digital ramp A/D converter but it has much
Itis the most widely used A/D convertor. It has more complex circuitry
n-successive steps are required for completing the approximation process.
shorter conversion time. For n-bit A/D converter
A/D converter are
The various functional blocks of successive approximation
be used)
1. Comparator 2. D/A Convertor (Binary ladder may
3. Control Logic 4. Successive Approximation Register (SAR)
11.13.
SAR consists of flip-flops and level amplifiers. It is as shown in figure
Analog Input Voltage

V Control Logic
V, Comparator CLK
(Reference
Voltage)
-R
Flip Flops >Flip Flops
are used

SAR

Level Amplifiers
D3
Latches D2|
D
Do
Digital outputs
D/A Converters

Converter.
Approximation Type AD
11.13 Black diagram of Successive
Fig.
856 DIGITAL CIRCUITS & LOGIC DESIGN
c Contro logic is used to set or reset the flip-flops. The output of these flip-flops are given to level amplifiers and
D A converter which is a binary ladder network. It gives digital outputs as well as the analog reference voltage V.

nitialy the control logie resets all the

fnip-flops. There three baslc conditions are
, < V , i.e. reference voltage from D/A converteris less than the input analog voltage, then MSB (most significant
bit) is set to
'T' by control logic.
2.
If V,> V, then MSB is reset to (zero) '0' and next bit is set to
3.
l V,=V, then the control logic disables the clock to flip-flops and we get digital outputs from SAR by usine
latches.
Let us consider an
example for its working
4-bit SAR is used. Let 4V and let us assume that the counter is reset to zerO. L.e. V, =U
V, =

Now, V,<V, MSB is set to 1,

Output of SAR will be 0000 (Because, (1000,) (8)10
=

1000

Now, V,8V and V, 4V =

V,>V, next MSB is set and first one reset to zero.

0100
Now, V,= 4V and V, = 4V

V,=Vi
Clock is disabled by control logic and we get 4V as analog voltage in digital output 0100.
Consider another example for its
working
LetAnalog Voltage be V 5V and intially V, 0, thus V,< V, First MSB in set to '1', output
= =
of SAR =
1000.
Again, V, = 8V and V; = 5V

V,>V
Ist MSB is reset to 0' and 2nd MSB is set to '1', output of SAR = 0100
Again, V,=4V, and V; = 5V

Next MSB is set

V,<V
to 1, output of SAR = 0110
Again, V,=6V, and V, = 5V

3rd MSB is
V,>V
set to zero and 4 bit is 1', output of SAR 0101.
set to =

V,= Vi =5V
Now clock is disabled by control logic and output of SAR 0101 = is obtained as digital output through latches.
EXAMPLE 11.3 Find the sanversian time & c roio
 A/D AND D/A CONVERTERS
26 Performance Characteristics of AD Converter
857
126

defined
is del as the voltage input change necessary for one bit hange in the output. For n bit ADC, the
Resolution : It
1.
levels are 2"- 1.
Rmber of output
Full scale input Full scale I/P
Resoluton=
[Link] O/P levels 2"-1
Eor Example: 10 bit ADC having an I/P voltage range of -10 and + 10V. The resolution is given by:
or

Voltage I/P 10-(-10) 20 = 19.5 mV.

2h-1 210-1 1023

%Resolution = x 100%

(Because,n =4)
For 4 bits, %Resolution = 2"-1x100x100
15
=6.7%.

(Or)
Resolution may also be defined in two ways
(a) A DAC that can provide
number of different analog output values is called Resolutions.
For a DAC having n-bits
Resolution 'R' =2".
1 least significant
A DAC in which the ratio of change
in output voltage resulting from a change of 1 LSB (i.e.,
(6)
known as resolution.
bit) at the digital inputs is
Resolution for n-bit DAC is given by

Resolution R = Where, VOFS= Full scale output voltage.

2-1

"%R'= OFSx100.
Percentage Resolution -1
resolution is known, we have:
obtained for DAC, if the
Input-Output equation can also be
D
Vo= Resolution x
where, Vg =Output voltage.
D Decimal value of the digital input.
R
x 100 X100
2-1
If Vo R where R = Resolution. Then, %
Resolution= R(2n_
converter determines the number of bits which can
ADC i.e. analog to digital
Accuracy: The accuracy of a given
2.
be usefully provided. etc. Typical values are t 0.02% of the full scale
error system noise
ADC consists of quantization
he accuracy of an reading. The
reading. 0.02% of full scale
10V. If the accuracy is
ADC OR with input range of t
For Example: Consider an limitation is 2mv.
naximum error due to such accuracy
(Or)
and the expected analog output,
the actual analog Output
difference between
ACCuracy may also be
defined as the
in percentage. In ideal case the accuracy of DAC should be at worst,
whenud given digital input in applied. It is expressed
+of its LSB.
VOFS
Accuracy 2(2-1)
 DESIGN
$58 DIGITAL CIRCUITS & LOGIC complete measurment by analog
time requires for a
Conversion Time or Setting Time: lt is the time refers to the
to digital converter.
(Or)
It 1s dcpendent on the
amplifiers
into its digital equivalent.
m e required for conversion of analog signal
output and switches response time.
converter directly determines the relative
4Linearity: Linearity is basically a "best staraight line'. Lincarity of a actual
the oonverter. It is the difference of errors betweens
the nominal and
the ruil
scale analog value
ratios to error should
ury
o and independent of full scale
calibration. The linearity be less than
esponding to a given digital input

LSB
must be specified over
error, monotonicity and otiset
SStability : When all the parameters such as gain, linearity the converter.
Dc power supply ranges and full temperature then these parameters
represent the stability of
for a
decrease or skip at any point continuously increas ing
Monotonicity: The output of AD convertor should not
input signal. It is known as monotonicity of A/D convertor.
(Or)
counter, then it is said to have a
during its entire range stepped by
a
ifa converter does not miss any step backward
coaverter having good monolonicity.