a LC2MOS Dual, Complete,

12-Bit/14-Bit Serial DACs

AD7244
FEATURES FUNCTIONAL BLOCK DIAGRAM
Two 12-Bit/14-Bit DACs with Output Amplifiers
AD7242: 12-Bit Resolution
AD7244: 14-Bit Resolution
On-Chip Voltage Reference
Fast Settling Time
AD7242: 3 ␮s to ⴞ1/2 LSB
AD7244: 4 ␮s to ⴞ1/2 LSB
High Speed Serial Interface
Operates from ⴞ5 V Supplies
Specified Over –40ⴗC to +85ⴗC in Plastic Packages
Low Power – 130 mW typ
AD7242isobsolete

GENERAL DESCRIPTION
The AD7242/AD7244 is a fast, complete, dual 12-bit/14-bit
voltage output D/A converter. It consists of a 12-bit/14-bit
DAC, 3 V buried Zener reference, DAC output amplifiers and
high speed serial interface logic.
Interfacing to both DACs is serial, minimizing pin count and
allowing a small package size. Standard control signals allow
interfacing to most DSP processors and microcontrollers.
Asynchronous control of DAC updating for both DACs is made
possible with a separate LDAC input for each DAC. PRODUCT HIGHLIGHTS
1. Complete, Dual 12-Bit/14-Bit DACs
The AD7242/AD7244 operates from ± 5 V power supplies, The AD7242/AD7244 provides the complete function for
providing an analog output range of ± 3 V. A REF OUT/REF generating voltages to 12-bit/14-bit resolution. The part
IN function allows the DACs to be driven from the on-chip 3 V features an on-chip reference, output buffer amplifiers and
reference or from an external reference source. two 12-bit/14-bit D/A converters.
The AD7242/AD7244 is fabricated in Linear Compatible 2. High Speed Serial Interface
CMOS (LC2MOS), an advanced mixed technology process that The AD7242/AD7244 provides a high speed, easy-to-use,
combines precision bipolar circuits with low power CMOS serial interface allowing direct interfacing to DSP processors
logic. Both parts are available in a 24-pin, 0.3-inch wide, plastic and microcontrollers. A separate serial port is provided for
or hermetic dual-in-line package (DIP) and in a 28-pin, plastic each DAC.
small outline (SOIC) package. The AD7242 and AD7244 are
available in the same pinout to allow easy upgrade from 12-bit 3. Small Package Size
to 14-bit performance. The AD7242/AD7244 is available in a 24-pin DIP and a 28-
pin SOIC package offering considerable space saving over
comparable solutions.

TheAD7242isnolongeravailable.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices. Fax: 781/461-3113 © Analog Devices, Inc., 2015
 = +5 V ⴞ 5% V = –5 V ⴞ 5%, AGND = DGND = 0 V, REF INA =
AD7242/AD7244–SPECIFICATIONS (VREF INB = +3 V. V , V load to AGND: R = 2 k⍀, C = 100 pF.
DD SS
OUTA OUTB L L
All Specifications TMIN to TMAX unless otherwise noted.)
AD7242
Parameter J, A Versions1 K, B Versions1 Units Test Conditions/Comments

DC ACCURACY
Resolution 12 12 Bits
Integral Nonlinearity ±1 ± 1/2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed Monotonic
Bipolar Zero Error ±5 ±5 LSB max
Positive Full-Scale Error2 ±5 ±5 LSB max
Negative Full-Scale Error2 ±5 ±5 LSB max

REFERENCE OUTPUT3
REF OUT @ +25°C 2.99/3.01 2.99/3.01 V min/V max
TMIN to TMAX 2.98/3.02 2.98/3.02 V min/V max
REF OUT Tempco 35 35 ppm/°C typ
Reference Load Change
(ΔREF OUT vs. ΔI) –1 –1 mV max Reference Load Current Change (0 μA–500 μA)

REFERENCE INPUTS
REF INA, REF INB Input Range 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%
Input Current 1 1 μA max
LOGIC INPUTS
(LDACA, LDACB, TFSA, TFSB,
TCLKA, TCLKB, DTA, DTB)
Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5%
Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5%
Input Current, IIN ± 10 ± 10 μA max VIN = 0 V to VDD
Input Capacitance, CIN4 10 10 pF max

ANALOG OUTPUTS
(VOUTA, VOUTB)
Output Voltage Range ±3 ±3 V nom
DC Output Impedance 0.1 0.1 Ω typ
Short Circuit Current 20 20 mA typ

AC CHARACTERISTICS4
Voltage Output Settling Time Settling Time to Within ± 1/2 LSB of Final Value
Positive Full-Scale Change 3 3 μs max Typically 2 μs
Negative Full-Scale Change 3 3 μs max Typically 2 μs
Digital-to-Analog Glitch Impulse 10 10 nV secs typ DAC Code Change All 1s to All 0s
Digital Feedthrough 2 2 nV secs typ
Channel-to-Channel Isolation 110 110 dB typ VOUT = 10 kHz Sine Wave

POWER REQUIREMENTS
VDD +5 +5 V nom ± 5% for Specified Performance
VSS –5 –5 V nom ± 5% for Specified Performance
IDD 27 27 mA max Cumulative Current from the Two VDD Pins
ISS 15 15 mA max Cumulative Current from the Two VSS Pins
Total Power Dissipation 195 195 mW max Typically 130 mW
NOTES
1
Temperature ranges are as follows: J, K Versions: –40°C to +85°C; A, B Versions: –40°C to +85°C.
2
Measured with respect to REF IN and includes bipolar offset error.
3
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
4
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.

–2– REV. B
 AD7244
AD7244
Parameter J, A Versions1 S Version1 Units Test Conditions/Comments

DC ACCURACY
Resolution 14 14 Bits
Integral Nonlinearity ±2 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed Monotonic
Bipolar Zero Error ± 10 ± 10 LSB max
Positive Full-Scale Error2 ± 10 ± 10 LSB max
Negative Full-Scale Error2 ± 10 ± 10 LSB max

REFERENCE OUTPUT3
REF OUT @ +25°C 2.99/3.01 2.99/3.01 V min/V max
TMIN to TMAX 2.98/3.02 2.98/3.02 V min/V max
REF OUT Tempco 35 35 ppm/°C typ
Reference Load Change
(ΔREF OUT vs. ΔI) –1 –1 mV max Reference Load Current Change (0 μA–500 μA)

REFERENCE INPUTS
REF INA, REF INB Input Range 2.85/3.15 2.85/3.15 V min/V max 3 V ± 5%
Input Current 1 1 μA max
LOGIC INPUTS
(LDACA, LDACB, TFSA, TFSB,
TCLKA, TCLKB, DTA, DTB)
Input High Voltage, VINH 2.4 2.4 V min VDD = 5 V ± 5%
Input Low Voltage, VINL 0.8 0.8 V max VDD = 5 V ± 5%
Input Current, IIN ± 10 ± 10 μA max VIN = 0 V to VDD
Input Capacitance, CIN4 10 10 pF max

ANALOG OUTPUTS
(VOUTA, VOUTB)
Output Voltage Range ±3 ±3 V nom
DC Output Impedance 0.1 0.1 Ω typ
Short Circuit Current 20 20 mA typ

AC CHARACTERISTICS4
Voltage Output Settling Time Settling Time to Within ± 1/2 LSB of Final Value
Positive Full-Scale Change 4 4 μs max Typically 2.5 μs
Negative Full-Scale Change 4 4 μs max Typically 2.5 μs
Digital-to-Analog Glitch Impulse 10 10 nV secs typ DAC Code Change All 1s to All 0s
Digital Feedthrough 2 2 nV secs typ
Channel-to-Channel Isolation 110 110 dB typ VOUT = 10 kHz Sine Wave

POWER REQUIREMENTS
VDD +5 +5 V nom ± 5% for Specified Performance
VSS –5 –5 V nom ± 5% for Specified Performance
IDD 27 28 mA max Cumulative Current from the Two VDD Pins
ISS 15 15 mA max Cumulative Current from the Two VSS Pins
Total Power Dissipation 195 205 mW max Typically 130 mW
NOTES
1
Temperature ranges are as follows: J Version: 0°C to +70°C; A Version: –40°C to +85°C; S Version: –55°C to +125°C.
2
Measured with respect to REF IN and includes bipolar offset error.
3
For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).
4
Sample tested @ +25°C to ensure compliance.
Specifications subject to change without notice.

REV. B –3–
AD7244
TIMING CHARACTERISTICS1, 2 (V DD = +5 V ⴞ 5%, VSS = –5 V ⴞ 5%, AGND = DGND = 0 V)
Limit at TMIN, TMAX Limit at TMIN, TMAX
Parameter (J, K, A, B Versions) (S Version) Units Conditions/Comments
t1 50 50 ns min TFS to TCLK Falling Edge
t2 75 100 ns min TCLK Falling Edge to TFS
t3 3 150 200 ns min TCLK Cycle Time
t4 30 40 ns min Data Valid to TCLK Setup Time
t5 75 100 ns min Data Valid to TCLK Hold Time
t6 40 40 ns min LDAC Pulse Width
NOTES
1
Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a volt-
age level of 1.6 V.
2
See Figure 6.
3
TCLK Mark/Space ratio is 40/60 to 60/40.

ABSOLUTE MAXIMUM RATINGS* Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

(TA = +25°C unless otherwise noted) Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V Power Dissipation (Any Package) to +75°C . . . . . . . 550 mW
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
*Stresses above those listed under “Absolute Maximum Ratings” may cause
VOUT to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS to VDD permanent damage to the device. This is a stress rating only, functional operation
REF OUT to AGND . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V of the device at these or any other conditions above those listed in the operational
REF INA, REF INB to AGND . . . . . . . –0.3 V to VDD + 0.3 V sections of this specification is not implied. Exposure to absolute maximum rating
Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V conditions for extended periods may affect device reliability.
Operating Temperature Range
J, K Versions
AD7244 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD7242 . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. WARNING!
Although the AD7242/AD7244 feature proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
ESD SENSITIVE DEVICE
precautions are recommended to avoid performance degradation or loss of functionality.

PIN CONFIGURATIONS

DIP SOIC

–4– REV. B
 AD7244
AD7242/AD7244 PIN FUNCTION DESCRIPTION
DIP
Pin No. Mnemonic Description
1 LDACA Load DAC, Logic Input. A new word is transferred into DAC Latch A from input Latch A on the fall-
ing edge of this signal. If LDACA is hard-wired low, data is transferred from input Latch A to DAC
Latch A on the sixteenth falling edge of TCLKA after TFSA goes low.
2 TFSA Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACA
data with serial data expected after the falling edge of this signal.
3 DTA Transmit Data, Logic Input. This is the data input which is used in conjunction with TFSA and
TCLKA to transfer serial data to input Latch A.
4 TCLKA Transmit Clock, Logic Input. Serial data bits for DACA are latched on the falling edge of TCLKA
when TFSA is low.
5 DGND Digital Ground. Both DGND pins for the device must be tied together at the device.
6 TP1 Test Pin 1. Used when testing the device. Do not connect anything to this pin.
7 VDD Positive Power Supply, 5 V ± 5%. Both VDD pins for the device must be tied together at the device.
8 AGND Analog Ground. Both AGND pins for the device must be tied together at the device.
9 VOUTB Analog Output Voltage from DACB. This output comes from a buffer amplifier. The range is bipolar,
± 3 V with REF INB = +3 V.
10 VSS Negative Power Supply, –5 V ± 5%. Both VSS pins for the device must be tied together at the device.
11 TP2 Test Pin 2. Used when testing the device. Do not connect anything to this pin.
12 REF INB DACB Voltage Reference Input. The voltage reference for DACB is applied to this pin. It is internally
buffered before being applied to DACB. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.
13 LDACB Load DAC, Logic Input. A new word is transferred into DAC Latch B from input Latch B on the fall-
ing edge of this signal. If LDACB is hard-wired low, data is transferred from input Latch B to DAC
Latch B on the sixteenth falling edge of TCLKB after TFSB goes low.
14 TFSB Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACB
data with serial data expected after the falling edge of this signal.
15 DTB Transmit Data, Logic Input. This is the data input used in conjunction with TFSB and TCLKB to
transfer serial data to input Latch B.
16 TCLKB Transmit Clock, Logic Input. Serial data bits for DACB are latched on the falling edge of TCLKB
when TFSB is low.
17 DGND Digital Ground. Both DGND pins for the device must be tied together at the device.
18 TP3 Test Pin 3. Used when testing the device. Do not connect anything to this pin.
19 VDD Positive Power Supply, 5 V ± 5%. Both VDD pins for the device must be tied together at the device.
20 AGND Analog Ground. Both AGND pins for the device must be tied together at the device.
21 VOUTA Analog Output Voltage from DACA. This output comes from a buffer amplifier. The range is bipolar,
± 3 V with REF INA = +3 V.
22 VSS Negative Power Supply, –5 V ± 5%. Both VSS pins for the device must be tied together at the device.
23 REF OUT Voltage Reference Output. To operate the DACs with this internal reference, REF OUT should be
connected to both REF INA and REF INB. The external load capability of the reference is 500 μA.
24 REF INA DACA Voltage Reference Input. The voltage reference for DACA is applied to this pin. It is internally
buffered before being applied to DACA. The nominal reference voltage for correct operation of the
AD7242/AD7244 is 3 V.

REV. B –5–
AD7244
CIRCUIT DESCRIPTION 9-bit R-2R ladder structure while on the AD7244, the 11 LSBs
The AD7242/AD7244 contains two 12-bit/14-bit D/A convert- switch an 11-bit R-2R ladder structure. The output voltage
ers, each with an output buffer amplifier. The part also contains from this converter has the same polarity as the reference
a reference input buffer amplifier for each DAC, and an on-chip voltage, REF IN.
3 V reference. The REF IN voltage is internally buffered by a unity gain
D/A Section amplifier before being applied to the D/A converters and the
The AD7242/AD7244 contains two 12-bit/14-bit voltage mode bipolar bias circuitry. The D/A converter is configured and
D/A converters, each consisting of highly stable thin-film resistors scaled for a 3 V reference, and the device is tested with 3 V
and high speed single-pole, double-throw switches. The simplified applied to REF IN. Operating the AD7242/AD7244 at refer-
circuit diagram for the DAC section is shown in Figure 1. The ence voltages outside the ± 5% tolerance range may result in
three MSBs of the data word are decoded to drive the seven degraded performance from the part.
switches A-G. On the AD7242, the 9 LSBs switch a

Figure 1. DAC Ladder Structure

Internal Reference
The on-chip reference is a temperature-compensated buried
Zener reference that is factory trimmed for 3 V ± 10 mV. The
reference can be used to provide both the reference voltage for
the two D/A converters and the bipolar biasing circuitry. This is
achieved by connecting REF OUT to REF INA and REF INB.
The reference voltage can also be used for other components
and is capable of providing up to 500 μA to an external load.
The maximum recommended capacitance on the reference
output pin for normal operation is 50 pF. If the reference
Figure 2. Circuit Connection for REF OUT with an External
output is required to drive a capacitive load greater than 50 pF,
Capacitive Load of Greater Than 50 pF
a 200 Ω resistor should be placed in series with the capacitive
load. Decoupling the REF OUT pin with a series 200 Ω resistor
and a parallel combination of a 10 μF tantalum capacitor and a
0.1 μF ceramic capacitor as in Figure 2 reduces the noise
spectral density of the reference (see Figure 4). Using this
decoupling scheme to generate the reference voltage for REF
INA and REF INB gives a channel-to-channel isolation number
of 110 dB (connecting REF OUT directly to REF INA and
REF INB gives 80 dB). The channel-to-channel isolation is 110
dB using an external reference.
External Reference
In some applications, the user may require a system reference or
some other external reference to drive the AD7242/AD7244
reference inputs. Figure 3 shows how the AD586 reference can
be conditioned to provide the 3 V reference required by the
AD7242/AD7244 reference inputs.

Figure 3. AD586 Driving AD7242/AD7244 Reference Inputs

–6– REV. B
 AD7244
Output Amplifier For the AD7242, the output voltage can be expressed in terms
The outputs from each of the voltage-mode DACs are buffered of the input code, N, using the following relationship:
by a noninverting amplifier. The buffer amplifier is capable of
developing ± 3 V across a 2 kΩ and 100 pF load to ground, and 2 • N • REF IN
V OUT =
can produce 6 V peak-to-peak sine wave signals to a frequency 4096
of 20 kHz. The output is updated on the falling edge of the where –2048 ≤ N ≤ +2047
respective LDAC input. The output voltage settling time, to
For the AD7244, the output voltage can be expressed in terms
within 1/2 LSB of its final value, is typically less than 2 μs for
of the input code, N, using the following relationship:
the AD7242 and 2.5 μs for the AD7244.
2 • N • REF IN
The small signal (200 mV p-p) bandwidth of the output buffer V OUT =
amplifier is typically 1 MHz. The output noise from the 16384
amplifier is low, with a figure of 30 nV/√Hz at a frequency of where –8192 ≤ N ≤ +8191
1 kHz. The broadband noise from the amplifier exhibits a
typical peak-to-peak figure of 150 μV for a 1 MHz output Table I. AD7242 Ideal Input/Output Code Table Code
bandwidth. Figure 4 shows a typical plot of noise spectral DAC Latch Contents
density versus frequency for the output buffer amplifier and for MSB LSB Analog Output, VOUT*
the on-chip reference (including and excluding the decoupling
components). 01 11 1111 1111 +2.998535 V
01 11 1111 1110 +2.99707 V
00 00 0000 0001 +0.001465 V
00 00 0000 0000 0V
11 11 1111 1111 –0.001465 V
10 00 0000 0001 –2.998535 V
10 00 0000 0000 –3 V
*Assuming REF IN = +3 V.

Table II. AD7244 Ideal Input/Output Code Table Code

DAC Latch Contents

MSB LSB Analog Output, VOUT*
01 1111 1111 1111 +2.999634 V
01 1111 1111 1110 +2.99268 V
00 0000 0000 0001 +0.000366 V
Figure 4. Noise Spectral Density vs. Frequency 00 0000 0000 0000 0V
11 1111 1111 1111 –0.000366 V
TRANSFER FUNCTION 10 0000 0000 0001 –2.999634 V
The basic circuit configuration for the AD7242/AD7244 is 10 0000 0000 0000 –3 V
shown in Figure 5. Table I and Table II show the ideal input
code to output voltage relationship for the AD7242 and *Assuming REF IN = +3 V.
AD7244 respectively. Input coding for the AD7242/AD7244 is
2s complement.

Figure 5. Basic Connection Diagram

REV. B –7–
AD7244
TIMING AND CONTROL timing diagram for operation of either of the two serial input
Communication with the AD7242/AD7244 is via six serial logic ports on the part.
inputs. These consist of separate serial clocks, word framing and Although 16 bits of data are clocked into the input latch, only
data lines for each DAC. DAC updating is controlled by two 12 bits are transferred into the DAC latch for the AD7242 and
digital inputs: LDACA for updating VOUTA and LDACB for 14 bits are transferred for the AD7244. Therefore, 4 bits in the
updating VOUTB. These inputs can be asserted independently of AD7242 data stream and 2 bits in the AD7244 data stream are
the microprocessor by an external timer when precise updating don’t cares since their value does not affect the DAC latch data.
intervals are required. Alternatively, the LDACA and LDACB The bit positions are the don’t cares followed by the DAC data
inputs can be driven from a decoded address bus allowing the starting with the MSB (see Figure 6).
microprocessor control over DAC updating as well as data
communication to the AD7242/AD7244 input latches. The respective LDAC signals control the transfer of data to the
respective DAC latches. Normally, data is loaded to the DAC
The AD7242/AD7244 contains two latches per DAC, an input latch on the falling edge of LDAC. However, if LDAC is held
latch and a DAC latch. Data must be loaded to the input latch low, serial data is loaded to the DAC latch on the sixteenth
under the control of TCLKA, TFSA and DTA for input Latch falling edge of TCLK. If LDAC goes low during the loading of
A and TCLKB, TFSB and DTB for input Latch B. Data is then serial data to the input latch, no DAC latch update takes place
transferred from input Latch A to DAC Latch A under the control on the falling edge of LDAC. If LDAC stays low until the serial
of the LDACA signal, while LDACB controls the loading of DAC transfer is completed, then the update takes place on the sixteenth
Latch B from input Latch B. Only the data held in the DAC falling edge of TCLK. If LDAC returns high before the serial
latches determines the analog outputs of the AD7242/AD7244. data transfer is completed, no DAC latch update takes place.
Data is loaded to the input latches under control of the respec- If seventeen or more TCLK edges occur while TFS is low, the
tive TCLK, TFS and DT signals. The AD7242/AD7244 seventeenth (and beyond) clock edges are ignored, i.e., no
expects a 16-bit stream of serial data on its DT inputs. Data further data is clocked into the input latch after the sixteenth
must be valid on the falling edge of TCLK. The TFS input TCLK edge following a falling edge on TFS.
provides the frame synchronization signal that tells the AD7242/
AD7244 that valid serial data will be available on the DT input
for the next 16 falling edges of TCLK. Figure 6 shows the

Figure 6. AD7242/AD7244 Timing Diagram

–8– REV. B
 AD7244
MICROPROCESSOR INTERFACING control or address line of the ADSP-2101/ADSP-2102 could be
Microprocessor interfacing to the AD7242/AD7244 is via a used to drive these inputs. Alternatively, the LDACA and
serial bus that uses standard protocol compatible with DSP LDACB inputs of the AD7242/AD7244 could be hardwired
processors and microcontrollers. The communication interface low; in this case the update of the DAC latches and analog
consists of a separate transmit section for each of the DACs. outputs takes place on the 16th falling edge of SCLK (after the
Each section has a clock signal, a data signal and a frame or respective TFS signal goes low).
strobe pulse. AD7242/AD7244 to DSP56000 Interface
Figures 7 through 11 show the AD7242/AD7244 configured A serial interface between the AD7242/AD7244 and the
for interfacing to a number of popular DSP processors and DSP56000 is shown in Figure 8. The DSP56000 is configured
microcontrollers. for normal mode, asynchronous operation with gated clock. It is
AD7242/AD7244 to ADSP-2101/ADSP-2102 Interface also set up for a 16-bit word with SCK and SC2 as outputs and
Figure 7 shows a serial interface between the AD7242/AD7244 the FSL control bit set to a 0. SCK is internally generated on
and the ADSP-2101/ADSP-2102 DSP processor. The ADSP- the DSP56000 and applied to both the TCLKA and TCLKB
2101/ADSP-2102 has two serial ports and, in the interface inputs of the AD7242/AD7244. Data from the DSP56000 is
shown, both serial ports are used, one for each DAC. Both serial valid on the falling edge of SCK. The serial data line, STD
ports do not have to be used; in the case where only one serial drives the DTA and DTB serial input data lines of the
port is used, an extra line (DACA/DACB as shown in the other AD7242/AD7244.
serial interfaces) would have to decode the one TFS line to The SC2 output provides the framing pulse for valid data. This
provide TFSA and TFSB lines for the AD7242/AD7244. is an active high output and is gated with a DACA/DACB
control line before being applied to the TFSA and TFSB inputs
of the AD7242/AD7244. The DACA/DACB line determines
which DAC serial data is to be transferred to, i.e., which TFS
line is active when SC2 is active.
As in the previous interface, a common LDAC input is shown
driving the LDACA and LDACB inputs of the AD7242/AD7244.
Once again, these LDAC inputs could be hardwired low, in
which case VOUTA or VOUTB will be updated on the sixteenth
falling edge of SCK after the TFSA or TFSB input goes low.

Figure 7. AD7242/AD7244 to ADSP-2101/ADSP-2102

Interface
The three serial lines of the first serial port, SPORT1, of the
ADSP-2101/ADSP-2102 connect directly to the three serial
input lines of DACA of the AD7242/AD7244. The three serial
lines of SPORT2 connect directly to the three serial lines on the
DACB serial input port. Data from the ADSP-2101/ADSP-2102 is
valid on the falling edge of SCLK. A common LDAC signal is
used to drive the LDACA and LDACB inputs. This is shown to Figure 8. AD7242/AD7244 to DSP56000 Interface
be generated from a timer or clock recovery circuit but another

REV. B –9–
AD7244
AD7242/AD7244 to TMS320C25 Interface output of one of the DACs will be updated on the sixteenth
Figure 9 shows a serial interface between the AD7242/AD7244 falling edge of TXD after the respective TFS signal for that
and the TMS320C25 DSP processor. In this interface, the DAC has gone low. Alternatively, the scheme used in previous
CLKX and FSX signals of the TMS320C25 are generated from interfaces, whereby the LDAC inputs are driven from a timer,
the clock/timer circuitry. The FSX pin of the TMS320C25 can be used.
must be configured as an input. CLKX is used to provide both
the TCLKA and TCLKB inputs of the AD7242/AD7244. DX
of the TMS320C25 is also routed to the serial data line of each
input port of the AD7242/AD7244.
Data from the TMS32020 is valid on the falling edge of CLKX
after FSX goes low. This FSX signal is gated with the DACA/
DACB control line to determine whether TFSA or TFSB goes
low when FSX goes low.
The clock/timer circuitry also generates the LDAC signal for the
AD7242/AD7244 to synchronize the update of the outputs with
the serial transmission. As in the previous interface diagrams, a
common LDAC input is shown driving the LDACA and
LDACB inputs of the AD7242/AD7244. Once again, these
LDAC inputs could be hardwired low, in which case VOUTA or
Figure 10. AD7242/AD7244 to 87C51 Interface
VOUTB will be updated on the sixteenth falling edge of CLKX
after the TFSA or TFSB input goes low. AD7242/AD7244 to 68HC11 Interface
Figure 11 shows a serial interface between the AD7242/AD7244
and the 68HC11 microcontroller. SCK of the 68HC11 drives
TCLKA and TCLKB of the AD7242/AD7244 while the MOSI
output drives the two serial data lines of the AD7242/AD7244.
The TFSA and TFSB signals are derived from PC6 and PC7,
respectively.
For correct operation of this interface, the 68HC11 should be
configured such that its CPOL bit is a 0 and its CPHA bit is a 1.
When data is to be transmitted to the part, PC6 (for DACA) or
PC7 (for DACB) is taken low. When the 68HC11 is configured
like this, data on MOSI is valid on the falling edge of SCK. The
68HCll transmits its serial data in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. To load data
to the AD7242/AD7244, PC6 (for DACA) or PC7 (for DACB)
is left low after the first eight bits are transferred and a second
Figure 9. AD7242/AD7244 to TMS320C25 Interface byte of data is then serially transferred to the AD7242/AD7244.
When the second serial transfer is complete, the PC6 line (for
AD7242/AD7244 to 87C51 Interface
DACA) or the PC7 line (for DACB) is taken high.
A serial interface between the AD7242/AD7244 and the 87C51
microcontroller is shown in Figure 10. TXD of the 87C51
drives TCLKA and TCLKB of the AD7242/AD7244 while
RXD drives the two serial data lines of the part. The TFSA and
TFSB signals are derived from P3.2 and P3.3, respectively.
The 87C51 provides the LSB of its SBUF register as the first bit
in the serial data stream. Therefore, the user will have to ensure
that the data in the SBUF register is correctly arranged so the
don’t care bits are the first to be transmitted to the AD7242/
AD7244; the last bit to be sent is the LSB of the word to be
loaded to the AD7242/AD7244. When data is to be transmitted
to the part, P3.2 (for DACA) or P3.3 (for DACB) is taken low.
Data on RXD is valid on the falling edge of TXD. The 87C51
transmits its serial data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. To load data to the Figure 11. AD7242/AD7244 to 68HC11 Interface
AD7242/AD7244, P3.2 (for DACA) or P3.3 (for DACB) is left
Figure 11 shows both LDAC inputs of the AD7242/AD7244
low after the first eight bits are transferred and a second byte of
hardwired low. As a result, the DAC latch and the analog
data is then serially transferred to the AD7242/AD7244. When
output of one of the DACs will be updated on the sixteenth
the second serial transfer is complete, the P3.2 line (for DACA)
falling edge of SCK after the respective TFS signal for that
or the P3.3 line (for DACB) is taken high.
DAC has gone low. Alternatively, the scheme used in previous
Figure 10 shows both LDAC inputs of the AD7242/AD7244 interfaces, whereby the LDAC inputs are driven from a timer,
hardwired low. As a result, the DAC latch and the analog can be used.
–10– REV. B
 AD7244
APPLYING THE AD7242/AD7244 Low impedance analog and digital power supply common
Good printed circuit board layout is as important as the overall returns are essential to low noise operation of high performance
circuit design itself in achieving high speed converter perfor- converters. Therefore, the foil width for these tracks should be
mance. The AD7242 works on an LSB size of 1.465 mV, while kept as wide as possible. The use of ground planes minimizes
the AD7244 works on an LSB size of 366 μV. Therefore, the impedance paths and also guards the analog circuitry from
designer must be conscious of minimizing noise in both the digital noise.
converter itself and in the surrounding circuitry. Switching
mode power supplies are not recommended as the switching NOISE
spikes can feed through to the on-chip amplifier. Other causes Keep the signal leads on the VOUTA and VOUTB signals and the
of concern are ground loops and digital feedthrough from signal return leads to AGND as short as possible to minimize
microprocessors. These are factors that influence any high noise coupling. In applications where this is not possible, use a
performance converter, and a proper PCB layout that minimizes shielded cable between the DAC outputs and their destination.
these effects is essential for best performance. Reduce the ground circuit impedance as much as possible since
any potential difference in grounds between the DAC and its
LAYOUT HINTS destination device appears as an error voltage in series with the
Ensure that the layout for the printed circuit board has separated DAC output.
digital and analog lines as much as possible. Take care not to
run any digital track alongside an analog signal track. Establish a
single point analog ground (star ground) separate from the logic
system ground. Place this star ground as close as possible to the
AD7242/AD7244. Connect all analog grounds to this star
ground and also connect the AD7242/AD7244 DGND pins to
this ground. Do not connect any other digital grounds to this
analog ground point.

REV. B –11–
AD7244

OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)

24 13 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
12
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC
0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38)0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING 0.010 (0.25)
PLANE
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

071006-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 12. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters)

0.005 (0.13) 0.098 (2.49)

MIN MAX 0.310 (7.87)
24 13 0.220 (5.59)

1 12
PIN 1
0.060 (1.52)
0.200 (5.08) 0.320 (8.13)
1.280 (32.51) MAX 0.015 (0.38)
MAX 0.290 (7.37)
0.150 (3.81)
MIN
0.015 (0.38)
0.200 (5.08) 15° 0.008 (0.20)
0.125 (3.18) 0.100 0.070 (1.78) SEATING 0°
0.023 (0.58)
(2.54) 0.030 (0.76) PLANE
BSC
0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

100808-A

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 13. 24-Lead Ceramic Dual In-Line Package [CERDIP]

Narrow Body
(Q-24-1)
Dimensions shown in inches and (millimeters)

Rev. B | Page 12
 AD7244
18.10 (0.7126)
17.70 (0.6969)

28 15
7.60 (0.2992)
7.40 (0.2913)

1 10.65 (0.4193)
14
10.00 (0.3937)

0.75 (0.0295)
45°
2.65 (0.1043) 0.25 (0.0098)
0.30 (0.0118) 2.35 (0.0925)
8°
0.10 (0.0039) 0°
COPLANARITY
0.10 1.27 (0.0500) 0.51 (0.0201) SEATING 1.27 (0.0500)
PLANE 0.33 (0.0130)
BSC 0.31 (0.0122) 0.40 (0.0157)
0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AE

06-07-2006-A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 14. 28-Lead Standard Small Outline Package [SOIC_W]

Wide Body
(RW-28)
Dimensions shown in millimeters and (inches)

ORDERING GUIDE
Model1 Temperature Range Integral Nonlinearity Package Description Package Options
AD7244JNZ –40°C to +85°C ±2 LSB max 24-Lead PDIP N-24-1
AD7244JR –40°C to +85°C ±2 LSB max 28-Lead SOIC_W RW-28
AD7244AQ –40°C to +85°C ±2 LSB max 24-Lead CERDIP Q-24-1
AD7244JRZ –40°C to +85°C ±2 LSB max 28-Lead SOIC_W RW-28
AD7244JRZ-REEL –40°C to +85°C ±2 LSB max 28-Lead SOIC_W RW-28
1
Z = RoHS Compliant Part.

REVISION HISTORY
4/15—Rev. A to Rev. B
Added AD7242 Obsolete Note ....................................................... 1
Updated Outline Dimensions ....................................................... 12
Changes to Ordering Guide .......................................................... 13

©2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D01421-0-4/15(B)

Rev. B | Page 13