RISC-V

System-on-Chip Design
Harris, Stine, Thompson & Harris

Chapters 2:
RISC-V Introduction
Chapter 2 :: Topics
RISC-V Introduction
2.1 RISC-V Assembly Language
2.2 RISC-V Machine Language
2.3 Have a Hart
2.4 Memory Map
2.5 RISC-V Extensions & Profiles
2.6 Comparison with other Architectures
2.7 RISC-V Microarchitecture
2.8 Wally SoC
2.9 RISC-V Market

2 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

RISC-V Intro
RISC-V
!"#" &%%&
• Developed by Krste Asanovic, Andrew
!"$% '(')!!
Waterman, Yunsup Lee, David Patterson
!"$$ +HH-.I00
and their colleagues at UC Berkeley in
2010. !"*! 012I'3
!"*4)I
5063
• First widely accepted open-source !"*#
+-H78I
computer architecture !""4
4!%#&
!""9 '.:;<=>
• Called RISC-V (pronounced “risk five”) !""&) 2?@I
because it was the 5th generation RISC 4%%# A8BC

processor developed at Berkeley 4%%# 3MB.

4%!% 5063)E

4 RISC-V System-on-Chip Design Chapter 2 RISC-V

Kriste Asanovic
• Professor of Computer
Science at the University of
California, Berkeley
• Began developing RISC-V
during summer 2010
• Chairman of the Board of
RISC-V International, RISC-V’s
governing board
• Co-Founder of SiFive, a
company that commercializes
and develops supporting Photo used with permission.

tools for RISC-V

5 RISC-V System-on-Chip Design Chapter 2 RISC-V
Andrew Waterman
• Weary of existing instruction
set architectures (ISAs), he
co-designed the RISC-V
architecture and the first
RISC-V cores
• Co-founded SiFive with Krste
Asanovic
• Earned his PhD in computer
science from UC Berkeley in
Photo used with permission.
2016

6 RISC-V System-on-Chip Design Chapter 2 RISC-V

Forecast RISC-V Market Growth
12 billion RISC-V cores
have shipped by 2022

“RISC-V is envitable”
– Krste Asanovic

7 RISC-V System-on-Chip Design Chapter 2 RISC-V

 RISC-V ISA
• Officially defined at:
https://riscv.org/specifications/ratified/
• Base ISAs: RV128I and RV32E
– RV32I (XLEN = 32) (embedded) are also
– RV64I (XLEN = 64) in development
• Extensions:
– A: Atomic memory accesses
– C: Compressed instructions
– F, D: Float/double precision
– M: Integer multiply/divide
– G: IACFDM
RISC-V International: the
• Applications processors: governing organization and
– Run multitasking OS with graphical user interface community for developing
– Typically RV64GC RISC-V technical
• Embedded processors: specifications (riscv.org)
– Execute smaller operations, including driving
motors, flashing LEDs, etc.
– Typically RV32IC

8 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

Assembly Language
RISC-V Assembly Language
• RV32I:
– Integer operations
– 40 instructions
• RV64I adds instructions:
– For 64-bit (double-word) loads/stores
– To operate on bottom 32 bits of 64-bit register

See inside cover of textbook for list of RISC-V instructions.

10 RISC-V System-on-Chip Design Chapter 2 RISC-V

RV32I: Integer Instructions
• R-Type (Register-Type): Register operands only
• I-Type (Immediate-Type): Immediate & register operands
• S-Type (Store-Type): Stores
• B-Type (Branch-Type): Branches
• J-Type (Jump-Type): Jump
• U-Type (Upper-Imm.-Type): Upper-immediate operand

All RV32I instructions are also part of RV64I. These

instructions operate on XLEN-bit operands.

11 RISC-V System-on-Chip Design Chapter 2 RISC-V

 R-Type Instructions
Register-Type Instructions:
– Arithmetic: add, sub
– Logical: and, or, xor
– Shift: sll, srl, sra (shift left/right logical/arithmetic)
– Comparison: slt, sltu (set if less than/unsigned)
• sltu (set if less than unsigned) compares the operands as if they’re
unsigned. slt treats them as signed (2’s complement)
Examples:
add s0, s1, s2 # s0 = s1 + s2
or t0, t1, t2 # t0 = t1 | t2

12 RISC-V System-on-Chip Design Chapter 2 RISC-V

 I-Type Instructions
Immediate-Type Instructions:
– Arithmetic: addi • The processor sign-
extends the immediate
– Logical: andi, ori, xori before using it in all
– Shift: slli, srli, srai operations except shifts.
• So, the immediate is sign-
– Comparison: slti, sltiu extended for logical
– Loads: lw, lh, lb, lhu, lbu operations and before
treating it as an unsigned
– Jumps: jalr
number in sltiu.
Examples:
addi s0, s1, -15 # s0 = s1 - 15
xori t2, t3, -1 # t2 = t3 ^ 0xFFFFFFFF
slli t0, t1, 7 # t0 = t1 << 7
lw t0, 0x24(s3) # t0 = memory[s3 + 0x24]
jalr s5 # PC = s5, ra = PC + 4

13 RISC-V System-on-Chip Design Chapter 2 RISC-V

 S-Type Instructions
Store-Type Instructions:
– sw, sh, sb
– Store word, half, byte
Examples:
sw s0, 0x2c(t1) # memory[t1 + 0x2c] = s0
sh t1, 0x30(s2) # memory[s2 + 0x30]15:0 = t115:0
sb t3, 0x8c(s7) # memory[s7 + 0x8c]7:0 = t37:0

14 RISC-V System-on-Chip Design Chapter 2 RISC-V

 B-Type Instructions
Branch-Type Instructions:
– Branch if equal: beq
– Branch if not equal: bne
– Branch if less than: blt
– Branch if greater than or equal: bge
– Branch if less than (unsigned): bltu
– Branch if greater than or equal (unsigned): bgeu

Examples:
beq s0, s1, L1 # if (s0 == s1), goto L1
blt t0, t1, L3 # if (t0 < t1), goto L3

15 RISC-V System-on-Chip Design Chapter 2 RISC-V

 J-Type Instruction
Jump-Type Instruction:
– Jump and Link: jal
Example:
jal L1 # ra = PC + 4, goto L1
jal s3, L7 # s3 = PC + 4, goto L7

16 RISC-V System-on-Chip Design Chapter 2 RISC-V

 U-Type Instructions
Upper-Immediate-Type Instructions:
– Load upper-immediate: lui
– Add upper-immediate to PC: auipc
Examples:
# Load 20-bit immediate into upper bits, lower bits are 0s
lui t1, 0xABCDE # t1 = 0xABCDE000
# Load a 32-bit immediate (0xBBCCD123) into a register
lui s3, 0xBBCCD # s3 = 0xBBCCD000
addi s3, s3, 0x123 # s3 = 0xBBCCD000+0x123 = 0xBBCCD123
# Load a 32-bit immediate (0x12345ABC) into a register
lui s1, 0x12346 # s1 = 0x12346000
addi s1, s1, 0x123 # s1 = 0x12346000+0xFFFFFABC = 0x12345ABC
# Move PC (+ upper-immediate) into a register
auipc s5, 0 # s5 = PC
auipc s11, 0xAABBC # s11 = PC + {0xAABBC, 12’b0}

17 RISC-V System-on-Chip Design Chapter 2 RISC-V

RV64I: Additional Instructions
• Load and store double-words (64-bit word): ld, sd
• Load word unsigned: lwu
• 32-bit (word) operations in 64-bit registers:
addw, subw, sllw, srlw, sraw
– Immediate versions: addiw, slliw, srliw, sraiw

RV64I word operations operate on the lower 32 bits of a

register, discard the upper 32 bits and sign-extend the
result into the upper bits of the register. This is important
to support 32-bit int data types efficiently on a 64-bit
processor for languages such as C.

18 RISC-V System-on-Chip Design Chapter 2 RISC-V

RV64I Word Operations
Example: addw s0, s1, s2
s1 and s2 should be treated as 32-bit operands (in lower half of register).
Suppose:
s1 = s2 = 0xFFFF_FFFF_8000_0000
Performed on 32-bit ALU:
0x8000_0000 + 0x8000_0000 = 0x0000_0000
Performed on 64-bit ALU (numbers are sign-extended):
0xFFFF_FFFF_8000_0000 + 0xFFFF_FFFF_8000_0000 =
0xFFFF_FFFF_0000_0000
But the result should be 0 for a 32-bit operation. So,
• Discard upper 32 bits: 0xFFFF_FFFF_0000_0000
• Sign-extend to 64 bits: 0x0000_0000_0000_0000

19 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: Introduction

Registers &
Conventions
RISC-V Register
Name Register Number Usage
zero x0 Constant value 0
ra x1 Return address
sp x2 Stack pointer
gp x3 Global pointer
tp x4 Thread pointer
t0-2 x5-7 Temporaries
s0/fp x8 Saved register / Frame pointer
s1 x9 Saved register
a0-1 x10-11 Function arguments / return values
a2-7 x12-17 Function arguments
s2-11 x18-27 Saved registers
t3-6 x28-31 Temporaries

21 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Register Naming & Conventions
• Registers:
– Can use either name (i.e., ra, zero) or x0, x1, etc.
– Using name is preferred
• Registers used for specific purposes:
• zero: always holds the constant value 0.
• s0-s11: the saved registers, used to hold variables
• t0-t6: the temporary registers, used to hold
intermediate values during a larger computation
• ra: return address register
• sp: stack pointer (address of top of stack)
• a0-a7: argument registers
• a0: also the return register

22 RISC-V System-on-Chip Design Chapter 2 RISC-V

 RV32E
• Register file is the biggest part of a simple
embedded RV32I core
• RV32E reduces register file to only 16 regs
• x0-x15
• Still includes t0-t2, s0-s1, a0-a5
• And all the special purpose registers

23 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Endianness
• How bytes are numbered (addressed) within a
word in memory:
• Big-endian: Address numbers start at the big end (MSB)
and increase toward the LSB.
• Little-endian: Address numbers start at the LSB and
increase toward the MSB.
#,-.LME,1M B&'E A,223*.LME,1M
)EE'*++
#42*5)EE'*++*+

#42*5)EE'*++*+
77 88 99 AA 77 88 99 AA
C D E F C F E D C
12 34 F0 E0 12 34 F0 E0
8 9 A B 8 B A 9 8
FF EE DD CC FF EE DD CC
4 5 6 7 4 7 6 5 4
AB CD EF 00 AB CD EF 00
0 1 2 3 0 3 2 1 0
!"# A"# !"# A"#
24 RISC-V System-on-Chip Design Chapter 2 RISC-V
Big-Endian & Little-Endian Example
• Suppose 0x23456789 is stored at address 0x3C.
• What value is in s0 after this instruction executes in a
big-endian system? lb s0, 0x3D(zero)
• In a little-endian system?

25 RISC-V System-on-Chip Design Chapter 2 RISC-V

Big-Endian & Little-Endian Example
• Suppose 0x56789ABC is stored at address 0x3C.
• What value is in s0 after this instruction executes in a
big-endian system? lb s0, 0x3D(zero)
• In a little-endian system?
Big-endian: Little-endian:
s0 = 0x00000078 s0 = 0xFFFFFF9A
B345FSM37S 83VVW15FSM37S
-.LM
B;V1<AMML122 DC DE DF D* AMML122 D* DF DE DC B;V1<AMML122
E7V7<=7W>1 !" !" #A BC DC !" +, #A BC E7V7<=7W>1
?@B 8@B ?@B 8@B

Remember that lb sign-extends the byte.

26 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Chapter 1: Introduction

Pseudoinstructions
Pseudoinstructions
• Pseudoinstructions: instructions that are
convenient for the programmer that can be
implemented with existing RISC-V instructions.
• Assembler converts them to real RISC-V instructions.

28 RISC-V System-on-Chip Design Chapter 2 RISC-V

Some RISC-V Pseudoinstructions
Pseudoinstruction RISC-V Instructions
j label jal zero, label
jal label jal ra, label
jr ra jalr zero, ra, 0
mv t5, s3 addi t5, s3, 0
not s7, t2 xori s7, t2, -1
nop addi zero, zero, 0
li s8, 0x56789DEF lui s8, 0x5678A
addi s8, s8, 0xDEF
bgt s1, t3, L3 blt t3, s1, L3
bgez t2, L7 bge t2, zero, L7
call L1 auipc ra, imm31:12
jalr ra, ra, imm11:0
ret jalr zero, ra, 0
See inside covers for more pseudoinstructions.
29 RISC-V System-on-Chip Design Chapter 2 RISC-V
Chapter 1: RISC-V Introduction

C to Assembly
Examples
C to Assembly Examples: Variables
• For the following programs, assume these variables
have been declared and are kept in these registers:
int a, b, c; // in s0, s1, s2, respectively
int i, j; // in s3, s4
int grades[100]; // base address in s5
char name[80]; // base address in s6

31 RISC-V System-on-Chip Design Chapter 2 RISC-V

Simple Operations
C Code RISC-V Assembly Code
a = b + c; add s0, s1, s2 # a = b + c

a = b & 0xFF; andi s0, s1, 0xFF # 0xFF = 8 1s

32 RISC-V System-on-Chip Design Chapter 2 RISC-V

Conditional Statements: if, if/else
C Code RISC-V Assembly Code
if (i == j) bne s3, s4, done # skip if i != j
a = 1; li s0, 1 # a = 1
done:

if (i == j) bne s3, s4, else # skip if i != j

a = 1; li s0, 1 # a = 1
j done
else else:
a = 2; li s0, 2 # a = 2
done:

The C code checks (i == j) and the assembly code checks

the opposite condition (i != j, using bne).

33 RISC-V System-on-Chip Design Chapter 2 RISC-V

Loop: while
C Code RISC-V Assembly Code
a = 0; li s0, 0 # a = 0
i = 0; li s3, 0 # i = 0
li t0, 10 # need 10 for compare
while (i <= 10){ while:
bgt s3, t0, done # done if i > 10
a = a + i; add s0, s0, s3 # a = a + i
i = i + 2; addi s3, s3, 2 # i = i + 2
} j while # repeat while loop
done:

34 RISC-V System-on-Chip Design Chapter 2 RISC-V

Loop: for
C Code RISC-V Assembly Code
a = 1; li s0, 1 # a = 1
li s3, 1 # i = 1
for (i=1; i<=b; i++) for:
bgt s3, s1, done # done if i > b
a = a * 2; slli s0, s0, 1 # a = a * 2
addi s3, s3, 1 # i++
j for # repeat for loop
done:

35 RISC-V System-on-Chip Design Chapter 2 RISC-V

Arrays Example 1
C Code RISC-V Assembly Code
grades[1] = grades[0] + 17; # t0 = grades[0]
lw t0, 0(s5)

# t0 = t0 + 17
addi t0, t0, 17

# grades[1] = t0
sw t0, 4(s5)

36 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Arrays Example 2
C Code RISC-V Assembly Code
li s3, 0 # i = 0
li t0, 100 # t0 = 100 for <
for (i=0; i<100; i++) for:
bge s3, t0, done # t0 >= 100? done
slli t1, s3, 2 # t1 = i*4
grades[i]=grades[i]+14; add t1, s5, t1 # t1 = &grades[i]
lw t2, 0(t1) # t2 = grades[i]
addi t2, t2, 14 # grades[i] += 14
sw t2, 0(t1) # grades[i] = t2
addi s3, s3, 1 # i++
j for # repeat
done:

37 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Arrays Example 3: String Handling
C Code RISC-V Assembly Code
i = 0; li s3, 0
while (name[i]) while: add t0, s6, s3
i++; lb t1, 0(t0)
beq t1, zero, done
addi s3, s3, 1
j while
done:

38 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Function Call: Factorial
C Code RISC-V Assembly Code
// s0 = result fact: addi sp, sp, -8 # room on stack
// s1 = i sw s0, 0(sp) # save s0
int fact(int n) { sw s1, 4(sp) # save s1
int result = 1; li s0, 1 # result = 1
int i; li s1, 1 # i = 1
for (i=1; i<=n; i++) for: bgt s1, a0, done # i > n?
result = result*i; mul s0, s0, s1 # result *= i
addi s1, s1, 1 # i++
j for # repeat
return result; done: mov a0, s0 # return result
} lw s1, 4(sp) # restore s1
lw s0, 0(sp) # restore s0
addi sp, sp, 8 # restore stack
ret # return

39 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Recursive Function Call: Factorial
C Code RISC-V Assembly Code
int factr(int n) { factr: li t0, 1 # for compare
if (n<=1) bgt a0, t0, else # n > 1
return 1; li a0, 1 # return 1
ret # return
else else: addi sp, sp, -8 # room on stack
sw ra, 0(sp) # save ra
sw a0, 4(sp) # save n
addi a0, a0, -1 # n-1
return n*factr(n-1); jal factr # factr(n-1)
} lw t0, 4(sp) # restore n
lw ra, 0(sp) # restore ra
addi sp, sp, 8 # restore stack
mul a0, t0, a0 # n*factr(n-1)
ret

40 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

RISC-V Machine
Language
RISC-V Instruction Formats
&./0%( 1./0%( 1./0%( 2./0%( 1./0%( &./0%(
!"#$%& '() '(* !"#$%2 '+ ,- !"#$B&
033**45 '(* !"#$%2 '+ ,- '"#$B&
033**41 '() '(* !"#$%2 033645 ,- ("#$B&
033*)7*541 '() '(* !"#$%2 03364*7** ,- )"#$B&
0332*4*) '+ ,- *"#$B&
033)57*54*7**7*84*) '+ ,- +"#$B&
)5./0%( 1./0%( &./0%(

42 RISC-V System-on-Chip Design Chapter 2 RISC-V

RISC-V Instruction Fields
• Operands:
– rs1, rs2: Source registers
– rd: Destination register
– imm: 12-, 13-, 21-, or 32-bit immediate
• Control fields – indicate what operation to perform:
– op: 7-bit operation code or opcode
– funct7, funct3: 7- and 3-bit function

43 RISC-V System-on-Chip Design Chapter 2 RISC-V

RISC-V Instruction Fields
When present in an instruction format, all fields (except imm)
are located in same instruction bits:
– op: Bits 6:0
– rs2, rs1, rd: Bits 24:20, 19:15, 11:7
– funct7, funct3: Bits 31:25, 14:12
!"#$%&
31:25 24:20 19:15 14:12 11:7 6:0
!"#$%& '() '(* !"#$%2 '+ ,-
&./0%( 1./0%( 1./0%( 2./0%( 1./0%( &./0%(

I!"#$%
31:20 19:15 14:12 11:7 6:0
!""##$% &'# 2345.0 &( )*
#+,-!.' /,-!.' 0,-!.' /,-!.' 1,-!.'

44 RISC-V System-on-Chip Design Chapter 2 RISC-V

 RISC-V Immediate Fields
11 10 9 8 7 6 5 4 3 2 1 0 !"$ %&'()* !+ I
I112+-3)2/0-)

11 10 9 8 7 6 5 !"# !"$ %&'()* 4 3 2 1 0 !

12 10 9 8 7 6 5 !"# !"$ %&'()* 4 3 2 1 11 .4 "
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 !+ #
20 10 9 8 7 6 5 4 3 2 1 11 19 18 17 16 15 14 13 12 !+ J
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I'")!&()-.'/0-)

Immediate bit aims to stay in the same instruction bit, but

varying immediate sizes and operands require exceptions.
• I-type: 12-bit signed immediate
• S-type: 12-bit signed immediate
• B-type: 13-bit signed immediate
• U-type: 32-bit upper immediate
• J-type: 21-bit signed immediate
45 RISC-V System-on-Chip Design Chapter 2 RISC-V
 Composition of 32-bit Immediates
11 10 9 8 7 6 5 4 3 2 1 0 !"$ %&'()* !+ I
I112+-3)2/0-)

11 10 9 8 7 6 5 !"# !"$ %&'()* 4 3 2 1 0 !

12 10 9 8 7 6 5 !"# !"$
%&'()* 4 3 2 1 11 .4 "
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 !+ #
20 10 9 8 7 6 5 4 3 2 1 11 19 18 17 16 15 14 13 12 !+ J
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I'")!&()-.'/0-)
%! %&#$' $,#$! $& I
!""#$$' !""#$%&%'
%!
!"#$B&'$E)"*+E$

%&#$' !!#+ * S
!""#$$' !""#$%&%'
%! * %&#$' !!#+ ! (
!""#$(' !""#$$&$'
%! %&#$& !"#!$ ! )
!""#)$&$('
%! !"#!$ $& %&#$' $,#$! ! J
!""#(%' !""#$*&$'
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!II-.$*+E$
46 RISC-V System-on-Chip Design Chapter 2 RISC-V
Assembly to Machine Code
Convert to machine language:
sub x3, x4, x5

Solution: According to Table 1.2, sub is an R-type

instruction with:
• op = 0110011
• funct3 = 000, funct7 = 0100000
• rs1 = 4 = 00100, rs2 = 5 = 00101, rd = 3 = 00011
funct7 rs2 rs1 funct3 rd op
0100000 00101 00100 000 00011 0110011 = 0x405201B3

47 RISC-V System-on-Chip Design Chapter 2 RISC-V

Machine Code to Assembly
Convert to assembly language:
0x03E90523

Solution:
• Write in binary: 0000 0011 1110 1001 0000 0101 0010 0011
• Start with op: tells how to parse rest: 010 0011 = S-type
• Extract fields:
imm11:5 rs2 rs1 funct3 imm4:0 op
0000001 11110 10010 000 01010 0100011
• op = 0100011, funct3 = 00: sb
• rs2 = 11110 (x30), rs1 = 10010 (x18)
• imm = 000000101010 = 42
sb x30, 42(x18)
48 RISC-V System-on-Chip Design Chapter 2 RISC-V
RISC-V Integer Instruction Summary

49 RISC-V System-on-Chip Design Chapter 2 RISC-V

RV64I Additional Instructions

50 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

RISC-V Hart
RISC-V Hart
• A hart is an abstraction of a hardware thread, but
harts may be physical (in hardware), virtual, or
simulated.
• Each hart:
– Has a PC (program counter) and registers
– Executes independently of other harts
• Example: a hart may correspond to a physical core or
an operating system (OS) may time-multiplex many
user-level virtual harts onto a smaller number of
physical harts.

52 RISC-V System-on-Chip Design Chapter 2 RISC-V

Privilege Modes
• 3 privilege modes:
– Machine: M-Mode (highest)
– Supervisor: S-Mode
– User: U-Mode (lowest)
• They offer protection between modes:
– Lower privilege modes have restricted access to
some memory and some control registers
– M-mode has access to all memory and registers

53 RISC-V System-on-Chip Design Chapter 2 RISC-V

Control & Status Registers (CSRs)
• Each privilege mode has a set of CSRs
• CSRs include:
– Address of trap handler
– Flags from a floating-point operation
– Performance counters
– Etc.

54 RISC-V System-on-Chip Design Chapter 2 RISC-V

Processes & Threads
• Process: a running program.
– Operating systems often support multiple processes
running at once.
• Thread: a process is divided up into one or more
threads.
– E.g., a word processor printing, spell-checking, and
allowing text entry at the same time
– Threads share common memory and code space
• Hart: contains architectural state (PC, registers, CSRs)
to run independently/concurrently with other
threads.

55 RISC-V System-on-Chip Design Chapter 2 RISC-V

Cores & Harts
• Core: single processor on one chip. At a minimum, includes:
– Architectural state: PC, Registers, CSRs
– Execution units needed to run a thread
• Multithreaded core: single processor that:
– Contains multiple copies of architectural state to support multiple
threads
– Shares execution units amongst threads
• Multicore processor: on the same chip, contains:
– Multiple cores
– Interconnection network
– Upper-level cache (usually)
• Microprocessor: partitioned into:
– Core: architectural state and execution units
– Uncore: peripherals, shared memory or caches, external interfaces

56 RISC-V System-on-Chip Design Chapter 2 RISC-V

Harts revisited
• Multicore processor:
– Each core is a hart capable of running a separate thread
• Single Multithreaded processor:
– Can switch between threads (architectural state), so acts as multiple
harts
• Example: Multicore processor
– 4 cores
– Each core is 2-way multithreaded
– Thus, has 8 physical harts
• Other cases:
– An OS may time-multiplex multiple virtual harts onto a single physical
hart
– An emulator, such as QEMU, may run RISC-V programs on emulated
harts

57 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Harts: Examples

!"#$%C

,- .! -/.+ !"#$%C'#(F
*#C%+

'()*H,-.%/-#0%C
!"#$%1

,- .! -/.+ !"#$%C'#(F
*#C%+

'()*H,-.%/-#0%1
!"#$%2

,- .! -/.+ !"#$%C'#(F
*#C%+

'()*H,-.%/-#0%2
!"#$%P

,- .! -/.+ !"#$%C'#(F
*#C%+

'()*H,-.%/-#0%P

4 Cores
4 Physical Harts

58 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Harts: Examples
!"#$%C

!" #$ "%#C $'(F*+,(-.

'()*H,-.%/-#0%C /(+*C

!"#$%C !" #$ "%#C

'()*H,-.%/-#0%1
,- .! -/.+ !"#$%C'#(F
*#C%+ !"#$%1

'()*H,-.%/-#0%C !" #$ "%#C $'(F*+,(-.

'()*H,-.%/-#0%2 /(+*C
!"#$%1

,- .! -/.+ !"#$%C'#(F !" #$ "%#C

*#C%+ '()*H,-.%/-#0%P

'()*H,-.%/-#0%1 !"#$%2

!"#$%2 !" #$ "%#C $'(F*+,(-.

'()*H,-.%/-#0%4 /(+*C
,- .! -/.+ !"#$%C'#(F
*#C%+ !" #$ "%#C
'()*H,-.%/-#0%5
'()*H,-.%/-#0%2
!"#$%P
!"#$%P
!" #$ "%#C $'(F*+,(-.
,- .! -/.+ !"#$%C'#(F
'()*H,-.%/-#0%6 /(+*C
*#C%+

'()*H,-.%/-#0%P !" #$ "%#C

'()*H,-.%/-#0%7

4 Cores 4 Multithreaded Cores

4 Physical Harts 8 Physical Harts

59 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Harts: Examples
!"#$%C :$;"#) !"#$%C

!" #$ "%#C $'(F*+,(-. !" #$ "%#C !" #$ "%#C $'(F*+,(-.

'()*H,-.%/-#0%C /(+*C 8H#MV-.%/-#M%C '()*H,-.%/-#M%C /(+*C
!" #$ "%#C
!"#$%C !" #$ "%#C 8H#MV-.%/-#M%N !" #$ "%#C
'()*H,-.%/-#0%1 !" #$ "%#C '()*H,-.%/-#M%N
,- .! -/.+ !"#$%C'#(F
*#C%+ !"#$%1 8H#MV-.%/-#M%2 !"#$%N
!" #$ "%#C
'()*H,-.%/-#0%C !" #$ "%#C $'(F*+,(-. !" #$ "%#C $'(F*+,(-.
8H#MV-.%/-#M%P
'()*H,-.%/-#0%2 /(+*C '()*H,-.%/-#M%2 /(+*C
!"#$%1 !" #$ "%#C
!" #$ "%#C 8H#MV-.%/-#M%4 !" #$ "%#C
,- .! -/.+ !"#$%C'#(F
*#C%+ '()*H,-.%/-#0%P '()*H,-.%/-#M%P
!"#$%2 <%<%< !"#$%2

<%<%<
'()*H,-.%/-#0%1
!"#$%2 !" #$ "%#C $'(F*+,(-. !" #$ "%#C $'(F*+,(-.
'()*H,-.%/-#0%4 /(+*C '()*H,-.%/-#M%4 /(+*C
,- .! -/.+ !"#$%C'#(F
*#C%+ !" #$ "%#C !" #$ "%#C
'()*H,-.%/-#0%5 '()*H,-.%/-#M%5
'()*H,-.%/-#0%2
!"#$%P !"#$%P
!"#$%P
!" #$ "%#C $'(F*+,(-. !" #$ "%#C $'(F*+,(-.
,- .! -/.+ !"#$%C'#(F
'()*H,-.%/-#0%6 /(+*C !" #$ "%#C '()*H,-.%/-#M%6 /(+*C
*#C%+
8H#MV-.%/-#M%=>N
'()*H,-.%/-#0%P !" #$ "%#C !" #$ "%#C
'()*H,-.%/-#0%7 !"#"$%&'()'*+ '()*H,-.%/-#M%7

4 Cores 4 Multithreaded Cores 4 Multithreaded Cores

4 Physical Harts 8 Physical Harts N Virtual Harts mapped to 8
Physical Harts
60 RISC-V System-on-Chip Design Chapter 2 RISC-V
Traps
• Trap: an exception or interrupt
– Exception: illegal instruction, ecall, access to non-existent
memory, etc.
– Interrupt: asynchronous external event, like a button being
pushed or serial port data arriving
• Traps cause a trap handler to execute. Related CSRs:
– mepc: Exception PC = PC of instruction when trap occurred
– mcause: Cause of trap
– mtval: Additional information, if needed
– mtvec: Address of trap handler
– S-mode versions also exist (sepc, scause, stvec, etc.)
• Traps return to program using:
– xret (mret, sret): return to address in xepc

61 RISC-V System-on-Chip Design Chapter 2 RISC-V

Execution Environments
• Purpose: enable lower-level privilege modes to
interact with higher-level privilege modes.
– ABI (application binary interface): an API that enables
application (U-mode) harts to interact with the OS (S-
mode) harts that reside in the application execution
environment.
– SBI (supervisor binary interface): an API that enables OS
(S-mode) harts to interact with M-mode harts that reside
in the supervisor execution environment.

62 RISC-V System-on-Chip Design Chapter 2 RISC-V

Execution Environment
• EEI (execution environment interface, or simply
execution environment) defines:
– Initial state of program
– Number & types of harts (including privilege mode, ISA,
memory map & how traps are handled)
• Example EEIs:
– ABI (application binary interface): defines calling
conventions and data types
– SBI (supervisor binary interface): defines how the OS calls
the underlying platform runtime firmware (e.g., setting the
system timer, starting/stopping/synchronizing cores, etc.)

63 RISC-V System-on-Chip Design Chapter 2 RISC-V

Simple Execution Environment
• Bare metal: simplest execution environment:
– Processor runs in machine mode with no OS
– Physical harts correspond to physical cores (each core has
a single copy of architectural state)
– Programmer has access to all features and memory
– No virtual harts exist
– No protection between harts

64 RISC-V System-on-Chip Design Chapter 2 RISC-V

Linux
• Linux OS – More complex execution environment:
– OS runs in S-mode:
• OS uses an SBI to access platform runtime firmware, which consists
of the supervisor execution environment
– Applications run in U-mode. OS provides each application
with an application execution environment, which defines:
• That application’s virtual memory space
• ABI provides a common set of system calls for applications to make
requests to the kernel to manage processes, memory, and files.
!""#AB&'A(F*+ !""#AB&'A(F*!
!"#$%& >*>*> !"#$%&
!<=*5494'-1*B&##48
I-K*I"/0&'AF1*-OP'/4*R/0F/#
!""#AB&'AE)*+I-B.'AE)*+)/A0E)1-)'2*'"#$%&
-<=*53S7*B&##48
S#&'7(04*89F'A4/*:A04;&0/
3."-0/A4E0*+I-B.'AE)*+)/A0E)1-)'2*#"#$%&

65 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

Memory Map &

Extensions
Wally Memory Map
• Memory Map: Locations (addresses) of memory & I/O
(peripherals)
• Wally memory map contains:
– A small boot ROM
– A larger RAM
– Peripherals including:
• GPIO: General Purpose Input/Output for reading and writing binary
values from pins
• UART: Universal Asynchronous Receiver and Transmitter for serial
communication, such as printing to a terminal
• CLINT: Core Local Interrupter for handling software and timer
interrupts
• PLIC: Platform-Level Interrupt Controller for multiplexing external
interrupts
• SDC: Secure Digital (SD) Card controller

67 RISC-V System-on-Chip Design Chapter 2 RISC-V

Wally Memory Map
• Same as SiFive FU540 processor and QEMU
87FFFFFF
virt machine (virt: QEMU virtual model with
%1G
peripherals suitable for booting Linux)
80000000
– Except UART:
100600FF • 0x10010000 on SiFive FU540
2I,&
10060000
• 0x10000000 on Wally and virt
100400FF
(I,
10040000 • On reset, processor starts at reset vector,
01%.
10000007
10000000
which usually points to a boot ROM, which
I+,*
0FFF0000 contains the boot loader (loads the next stage
0C000000
of the OS from SD card, flash, or hard drive).
*+,-.
0200FFFF
02000000
– The reset vector is platform-dependent:
• 0x80000000: Wally reset vector (it jumps to boot ROM)
0001211F • 0x1000: in QEMU & buildroot Linux configuration
()*
00012100
• 0x1004: on SiFive FE540 chip

00001FFF
!""#$%&G
00001000

68 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Common RISC-V Extensions
Extension Instructions
M Multiply, divide, and remainder
F, D, Q Single-, double-, and quad-precision floating-point operations
A Atomic read-modify-write for synchronization
C Compressed (16-bit)
Zicsr CSRs and CSR instructions
Zfencei FENCE.I
Zfh Half-precision floating-point
Zk* Cryptography
V Vector
B Bit manipulations

69 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

RISC-V
Microarchitecture
Simplified Example
• Simplified RV32I core that supports following subset
of instructions:
– ALU Instructions: add, sub, and, or, slt,
addi, andi, ori, slti
– Memory Instructions: lw, sw
– Branch Instructions: beq, jal

71 RISC-V System-on-Chip Design Chapter 2 RISC-V

Performance
• Performance measured as time to execute a program
of interest, TCPU (CPU time):
TCPU = # instructions x CPI x Tc
CPI = clock cycles per instruction
Tc = clock cycle time

72 RISC-V System-on-Chip Design Chapter 2 RISC-V

Microarchitecture Overview
• Any microarchitecture must include:
– Architectural state: PC, registers, memory
• Simplified Microarchitecture Examples
– Single-cycle
– Pipelined
• Both have architectural state and run instructions
• Differ in performance and cost
• Cores are partitioned into:
– IFU: instruction fetch unit
– IEU: instruction execution unit
– LSU: load/store unit
73 RISC-V System-on-Chip Design Chapter 2 RISC-V
Chapter 1: RISC-V Introduction

RISC-V Single-Cycle
Processor
Single-Cycle Processor
OP;S. !T#
D>U?LB;S.
A>"DI
34*FI4MMDI C=4D>U?LB;S.

g9N
eI C=4Pd7BSdL*9N
*F9*-
a?7.B+ C=4;S.*9N
+N
a?7.BWE !"";S.*9N
!"# .LM aL@BU D>BISCB>
#c
* OPM>AB
N OP .LM
*K9*E D*
C* I#+ DE* N ;S.C
!7UBS
C DE 34RS * C=4D>U?LB

!"#
-F9-N
N !#4D>U?LB
C- DE- N ;S.< !#4CRS N
D- *
!$%&
**9W
C+ * *
IE+ ID-.LMD

D>@RE@B@
.LM U9#
C I#
IE DE
+*9W !""#AB
DEFD*+ 1O!&
OPOL?UF
i
F *F9*- a?7.B+
D>U?LB

On-chip memories: IROM: Instruction ROM

DTIM: Data tightly integrated memory
75 RISC-V System-on-Chip Design Chapter 2 RISC-V
 Extend Operation
ImmSrc ImmExt Type
00 {{20{Instr[31]}}, Instr[31:20]} I (12-bit)

01 {{20{Instr[31]}}, Instr[31:25], Instr[11:7]} S (12-bit)

10 {{20{Instr[31]}}, Instr[7], Instr[30:25], Instr[11:8], 1'b0} B (13-bit)
11 {{12{Instr[31]}}, Instr[19:12], Instr[20], Instr[30:21], 1'b0} J (21-bit)

%! %&#$' $,#$! $& I

!""#$$' !""#$%&%'
%!
!"#$B&'$E)"*+E$

%&#$' !!#+ * S
!""#$$' !""#$%&%'
%! * %&#$' !!#+ ! (
!""#$(' !""#$$&$'
%! %&#$& !"#!$ ! )
!""#)$&$('
%! !"#!$ $& %&#$' $,#$! ! J
!""#(%' !""#$*&$'
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
!II-.$*+E$
76 RISC-V System-on-Chip Design Chapter 2 RISC-V
ALU Operations
ALUControl[1] ALUControl[0] Funct3 ALUResult
(Sub) (ALUOp)
0 0 x add
0 1 000 add
0 1 110 or
0 1 111 and
1 1 000 sub
1 1 010 slt

77 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Main Decoder Truth Table
ALU
Instr Op RegWrite ImmSrc ALUSrc ALUOp ResultSrc MemWrite ResultSrc Branch Jump
lw 0000011 1 00 01 0 0 0 1 0 0
sw 0100011 0 01 01 0 0 1 0 0 0
R-type 0110011 1 xx 00 1 0 0 0 0 0
ALU
I-type 0010011 1 00 01 1 0 0 0 0 0
ALU
beq 1100011 0 10 11 0 0 0 0 1 0
jal 1101111 1 11 11 0 1 0 0 0 1

78 RISC-V System-on-Chip Design Chapter 2 RISC-V

Single-Cycle Control Unit
eI

cM7OI

?O]+IA G*SB

!"#U9W*PJ7OI
U9W*PJ7OI
!"#A ;9S<O=J9
ABC'E %&D()&* !"#7OI
aCE
RSS7OI4'E
U9[<O=J9

!"#AB

+,-
F*+IJ.L'E !"#M1+JO1P4'E
%&D()&*
F*+IJBC
!"#$%"&&'%

79 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

RISC-V Pipelined
Processor
Pipelined Processor
!9? @A? *>BLSCB>L
OP;SC# CDE CDE CDE
*>BLSCB># *>BLSCB>A
*>U?DB;SC# *>U?DB;SCA *>U?DB;SCL
A>"*L# A>"*LA
1OED*O..%* F=4*>U?DB;SC#

g9N
eI F=4Pc7BScD#
-I9-M
a?7CB. F=4;SC#
.N
a?7CBWE !"";SC+
aD@BU
aD@BU#
!U? OP CDE
CDE CDE
-h9-E
F- L#. *+- NN a;SCF#
- OPd>ABa !7UBS+ N- N ;SCF#
F *+ -N
N -
#d

1O34 F=4*>U?DB#

!"#
MI9MN
FM *+M NN N !#4*>U?DBA
N- !#4FRS# N
--9W N ;SC<# -
!"#$ F. -N
-

a;SC<#
-
L+. *%+I-.%
CDE

*>@R+@B@L
F L#
L+ *+
.-9W !""#AB#
%&D%EF
LM!$
i
P=*
#d

I -I9-M a?7CB.+ a?7CB.# a?7CB.A

OPOD?UIa --9W *R+ *R# *RA *RL
P=*

P=*

P=*
#d

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#d
!9?

*>U?DBL
acSM@SRF#
acSM@SR<#

aD?UkL
aD?UkA
aD?Uk+

aD?Uk#

;B@DDL
;B@DDA
;B@DD+

;B@DD#
;B@DDa

RSTS*F

U%D1R L%1OF% 9&%1WD% $%3O*> ;*-D%<S1=

81 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

Wally RISC-V SoC

 Wally Supported Features
• XLEN (32 or 64) • Additional Extensions
• Primary Extensions o Zicsr: CSRs
o A: Atomic o Zicntr: Performance counters
o C: Compressed o Zifencei: fence.i synchronization
o D: Double-precision floating- o Zfh: Half-precision floating-point
point o Zfa: Additional floating-point
o E: Embedded 16 registers o Zmmul: Integer multiplication
o F: Single-precision floating-point without division
o M: Multiplication and division o Zbc: Carry-free multiplication
o Q: Quad-precision floating-point o Zca, Zcb, Zcf, Zcd: Additional
o Zb*: Bit manipulation compressed instructions
o Zicsr: CSRs o Zicbom, Zicboz, Zicbop: Cache
o Zfencei: FENCE.I instruction management operations
synchronization o Zicclsm: Misaligned loads & stores
o Zk*: Cryptography o Zihintpause: Pause hint
o Zicond: Conditional zero

83 RISC-V System-on-Chip Design Chapter 2 RISC-V

Wally Supported Features
• Privileged Modes and Features
o M, S, U
o Reset vector address
o Virtual memory (ITLB, DTLB)
o Physical memory protection
o Vectored interrupts
• Caches and Branch Prediction
• Peripherals
o Core Local Interrupt Controller with
timers (CLINT)
o Platform Level Interrupt Controller
(PLIC)
o UART
o GPIO
o TIM

84 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Not Supported in Wally
• Vector extension
• Hypervisor extension
• Advanced microarchitecture: superscalar, out-of-order,
multithreading, multicore
• Unfrozen extensions
o L: Decimal floating-point
o J: Dynamically translated languages
o T: Transactional memory
o P: Packed SIMD

85 RISC-V System-on-Chip Design Chapter 2 RISC-V

Wally Block Diagram
-@D*LB

"?#

cTd.
FC
TU D(I
RR#
?T
RR#
D(F*+$I >9#

!C HBD*AW
!4$

!"#
!$# !"#$%C A-<

HM;
RF#

$4$ BIBD-CM*@a-@MCb

$T#

CL2W

WLM;M<B=BH U94

E2S2LH

$BCDE FBD*HB "IBD-CB RBA*LB .LMCB12DP

86 RISC-V System-on-Chip Design Chapter 2 RISC-V

 Wally Configurations
DTIM /
IROM I$/D$ Priv. Virt.
Configuration Config XLEN Size Bus Periph Size Modes Mem
Embedded rv32e 32 bits n/a YES NO n/a none NO
Simple CPU rv32i 32 bits 2K / 2K NO NO n/a none NO
μcontroller rv32ic 32 bits 4K / 16K YES YES n/a MU NO
Apps Proc rv32gc 32 bits n/a YES YES 16K MSU YES
Simple CPU rv64i 64 bits 2K / 2K NO NO n/a none NO
Apps Proc rv64gc 64 bits n/a YES YES 16K MSU YES

87 RISC-V System-on-Chip Design Chapter 2 RISC-V

Chapter 1: RISC-V Introduction

RISC-V Market
 Rapidly Changing Market
• 2010: RISC-V developed at Berkeley
• 2011: First RISC-V chip fabricated in 28 nm
• 2015: RISC-V Foundation launched
• 2015: SiFive founded by RISC-V inventors
• 2021: 12 billion RISC-V cores shipped in commercial products
• 2022: Seimco Research forecasts 40% annual growth through
2030

89 RISC-V System-on-Chip Design Chapter 2 RISC-V

 RISC-V International
• Stewards the open RISC-V standard
• > 60 working groups
• > 3000 individuals contributing
• Processes for approving new extensions
• Infrastructure development
• Architectural Compatibility Tests
• Compilers and simulators
• Operating system support
• Debug standards

90 RISC-V System-on-Chip Design Chapter 2 RISC-V

 RISC-V Processor Suppliers
• Startups and established companies selling IP
• Alibaba, Andes, Esperanto, Rivos, Semidynamics, SiFive,
• Tenstorrent, Ventana, Western Digital
• In-house use
• Qualcomm, Intel
• Open Source IP
• OpenHW Group
• Global competition and cooperation
• Especially United States, China, Taiwan, Europe, India
• Open architecture reduces barriers to entry

91 RISC-V System-on-Chip Design Chapter 2 RISC-V

Commercial RV64 Multicore Apps Processors

92 RISC-V System-on-Chip Design Chapter 2 RISC-V

Commercial RV32 Embedded Processors

93 RISC-V System-on-Chip Design Chapter 2 RISC-V

Open-Source RV64 Apps Processors

94 RISC-V System-on-Chip Design Chapter 2 RISC-V

Open-Source RV32 Embedded Processors

95 RISC-V System-on-Chip Design Chapter 2 RISC-V

About these Notes
RISC-V System-on-Chip Design Lecture Notes
© 2025 D. Harris, J. Stine, R. Thompson, and S. Harris

These notes may be used and modified for educational and/or

non-commercial purposes so long as the source is attributed.

96 RISC-V System-on-Chip Design Chapter 2 RISC-V