CS T42 - MICROPROCESSORS AND MICROCONTROLLERS Dept of CSE

2 MARK QUESTIONS

1. What is Microprocessor ?
It is a program controlled semiconductor device (IC}, which fetches, decode and executes
instructions.

2. What are the basic units of a microprocessor?

The basic units or blocks of a microprocessor are ALU, an array of registers and control unit.

3. What is Software and Hardware?

The Software is a set of instructions or commands needed for performing a specific task by a
programmable device or a computing machine. The Hardware refers to the components or
devices used to form computing machine in which the software can be run and tested. Without
software the Hardware is an idle machine.

4. What is assembly language?

The language in which the mnemonics (short -hand form of instructions) are used to write a
program is called assembly language. The manufacturers of microprocessor give the mnemonics.

5. What are machine language and assembly language programs?

The software developed using 1's and 0's are called machine language, programs. The software
developed using mnemonics are called assembly language programs.

6. What is the drawback in machine language and assembly language, programs?

The machine language and assembly language programs are machine dependent. The programs
developed using these languages for a particular machine cannot be directly run on another
machine.

7. Define bit, byte and word.

A digit of the binary number or code is called bit. Also, the bit is the fundamental storage unit of
computer memory. The 8-bit (8-digit) binary number or code is called byte and 16-bit binary
number or code is called word.

8. What is a bus?
Bus is a group of conducting lines that carries data, address and control signals.

9. Why data bus is bi-directional?

The microprocessor has to fetch (read) the data from memory or input device for processing and
after processing, it has to store (write) the data to memory or output device. Hence the data bus is
bi-directional.

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10. Why address bus is unidirectional?

The address is an identification number used by the microprocessor to identify or access a
memory location or I / O device. It is an output signal from the processor. Hence the address bus
is unidirectional.

11. What is the function of microprocessor in a system?

The microprocessor is the master in the system, which controls all the activity of the system. It
issues address and control signals and fetches the instruction and data from memory. Then it
executes the instruction to take appropriate action.

12. What are the modes in which 8086 can operate?

The 8086 can operate in two modes and they are minimum (or uniprocessor) mode and
maximum (or multiprocessor) mode.

13. What is the data and address size in 8086?

The 8086 can operate on either 8-bit or 16-bit data. The 8086 uses 20-bit address to access
memory and 16-bit address to access 1/0 devices.

14. Explain the function of M/IO in 8086.

The signal M/IO is used to differentiate memory address and 1/0 address When the processor is
accessing memory locations MI 10 is asserted high and when it is accessing 1/0 mapped devices
it is asserted low.

15. Write the flags of 8086.

The 8086 has nine flags and they are
1. Carry Flag (CF) 6. Overflow Flag (OF)
2. Parity Flag (PF) 7. Trace Flag (TF)
3. Auxiliary carry Flag (AF) 8. Interrupt Flag (IF)
4. Zero Flag (ZF) 9. Direction Flag (DF)
5. Sign Flag (SF)

16. What are the interrupts of 8086?

The interrupts of 8085 are INTR and NMI. The INTR is general maskable interrupt and NMI is
non-maskable interrupt.

17. How clock signal is generated in 8086? What is the maximum internal clock frequency
of 8086?
The 8086 does not have on-chip clock generation circuit. Hence the clock generator chip, 8284 is
connected to the CLK pin of8086. The clock signal supplied by 8284 is divided by three for
internal use. The maximum internal clock frequency of8086 is 5MHz.

18. Write the special functions carried by the general purpose registers of 8086.
The special functions carried by the registers of 8086 are the following.
Register Special function
1. AX 16-bit Accumulator
2. AL 8-bit Accumulator

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3. BX Base Register
4. CX Count Register
5. DX .Data Register

19. What is pipelined architecture?

In pipelined architecture the processor will have number of functional units and the execution
time of functional units is overlapped. Each functional unit works independently most of the
time.

20. What are the functional units available in 8086 architecture?

The bus interface unit and execution unit are the two functional units available in 8086
architecture.

21. List the segment registers of 8086.

The segment registers of 8086 are Code segment, Data segment, Stack segment and Extra
segment registers.

22. Define machine cycle.

Machine cycle is defined as the time required to complete one operation of accessing memory,
I/O, or acknowledging an external request. This cycle may consist of three to six T-states.

23. Define T-State.

T-State is defined as one subdivision of the operation performed in one clock period. These
subdivisions are internal states synchronized with the system clock, and each T-State is precisely
equal to one clock period.

24. List the components of microprocessor based system

The microprocessor based system consist of microprocessor as CPU, semiconductor memories
like EPROM and RAM, input device, output device and interfacing devices.

25. Why interfacing is needed for 1/0 devices?

Generally I/O devices are slow devices. Therefore the speed of I/O devices does not match with
the speed of microprocessor. And so an interface is provided between system bus and I/O
devices.

26. What is the difference between CPU bus and system bus?
The CPU bus has multiplexed lines but the system bus has separate lines for each signal. (The
multiplexed CPU lines are demultiplexed by the CPU interface circuit to form system bus).

27. What does memory-mapping mean?

The memory mapping is the process of interfacing memories to microprocessor and allocating
addresses to each memory locations.

28. What is interrupt 1/0?

If the 1/0 device initiate the data transfer through interrupt then the 1/0 is called interrupt driven
1/0.

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29. Why EPROM is mapped at the beginning of memory space in 8085 system?
In 8085 microprocessor, after a reset, the program counter will have OOOOH address. If the
monitor program is stored from this address then after a reset, it will be executed automatically.
The monitor program is a permanent program and stored in EPROM memory. If EPROM
memory is mapped at the beginning of memory space, i.e., at OOOOH, then the monitor
program will be executed automatically after a reset.

30. What is the need for system clock and how it is generated in 8085?
The system clock is necessary for synchronizing various internal operations or devices in the
microprocessor and to synchronize the microprocessor with other peripherals in the system.

31. What is DMA?

The direct data transfer between I/O device and memory is called DMA.

32. What is the need for Port?

The I/O devices are generally slow devices and their timing characteristics do not match with
processor timings. Hence the I/O devices are connected to system bus through the ports.

33. What is a port?

The port is a buffered I/O, which is used to hold the data transmitted from the microprocessor to
I/O device or vice-versa.

34. Give some examples of port devices used in 8085 microprocessor basedsystem?
The various INTEL I/O port devices used in 8085 microprocessor based system are 8212, 8155,
8156, 8255, 8355 and 8755.

35. Write a short note on INTEL 8255?

The INTEL 8255 is a I/O port device consisting of 3 numbers of 8 –bit parallel I/O ports. The
ports can be programmed to function either as a input port or as a output port in different
operating modes. It requires 4 internal addresses and has one logic LOW chip select pin.

36. What is the drawback in memory mapped I/0?

When I/O devices are memory mapped, some of the addresses are allotted to I/O devices and so
the full address space cannot be used for addressing memory (i.e., physical memory address
space will be reduced). Hence memory mapping is useful only for small systems, where the
memory requirement is less.

37. How DMA is initiated?

When the I/O device needs a DMA transfer, it will send a DMA request signal to DMA
controller. The DMA controller in turn sends a HOLD request to the processor. When the
processor receives a HOLD request, it will drive its tri-stated pins to high impedance state at the
end of current instruction execution and send an acknowledge signal to DMA controller. Now
the DMA controller will perform DMA transfer.

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38. What is processor cycle (Machine cycle)?

The processor cycle or machine cycle is the basic operation performed by the processor. To
execute an instruction, the processor will run one or more machine cycles in a particular order.

39. What is Instruction cycle?

The sequence of operations that a processor has to carry out while executing the instruction is
called Instruction cycle. Each instruction cycle of a processor indium consists of a number of
machine cycles.

40. What is fetch and execute cycle?

In general, the instruction cycle of an instruction can be divided into fetch and execute cycles.
The fetch cycle is executed to fetch the opcode from memory. The execute cycle is executed to
decode the instruction and to perform the work instructed by the instruction.

41. What is Block and Demand transfer mode DMA?

In Block transfer mode, the DMA controller will transfer a block of data and relieve the bus for
processor. After sometime another block of data is transferred by DMA and so on. In Demand
transfer mode the DMA controller will complete the entire .data transfer at a stretch and then
relieve the bus to processor.

42. What is the need for timing diagram?

The timing diagram provides information regarding the status of various signals, when a machine
cycle is executed. The knowledge of timing diagram is essential for system designer to select
matched peripheral devices like memories, latches, ports, etc., to form a microprocessor system.

43. How many machine cycles constitute one instruction cycle in 8085?
Each instruction of the 8085 processor consists of one to five machine cycles.

44. Define opcode and operand.

Opcode (Operation code) is the part of an instruction / directive that identifies a specific
operation. Operand is a part of an instruction / directive that represents a value on which the
instruction acts.

45. What is opcode fetch cycle?

The opcode fetch cycle is a machine cycle executed to fetch the opcode of an instruction stored
in memory. Every instruction starts with opcode fetch machine cycle.

46. What operation is performed during first T -state of every machine cycle in 8085?
In 8085, during the first T -state of every machine cycle the low byte address is latched into an
external latch using ALE signal.

47. Why status signals are provided in microprocessor?

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The status signals can be used by the system designer to track the internal operations of the
processor. Also, it can be used for memory expansion (by providing separate memory banks for
program & data and selecting the bank using status signals).

48. How the 8085 processor differentiates a memory access (read/write) and 1/0 access
(read/write)?
The memory access and 1/0 access is differentiated using 10 I M signal. The 8085 processor
asserts 10 I M low for memory read/write operation and 10 I M is asserted high for 1/0
read/write operation.

49. When the 8085 processor checks for an interrupt?

In the second T -state of the last machine cycle of every instruction, the 8085 processor checks
whether an interrupt request is made or not.

50. What is interrupt acknowledge cycle?

The interrupt acknowledge cycle is a machine cycle executed by 8085 processor to get the
address of the interrupt service routine in-order to service the interrupt device.

51. How the interrupts are affected by system reset?

Whenever the processor or system is reset, all the interrupts except TRAP are disabled. fu order
to enable the interrupts, El instruction has to be executed after a reset.

52. What is Software interrupts?

The Software interrupts are program instructions. These instructions are inserted at desired
locations in a program. While running a program, if software interrupt instruction is encountered
then the processor executes an interrupt service routine.

53. What is Hardware interrupt?

If an interrupt is initiated in a processor by an appropriate signal at the interrupt pin, then the
interrupt is called Hardware interrupt.

54. What is the difference between Hardware and Software interrupt?

The Software interrupt is initiated by the main program, but the Hardware interrupt is initiated by
an external device. In 8085, the Software interrupt cannot be disabled or masked but the
Hardware interrupt except TRAP can be disabled or masked.

55. What is Vectored and Non- Vectored interrupt?

When an interrupt is accepted, if the processor control branches to a specific address defined by
the manufacturer then the interrupt is called vectored interrupt.
In Non-vectored interrupt there is no specific address for storing the interrupt service routine.
Hence the interrupted device should give the address of the interrupt service routine.

56. List the Software and Hardware interrupts of 8085?

Software interrupts: RST 0, RSTl, RST 2, RST 3, RST 4, RST 5,RST 6 and RST 7.
Hardware interrupts: TRAP, RST 7.5, RST 6.5, RST 5.5 and INTR.

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57. What is TRAP?

The TRAP is non-maskable interrupt of8085. It is not disabled by processor reset or after
reorganization of interrupt.

58. Whether HOLD has higher priority than TRAP or not?

The interrupts including mAP are recognized only if the HOLD is not valid, hence TRAP has
lower priority than HOLD.

59. What is masking and why it is required?

Masking is preventing the interrupt from disturbing the current program execution. When the
processor is performing an important job (process) and if the process should not be interrupted
then all the interrupts should be masked or disabled.
In processor with multiple 'interrupts, the lower priority interrupt can be masked so as to prevent
it from interrupting, the execution of interrupt service routine of higher priority interrupt.

60. When the 8085 processor accept hardware interrupt?

The processor keeps on checking the interrupt pins at the second T -state of last Machine cycle
of every instruction. If the processor finds a valid interrupt signal and if the interrupt is
unmasked and enabled then the processor accepts the interrupt. The acceptance of the interrupt is
acknowledged by sending an OOA signal to the interrupted device.

61. When the 8085 processor will disable the interrupt system?
The interrupts of 8085 except TRAP are disabled after anyone of the following operations
1. Executing El instruction.
2. System or processor reset.
3. After reorganization (acceptance) of an interrupt.

62. What is the function performed by Dl instruction?

The function of Dl instruction is to enable the disabled interrupt system.

63. What is the function performed by El instruction?

The El instruction can be used to enable the interrupts after disabling.

64. How the vector address is generated for the INTR interrupt of 8085?
For the interrupt INTR, the interrupting device has to place either RST opcode or CALL opcode
followed by l6-bit address. I~RST opcode is placed then the corresponding vector address is
generated by the processor. In case of CALL opcode the given l6-bit address will be the vector
address.

65. How clock signals are generated in 8085 and what is the frequency of theinternal clock?
The 8085 has the clock generation circuit on the chip but an external quartz crystal or L C circuit
or RC circuit should be connected at the pins XI and X2. The maximum internal clock frequency
of 8085A is 3.03 MHz

66. What happens to the 8085 processor when it is reset?

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When the 8085 processor is reset it executes the first instruction at the OOOOH location. The
8085 resets (clears) instruction register, interrupt mask bits and other registers.

67. What are the operations performed by ALU of 8085?

The operations performed by ALU of 8085 are Addition, Subtraction, Logical AND, OR,
Exclusive OR, Compare Complement, Increment, Decrement and Left I Right shift

68. What is a flag?

Flag is a flip flop used to store the information about the status of the processor and the status of
the instruction executed most recently.

69. List the flags of 8085

There are five flags in 8085. They are sign flag, zero flag, Auxiliary carry flag, parity flag and
carry flag.

70. What is the Hardware interrupts of 8085?

The hardware interrupts in 8085 are TRAP, RST 7.5, RST 6.5 and RST 5,5. 41.

71. Which interrupt has highest priority in 8085? What is the priority of otherinterrupts?
The TRAP has the highest priority, followed by RST 7.5, RST 6.5, RST 5.5 and INTR.

72 What is ALE?
The ALE (Address Latch Enable) is a signal used to demultiplex the address and data lines,
using an external latch. It is used to enable the external latch.

73. Explain the function of IO/M in 8085.

The IO/M is used to differentiate memory access and I/O access. For IN and OUT instruction it
is high. For memory reference instructions it is low.

74. Where is the READY signal used?

READY is an input signal to the processor, used by the memory or I/O devices to get extra time
for data transfer or to introduce wait states in the bus cycles.

75. What is HOLD and HLDA and how it is used?

Hold and hold acknowledge signals are used for the Direct Memory Access (DMA) type of data
transfer. The DMA controller place a high on HOLD pins in order to take control of the system
bus. The HOLD request is acknowledged by the 8085 by driving all its tristated pins to high
impedance state and asserting HLDA signal high.

76. What is Polling?

Polling is a scheme or an algorithm to identify the devices interrupting the processor. Polling is
employed when multiple devices interrupt the processor through one interrupt pin of the
processor.

77. What are the different types of Polling?

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The polling can be classified into software and hardware polling. In software polling the entire
polling process is govern by a prograrn.1n hardware polling, the hardware takes care of checking
the status of interrupting devices and allowing one by one to the processor.

78. What is the need for interrupt controller?

The interrupt controller is employed to expand the interrupt inputs. It can handle the interrupt
request from various devices and allow one by one to the processor.

79. List some of the features of INTEL 8259 (Programmable Interrupt

Controller)
1. It manage eight interrupt request
2. The interrupt vector addresses are programmable.
3. The priorities of interrupts are programmable.
4. The interrupt can be masked or unmasked individually.

80. What is a programmable peripheral device?

If the functions performed by a peripheral device can be altered or changed by a program
instruction then the peripheral device is called programmable device. Usually the programmable
devices will have control registers. The device can be programmed by sending control word in
the prescribed format to the control register.

81. What is synchronous data transfer scheme?

For synchronous data transfer scheme, the processor does not check the readiness of the device
after a command has been issued for read/write operation. This scheme the processor will request
the device to get ready and then read/W1.ite to the device immediately after the request. In some
synchronous schemes a small delay is allowed after the request.

82. What is asynchronous data transfer scheme?

In asynchronous data transfer scheme, first the processor sends a request to the device for
read/write operation. Then the processor keeps on polling the status of the device. Once the
device is ready, the processor executes a data transfer instruction to complete the process.

83. What are the operating modes of 8212?

The 8212 can be hardwired to work either as a latch or tri-state buffer. If mode (MD) pin is tied
HIGH then it will work as a latch and so it can be used as output port. If mode (MD) pin is tied
LOW then it work as tri- state buffer and so it can be used as input port.

84. Explain the working of a handshake output port

In handshake output operation, the processor will load a data to port. When the port receives the
data, it will inform the output device to collect the data. Once the output device accepts the data,
the port will inform the processor that it is empty. Now the processor can load another data to
port and the above process is repeated.

85. What are the internal devices of 8255?

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The internal devices of 8255 are port-A, port-B and port-C. The ports can be programmed for
either input or output function in different operating modes.

86. What is baud rate?

The baud rate is the rate at which the serial data are transmitted. Baud rate is defined as l /(The
time for a bit cell). In some systems one bit cell has one data bit, then the baud rate and bits/sec
are same.

87. What is USART?

The device which can be programmed to perform Synchronous or Asynchronous serial
communication is called USART (Universal Synchronous Asynchronous Receiver Transmitter).
The INTEL 8251A is an example of USART.

88. What are the functions performed by INTEL 8251A?

The INTEL 825lA is used for converting parallel data to serial or vice versa. The data
transmission or reception can be either asynchronously or synchronously. The 8251A can be
used to interface MODEM and establish serial communication through MODEM over telephone
lines.

89. What is an Interrupt?

Interrupt is a signal send by an external device to the processor so as to request the processor to
perform a particular task or work.

90. What are the control words of 8251A and what are its functions?
The control words of 8251A are Mode word and Command word. The mode word informs 8251
about the baud rate, character length, parity and stop bits. The command word can be sent to
enable the data transmission and reception.

91. What are the information that can be obtained from the status word of 8251?
The status word can be read by the CPU to check the readiness of the transmitter or receiver and
to check the character synchronization in synchronous reception. It also provides information
regarding various errors in the data received. The various error conditions that can be checked
from the status word are parity error, overrun error and framing error.

92. Give some examples of input devices to microprocessor-based system.

The input devices used in the microprocessor-based system are Keyboards, DIP switches, ADC,
Floppy disc, etc.

93. What are the tasks involved in keyboard interface?

The task involved in keyboard interfacing are sensing a key actuation, Debouncing the key and
Generating key codes (Decoding the key). These task are performed software if the keyboard is
interfaced through ports and they are performed by hardware if the keyboard is interfaced
through 8279.

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94. How a keyboard matrix is formed in keyboard interface using 8279?

The return lines, RLo to RL7 of 8279 are used to form the columns of keyboard matrix. In
decoded scan the scan lines SLo to SL3 of 8279 are used to form the rows of keyboard matrix. In
encoded scan mode, the output lines of external decoder are used as rows of keyboard matrix.

95. What is scanning in keyboard and what is scan time?

The process of sending a zero to each row of a keyboard matrix and reading the columns for key
actuation is called scanning. The scan time is the time taken by the processor to scan all the rows
one by one starting from first row and coming back to the first row again.

96. What is scanning in display and what is the scan time?

In display devices, the process of sending display codes to 7 –segment LEDs to display the LEDs
one by one is called scanning ( or multiplexed display). The scan time is the time taken to
display all the 7-segment LEDs one by one, starting from first LED and coming back to the first
LED again.

97. What are the internal devices of a typical DAC?

The internal devices of a DAC are R/2R resistive network, an internal latch and current to
voltage converting amplifier.

98. What is settling or conversion time in DAC?

The time taken by the DAC to convert a given digital data to corresponding analog signal is
called conversion time.

99. What are the different types of ADC?

The different types of ADC are successive approximation ADC, counter type ADC flash type
ADC, integrator converters and voltageto- frequency converters.

100. Define stack

Stack is a sequence of RAM memory locations defined by the programmer.

101. What is program counter? How is it useful in program execution?

The program counter keeps track of program execution. To execute a program the starting
address of the program is loaded in program counter. The PC sends out an address to fetch a byte
of instruction from memory and increments its content automatically.

102. How the microprocessor is synchronized with peripherals?

The timing and control unit synchronizes all the microprocessor operations with clock and
generates control signals necessary for communication between the microprocessor and
peripherals.

103. What is a minimum system and how it is formed in 8085?

A minimum system is one which is formed using minimum number of IC chips, The 8085 based
minimum system is formed using 8155, 8355 and 8755.

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104. What is meant by microcontroller?

A device which contains the microprocessor with integrated peripherals like memory, serial
ports, parallel ports, timer/counter, interrupt controller, data acquisition interfaces like ADC,
DAC is called microcontroller.

105. List the features of 8051 microcontroller?

The features are
*single_supply +5 volt operation using HMOS technology.
*4096 bytes program memory on chip (not on 8031)
*128 data memory on chip.
*Four register banks.
*Two multiple mode, 16-bit timer/counter.
*Extensive Boolean processing capabilities.
*64 KB external RAM size
*32 bidirectional individually addressable I/O lines.
*8 bit CPU optimized for control applications.

106. Explain the operating mode0 of 8051 serial ports?

In this mode serial enters &exits through RXD, TXD outputs the shift clock.8 bits are
transmitted/received: 8 data bits(LSB first).The baud rate is fixed at 1/12 the oscillator
frequency.

107 Explain the operating mode2 of 8051 serial ports?

In this mode 11 bits are transmitted(through TXD)or received (through RXD):a start bit(0), 8
data bits(LSB first),a programmable 9th data bit ,& a stop bit(1).ON transmit the 9th data bit
(TB* in SCON)can be assigned the value of 0 or 1.Or for eg:, the parity bit(P, in the PSW)could
be moved into TB8.On receive the 9th data bit go in to the RB8 in Special Function Register
SCON, while the stop bit is ignored. The baud rate is programmable to either 1/32or1/64 the
oscillator frequency.

108. Explain the mode3 of 8051 serial ports?

In this mode,11 bits are transmitted(through TXD)or received(through RXD):a start bit(0), 8 data
bits(LSB first),a programmable 9th data bit ,& a stop bit(1).In fact ,Mode3 is the same as Mode2
in all respects except the baud rate. The baud rate in Mode3 is variable. In all the four modes,
transmission is initiated by any instruction that uses SBUF as a destination register. Reception is
initiated in Mode0 by the condition RI=0&REN=1.Reception is initiated in other modes by the
incoming start bit if REN=1.

109. Explain the interrupts of 8051 microcontroller?

The interrupts are:
Vector address
• External interrupt 0 : IE0 : 0003H
• Timer interrupt 0 : TF0 : 000BH
• External interrupt 1 : IE1 : 0013H
• Timer Interrupt 1 : TF1 : 001BH
• Serial Interrupt

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Receive interrupt : RI : 0023H

Transmit interrupt: TI : 0023H

110. Write A program to perfom multiplication of 2 nos using 8051?

MOV A,#data 1
MOV B,#data 2
MUL AB
MOV DPTR,#5000
MOV @DPTR,A(lower value)
INC DPTR
MOV A,B
MOVX @ DPTR,A

111. Write a program to mask the 0th &7th bit using 8051?
MOV A,#data
ANL A,#81
MOV DPTR,#4500
MOVX @DPTR,A
LOOP SJMP LOOP

112. List the addressing modes of 8051?

• Direct addressing
• Register addressing
• Register indirect addressing.
• Implicit addressing
• Immediate addressing
• Index addressing
• Bit addressing

113. Write about CALL statement in 8051?

There are two subroutine CALL instructions. They are
*LCALL (Long CALL)
*ACALL (Absolute CALL)
Each increments the PC to the 1st byte of the instruction & pushes them in to the stack.

114. Write about the jump statement?

There are three forms of jump. They are
LJMP (Long jump)-address 16
AJMP (Absolute Jump)-address 11
SJMP (Short Jump)-relative address

115. Write program to load accumulator, DPH, &DPL using 8051?

MOV A,#30
MOV DPH, A
MOV DPL, A

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116. Write a program to find the 2’s complement using 8051?

MOV A, R0
CPL A
INC A

117. Write a program to add 2 8-bit numbers using 8051?

MOV A,#30H
ADD A,#50H

118. Write a program to swap two numbers using 8051?

MOV A, #data
SWAP A

119. Write a program to subtract 2 8-bit numbers &exchange the digits using
8051?
MOV A,#9F
MOV R0,#40
SUBB A, R0
SWAP A

120. Write a program to subtract the contents of R1 of Bank 0from the contentsof R0 of
Bank 2 using 8051?
MOV PSW, #10
MOV A, R0
MOV PSW, #00
SUBB A, R1

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11 MARK QUESTIONS AND ANSWERS

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UNIT 1
1.Explain the evolution of microprocessor?

EVOLUTION OF MICROPROCESSOR

1ST GENERATION µP : 1969

 4 Bit microprocessor
 Memory capacity : 4096 byts
 It has 45 instructions
 The frequenzy is very low

CHARACTERISTICS :

 Low cost
 Slow in speed
 Low operational current
 Not compatable in TTL levels

OTHER 4 BIT PROCESSOR :

 Intel 4040
 Fairchild PPS25
 National IMP4
 Rockweln PPS4
 Microsystem INTLMCI

APPLICATION

 Calculator
 Game machine
 Home appliances
 Accounting system
 Intelligent instrumentation

2nd GENERATION µP : 1973

 Intel co-operation introduced the 8-bit µP 8008 and 8080

IMPROVEMENT OVER 1st GENERATION µP

 Memory capacity in 64kb

 TTL compatable

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 Speed is heigh
 Clock frequenzy is in the range 1MHz – 6MHz
 NMOS technology is employed
 Offers faster speed and higher density than PMOS
 8-bit processor is yhe other name for 2nd generation µP

OTHER 8-BIT PROCESSORS :

 Intel 8080
 Intel 8085
 fairchild F8
 Motorola M6800
 Motorola M6809
 National CMP
 Zilog 80/Z80

CHARACTERISTICS :

 long chip size

 40 pin DIP
 More number of ON chip diode timing signals
 Ability to address larger memory location
 Ability to address more I/o codes
 Faster operation
 Most powerful instruction set
 Great number of levels of sub routine nesting
 Better interrupt handling capabilities

APPLICATION :

 Complex industrial controles

 Communication preprocessor control
 Process control system
 Instrumentation
 Intelligent terminals
 Military application

3rd GENERATION µP : 1978

 Released by intel co-operation in 1978

 16 bit µP ie. 8086
 16 bit µP are called lllrd generation µP
 Memory range is 1MB to 16MB

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 Works in multiprocesspr environment

 Nses HMOS(high speed MOS) technology
 Offers better speed and high packing density than NMOS

SOME OTHER 3rd GENERATION µP :

 Provided with 40/48/68 pins

 High speed and very strong processing capability
 Easier to program
 Allow for dynamically relocatable program
 Size of the internal register are 8.16/32 bits
 Processor has multiply or divide arithmetic hardware
 More powerful interrupt handling capability
 Flexible i/p ; o/p port addressing
 Different modes of operation

4th GENERATION µP : 1980

 Released by intel in 1980

 32 bit µP and has great memory
 32 bit µP are 4th generation µP
 INTEL 80386 :
 first 32 bit µP in 1985
 4GB of memory
 25/33/40 NHz clock frequenzy

INTEL 80486 :

 Improved version of 80386

 Has CPU , an arithmetic co-processor
 Me,pry management unit and 8kb cache memory

MOTOROLA 68030 :

 32 bit µP in 1985
 Most powerful

2.Draw and explain in detail about the 8085 architecture?

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8085 ARCHITECTURE:

The functional block diagram or architecture of 8085

Microprocessor is very important as it gives the complete details about a Microprocessor. Fig.
shows the Block diagram of a Microprocessor.

Accumulator (A):

 The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).
 This register is used to store 8-bit data and to perform arithmetic and logical operations.
 The result of an operation is stored in the accumulator.

Temporary Registers:

 The temporary regisrer receives one of the data to be processed by ALU.

 It stores the operand of arithmetic and logic operations.

Flags:

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 The ALU includes five flip-flops that are set or reset according to the result of an
operation.
 The microprocessor uses the flags for testing the data conditions.
 They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The
most commonly used flags are Sign, Zero, and Carry.

The bit position for the flags in flag register is,

1.Sign Flag (S):

After execution of any arithmetic and logical operation, if D7 of the result is 1, the sign flag
is set. Otherwise it is reset.
D7 is reserved for indicating the sign; the remaining is the magnitude of number.
If D7 is 1, the number will be viewed as negative number. If D7 is 0, the number will be
viewed as positive number.

2.Zero Flag (z):

If the result of arithmetic and logical operation is zero, then zero flag is set otherwise it
is reset.

3.Auxiliary Carry Flag (AC):

If D3 generates any carry when doing any arithmetic and logical operation, this flag is
set.Otherwise it is reset.

4.Parity Flag (P):

If the result of arithmetic and logical operation contains even number of 1's then this flag
will be set and if it is odd number of 1's it will be reset.

5.Carry Flag (CY):

If any arithmetic and logical operation result any carry then carry flag is set otherwise it is
reset.

Arithmetic and Logic Unit (ALU):

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 It is used to perform the arithmetic operations like addition, subtraction, multiplication,

division, increment and decrement and logical operations like AND, OR and EX-OR.
 It receives the data from accumulator and registers.
 According to the result it set or reset the flags.

Registers of 8085:

 The 8085 have six general-purpose registers to store 8-bit data during program execution.
 These registers are identified as B, C, D, E, H, and L.
 They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit
operations.

Instruction register and Decoder:

 The instruction fetched from memory is stored here.
 The decoder decodes the contents of the instruction.
 It determines the operation to be followed in executing the instruction.
Program Counter (PC):

 This 16-bit register sequencing the execution of instructions.

 It is a memory pointer. Memory locations have 16-bit addresses, and that is why this is a
16-bit register.
 The function of the program counter is to point to the memory address of the next
instruction to be executed.
 When an opcode is being fetched, the program counter is incremented by one to point to
the next memory location.

Stack Pointer (Sp):

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 The stack pointer is also a 16-bit register used as a memory pointer.

 It points to a memory location in R/W memory, called the stack.
 The beginning of the stack is defined by loading a 16-bit address in the stack pointer
(register).

Timing and Control unit:

 It has three control signals ALE, RD (Active low) and WR (Active low) and three status
signals IO/M(Active low), S0 and S1.
 ALE is used for provide control signal to synchronize the components of microprocessor
and timing for instruction to perform the operation.
 RD (Active low) and WR (Active low) are used to indicate whether the operation is
reading the data from memory or writing the data into memory respectively.
 IO/M(Active low) is used to indicate whether the operation is belongs to the memory or
peripherals.
 If,

3.Explain briefly about the addressing modes of 8085?

ADDRESSING MODES OF 8085

Immediate Addressing Mode:

In this type of addressing mode the operand is specified within the instruction itself.

EXAMPLE

 ADI 34H
 MVI B,05H

Direct Addressing :

In this mode of addressing, the address of the data (operand) is specified within the instruction.

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EXAMPLE

 OUT 10H
 LDA 4100H

Register Addressing Mode:

In this type of addressing mode the instruction specifies the name of the register in which the
data is available and Opcode specifies the name (or) address of the register on which the
operation would be performed.

EXAMPLE

 MOV A, B
 SUB H

Register Indirect Addressing Mode:

This is indirect way of addressing. In this mode the instruction specifies the name of the register
in which the address of the data is available.

EXAMPLE

 MOV A, M
 SUB M

Implied Addressing

The addressing mode of certain instructions is implied by the instruction’s function.

EXAMPLE

 STC
 DAA

4.Explain briefly about instruction set of 8085?

INSTRUCTION SET OF 8085

Data Transfer Instructions:

The data transfer instructions move data between registers or between memory and registers.

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EXAMPLE:

MOV B,C

BEFORE EXECUTION AFTEREXECUTION

B C B C

C2 E4 E4 E4

MVI D,09

BEFORE EXECUTION AFTER EXECUTION

C2 09

Arithmetic Instructions:

The arithmetic instructions add, subtract, increment, or decrement data in registers or memory.

EXAMPLE:

ADD B

BEFORE EXECUTION AFTER EXECUTION

A B A B

C2 B8 7A B8

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SUB B

BEFORE EXECUTION AFTER EXECUTION

A B A B

C4 89 3B 89

Logical Instructions:

This group performs logical (Boolean) operations on data in registers and memory and on
condition flags.

EXAMPLE:

ANA B

BEFORE EXECUTION AFTER EXECUTION

A B A B
15 E2 00 E2

XRA A

BEFORE EXECUTION AFTER EXECUTION

A 74 B A
00

Branching Instructions:

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The branching instructions alter normal sequential program flow, either unconditionally or
conditionally.

EXAMPLE:

 JMP 4500
 CALL 4300
 JNZ 4200

Machine Control instructions :

These instructions control machine functions.

EXAMPLE:

 EI

 DI
 HLT

5. Draw and explain in detail of pins in 8085?

8085 Pin description.

Properties

Single + 5V Supply
4 Vectored Interrupts (One is Non Maskable)
Serial In/Serial Out Port
Decimal, Binary, and Double Precision Arithmetic
Direct Addressing Capability to 64K bytes of memory

The Intel 8085A is a new generation, complete 8 bit parallel central processing unit (CPU). The
8085A uses a multiplexed data bus. The address is split between the 8bit address bus and the 8bit
data bus. Figures are at the end of the document.

Pin Description

The following describes the function of each pin:

A6 - A1s (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3
stated during Hold and Halt modes.

AD0 - 7 (Input/Output 3state)

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Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on
the bus during the first clock cycle of a machine state. It then becomes the data bus during the
second and third clock cycles. 3 stated during Hold and Halt modes.
ALE (Output)
Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the
address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to
guarantee setup and hold times for the address information. ALE can also be used to strobe the
status information. ALE is never 3stated.
SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:

S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.

RD (Output 3state)

READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is
available for the data transfer.

WR (Output 3state)

WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0
location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.

READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready
to send or receive data. If Ready is low, the CPU will wait for Ready to go high before
completing the read or write cycle.

HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The
CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the completion
of the current machine cycle. Internal processing can continue. The processor can regain the
buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD,
WR, and IO/M lines are 3stated.

HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it
will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is
removed. The CPU takes the buses one half clock cycle after HLDA goes low.

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INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the
next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be
inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or
CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled
and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during
the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip
or some other interrupt port.

RST 5.5
RST 6.5 - (Inputs)
RST 7.5

RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they
cause an internal RESTART to be automatically inserted.

RST 7.5 ~~ Highest Priority

RST 6.5
RST 5.5 o Lowest Priority

The priority of these interrupts is ordered as shown above. These interrupts have a higher priority
than the INTR.

TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is
unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops.
None of the other flags or registers (except the instruction register) are affected The CPU is held
in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to the
processor clock.

X1, X2 (Input)

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Crystal or R/C network connections to set the internal clock generator X1 can also be an external
clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating
frequency.

CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an
input to the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt
modes.
SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM
instruction is executed.
SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.
Vcc

+5 volt supply.

Vss

Ground Reference.

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6.Explain briefly about instruction word size of 8085?

Instruction word size

The 8085 instruction set is classified into the following three groups according to
word size:
1. One-word or 1-byte instructions
2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions
In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.
However, instructions are commonly referred to in terms of bytes rather than words.

One-Byte Instructions
A 1-byte instruction includes the opcode and operand in the same byte. Operand(s)
are internal register and are coded into the instruction
For example:
Task Opcode Operand Binary Hex
Code Code

Copy the contents of the accumulator in MOV C,A 0100 1111 4FH
the register C.

Add the contents of register B to the ADD B 1000 0000 80H

contents of the accumulator.

Invert (compliment) each bit in the CMA 0010 1111 2FH

accumulator.

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These instructions are 1-byte instructions performing three different tasks. In the first instruction,
both operand registers are specified. In the second instruction, the operand B is specified and the
accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the
implicit operand. These instructions are stored in 8- bit binary format in memory; each requires
one memory location.

MOV rd, rs
rd <-- rs copies contents of rs into rd.
Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the
destination of the data, sss is the code of the source register.

Example: MOV A,B

Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction design of such
processors).

ADD r
A <-- A + r

Two-Byte Instructions
In a two-byte instruction, the first byte specifies the operation code and the second byte specifies
the operand. Source operand is a data byte immediately following theopcode.
For example

Task Opcode Operand Binary Hex Code

Code

Load an 8-bit MVI A, Data 0011 1110 3E First Byte

data Data Second Byte
byte in the DATA
accumulator.

Assume that the data byte is 32H. The assembly language instruction is written as

Mnemonics Hex code

MVI A, 32H 3E 32H

The instruction would require two memory locations to store in memory.

MVI r,data
r <-- data

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Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is an example of
immediate addressing.
ADI data
A <-- A + data
OUT port

where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but points
directly to where it is located this is called direct addressing.

Three-Byte Instructions
In a three-byte instruction, the first byte specifies the opcode, and the following two bytes
specify the 16-bit address. Note that the second byte is the low-order address and the third byte is
the high-order address.
opcode + data byte + data byte
For example:

Task Opcode Operand Binary code Hex Code

Transfer the JMP 2085H 1100 0011 C3 First byte

program 85 Second Byte
sequence to 1000 0101 20 Third Byte
the memory
location 0010 0000
2085H.

This instruction would require three memory locations to store in memory.

Three byte instructions - opcode + data byte + data byte

LXI rp, data16

rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data
bytes are 16-bit data in L H order of significance.
rp <-- data16

Example:
LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate addressing.

LDA addr

A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as 3AH 34H
21H. This is also an example of direct addressing.

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7.Write some assembly language programming?

ASSEMBLY LANGUAGE PROGRAMMING

1. Write an assembly program to add two numbers

Program
MVI D, 8BH
MVI C, 6FH
MOV A, C
1100 0011
1000 0101
0010 0000
ADD D
OUT PORT1
HLT

2. Write an assembly program to multiply a number by 8

Program
MVI A, 30H
RRC
RRC
RRC
OUT PORT1
HLT
3. Write an assembly program to find greatest between two numbers
Program
MVI B, 30H
MVI C, 40H
MOV A, B
CMP C
JZ EQU
JC GRT
OUT PORT1
HLT
EQU: MVI A, 01H
OUT PORT1
HLT
GRT: MOV A, C
OUT PORT1
HLT

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8.Explain how to model the program?

The 8085 Programming Model

In the previous tutorial we described the 8085 microprocessor registers in reference to the
internal data operations. The same information is repeated here briefly to provide the continuity
and the context to the instruction set and to enable the readers who prefer to focus initially on the
programming aspect of the microprocessor.

The 8085 programming model includes six registers, one accumulator, and one flag register, as
shown in Figure. In addition, it has two 16-bit registers: the stack pointer

ACCUMULATOR A (8) FLAG REGISTER

B (8) C (8)
D (8) E (8)
H (8) L (8)
Stack Pointer (SP) (16)
Program Counter (PC) (16)
Data Bus Address Bus
8 Lines Bidirectional 16 Lines unidirectional
Registers
The 8085 has six general-purpose registers to store 8-bit data; these are identified as B,C,D,E,H,
and L as shown in the figure. They can be combined as register pairs - BC, DE, and HL – to
perform some 16-bit operations. The programmer can use these registers to store or copy data
into the registers by using data copy instructions.
Accumulator
The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is
used to store 8-bit data and to perform arithmetic and logical operations. The result of an
operation is stored in the accumulator. The accumulator is also identified as register A.
Flags
The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; their bit positions in the flag register
are shown in the Figure below. The most commonly used flags are Zero, Carry, and Sign. The
microprocessor uses these flags to test data

D7 D6 D5 D4 D3 D2 D1
D0
S Z AC P CY

For example, after an addition of two numbers, if the sum in the accumulator id larger than eight
bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When an
arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first
Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it
is not used as a register; five bit positions out of eight are used to store the outputs of the five
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flip-flops. The flags are stored in the 8-bit register so that the programmer can examine these
flags (data conditions) by accessing the register through an instruction.

These flags have critical importance in the decision-making process of the microprocessor. The
conditions (set or reset) of the flags are tested through the software instructions. For example, the
instruction JC (Jump on Carry) is implemented to change the sequence of a program when CY
flag is set. The thorough understanding of flag is essential in writing assembly language
programs.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit
register.

The microprocessor uses this register to sequence the execution of the instructions. The function
of the program counter is to point to the memory address from which the next byte is to be
fetched. When a byte (machine code) is being fetched, the program counter is incremented by
one to point to the next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-
bit address in the stack pointer.

This programming model will be used in subsequent tutorials to examine how these registers are
affected after the execution of an instruction.

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INTERRUPTS VECTOR
ADDRESS

RST 0 0000H

RST 1 0008H

RST 2 0010H

RST 3 0018H

RST 4 0020H

RST 5 0028H

RST 6 0030H

RST 7 0038H

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UNIT 2
1.Explain detail about the software interrupt of 8085?

SOFTWARE INTERRUPTS OF 8085:

1.The software instructions are program instructions. When a software interrupt instruction is
executed , the processor executes an interrupt service subroutine ( ISR ) stored in the vector
address of that software interrupt instruction.
2.The software interrupts of 8085 are RSR 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6 and
RST 7 . The software interrupts of 8085 are vectored interrupts. The software interrupts cannot
be masked and they cannot be disabled.
3.The vector addresses of software interrupt are given in the table.
4.The software interrupt instructions are included at the appropriate ( or required ) place in the
main program.
5.When the processor encounters the software instruction , it pushes the content of the PC
( program counter ) to stack.
6.Then loads the vector address in PC and starts executing an ISR stored in this address.
7.The last instruction of ISR will be RET instruction. When the RET instruction is executed, the
8.processor POP the content of the top of stack to PC.
Hence the processor control returns to the main program after receiving the interrupt.

2.Explain about the hardware interrupt of 8085?

HARDWARE INTERRUPTS OF 8085:

INTERRUPT VECTOR
S ADDRESS

RST 7.5 003CH

RST 6.5 0034H

RST 5.5 002CH

TRAP 0024H
The hardware interrupts of 8085 are initiated by an external
device by placing an appropriate signal at the interrupt pin of the processor.

 The processor keeps on checking the interrupt pins at the second T-state of
last machine cycle of every instruction.

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 If the processor finds a valid interrupt signal and if the interrupt is unmasked
and enabled; then the processor accepts the interrupt. The acceptance of the
hardware interrupt is acknowledged by sending an INTA signal to the
interrupting device.
 When the interrupt is accepted; the processor saves the content of PC into the
stack.
 The hardware interrupts of 8085 are TRAP , RST 7.5, RST 6.5, RST 5.5 and
INTR . Except INTR all are vectord interrupts.
 In vectored interrupts the address to which the program control is transferred
is fixed by the manufacturer.
 The vector addresses of hardware interrupts are given in table.
 TRAP is edge and level sensitive.Hence to initiate TRAP, the interrupt signal
has to make a low to high transition and then it has to remain high until the
interrupt is recognized.
 The RST 7.5 is edge sensitive. , and in order to initiate it ,the interrupt signal
has to make a low to high transition and then it need not remain high until
the interrupt is recognized.
 The RST 7.5, RST 6.5, RST 5.5 and INTR are level sensitive. Hence these
interrupts should remain high, until it is recognized.
 The Trap is non maskable interrupt and RST 7.5, RST 6.5, RST 5.5 are
maskable interrupt using SIM instruction. The status of maskable interrupts
can be read into the accumulator by executing RIM instruction.
 All the interrupts except TRAP are disabled when the processor is resetted or
can also be disabled by executing DI instruction.
 In order to enable them the processor has to execute EI instruction.

3.Explain briefly about the data transfer techniques?

DATA TRANSFER TECHNIQUES

The data transfer technique refers to the method of data transfer between the processor and
peripheral devices. In a typical microcomputer, data transfer takes place between any two
devices:

 Microprocessor and memory

 Microprocessor and I/O devices
 Memory and I/O devices
For effective data transfer between these devices, the timing parameters of the devices should be
matched.

TYPES OF DATA TRANSFER:-The data transfer technique have been broadly classified into
the following two categories;

 Programmed data transfer

 Direct memory access (DMA) data transfer

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Data Transfer

Programmed data transfer Direct memory Access

(DMA)

Synchronous Asynchronous Cycle

Block
Stealing
transfer mode
DMA
DMA
Interrupt driven

Polled Interrupts Vectored interrupts

Software Hardware Fixed Variable

Polling Polling Priority Priority
PROGRAMMED DATA TRANSFER:

In programmed data transfer, a memory resident request the device for data transfer to or
from one of the processor register. It is used when relatively small amount of data are to be
transferred. They can be further classified into the following three types;

 Synchronous data transfer

 Asynchronous data transfer

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 Interrupt driven data transfer

SYNCHRONOUS DATA TRANSFER:-

The synchronous data transfer scheme is the simplest of all data transfer schemes. In this
scheme the processor does not check the readiness of the devices. The I/O device or peripheral
should have matched timing parameters. Whenever data is to be obtained from the device or
transferred to the device, the user program can issue a suitable instruction for the device. At the
end of he execution of this instruction, the transfer would have been completed.

Request device to
Get ready

Perform any other task

Until the device
Is ready

Execute input/output
instruction

Synchronous data Transfer scheme

ASYNCHRONOUS DATA TRANSFER:-

The asynchronous data transfer scheme is employed when the speed of the processor and I/O
devices does not match. In this scheme the processor sends a request to the device for read/write
operation. Then the processor keeps on polling the status of the devices. Once the device is
ready, the processor execute a data transfer instruction to complete the process

INTERRUPT DRIVEN DATA TRANSFER:-

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The interrupt driven data transfer scheme is the best method of data transfer for efficient
utilization of processor time. In this scheme, the processor first initiates the I/O device for data
transfer. After initiating the device, the processor will continue the execution of instructions in
the program. Also at the end of every instruction the processor will check for a valid interrupt
signal. If there is no interrupt then the processor will continue the execution.

When the I/O device is ready, it will interrupt the processor. On receiving an interrupt
signal the processor will complete the current instruction execution and save the processor status
in stack. Then the processor call an Interrupt Service Routine (ISR) to service the interrupting
device. At the end of ISR, the processor status is retrieved from the stack and the processor starts
executing its main program.

Start ISR
Request
device to
get ready
Save processor
Status
Fetch next
instruction
And execute

Execute data transfer

Check for instructions
Interrupt
No
Restore processor status

Call ISR
associated
Yes
With this Enable interrupt system
interrupt
Call ISR associated
With this interrupt

Return main program

Main program execution sequence. ISR execution sequence

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DMA DATA TRANSFER:-

Normally the data transfer from memory to I/O device or I/O device to memory can be achieved
only through microprocessor. When data has to be transferred from memory to I/O device, first
the processor send address and control signals to memory to read the data from memory. Then
the processor send address and control signals to I/O device to write data to I/O device.
Similarly, the data can be transferred from I/O device to memory.

In the data transfer method described above, the data cannot be directly transferred between
memory and I/O devices, even though they are connected to common bus. This process is
inevitable, because the processor cannot simultaneously select two devices. Hence a scheme
called DMA have been developed in which the I/O device can access the memory directly for
data transfer. The DMA data transfer will be useful to transfer large amount of data between
memory and I/O device in a short time.

The modes of DMA operations are two types;

 Burst mode
 Cycle stealing
BURST MODE DATA TRANSFER:-

As bus control is granted to the device controller, it continues with the controller till the data
transfer is completed. After all the data has been transferred, the device interrupts the processor
to indicate the completion to the user program. During this period the microprocessor is idling
and it is in hold state. The microprocessor exits from this state only after an interrupt is received
or after the DMA request is withdrawn by the peripheral device. The duration of HOLD depends
on I/O device speed, the memory speed and the number of bytes transferred. This type of DMA
transfer is known as burst mode data transfer.

CYCLE STEALING DATA TRANSFER:-

The I/O device uses the concept of cycle stealing. The I/O device requests the processor
for DMA cycle. When request is granted a byte or a word is transferred and DMA request is
withdrawn. After sometime, when the device is again ready for data transfer, it repeats the above
process. Finally when the last data byte has been transferred, the device interrupts the processor
indicating the end of the requested I/O operation. This type of DMA access is cycle stealing data
transfer.

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4.Explian briefly about DMA?

Direct Memory Access (DMA)

Tri state devices:

 3 output states are high & low states and additionally a high impedance state.
 When enable E is high the gate is enabled and the output Q can be 1 or 0 (if A is 0, Q is
1, otherwise Q is 0). However, when E is low the gate is disabled and the output Q enters
into a high impedance state.

Fig (a) - Pin Diagram of 8085 & Fig(b) - logical schematic of Pin diagram.

 For both high and low states, the output Q draws a current from the input of the OR gate.
 When E is low, Q enters a high impedance state; high impedance means it is electrically
isolated from the OR gate's input, though it is physically connected. Therefore, it does not
draw any current from the OR gate's input.
 When 2 or more devices are connected to a common bus, to prevent the devices from
interfering with each other, the tristate gates are used to disconnect all devices except the
one that is communicating at a given instant.
 The CPU controls the data transfer operation between memory and I/O device. Direct
Memory Access operation is used for large volume data transfer between memory and an
I/O device directly.
 The CPU is disabled by tri-stating its buses and the transfer is effected directly by
external control circuits.
 HOLD signal is generated by the DMA controller circuit. On receipt of this signal, the
microprocessor acknowledges the request by sending out HLDA signal and leaves out the
control of the buses. After the HLDA signal the DMA controller starts the direct transfer
of data.

READY (input)

 Memory and I/O devices will have slower response compared to microprocessors.

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 Before completing the present job such a slow peripheral may not be able to handle
further data or control signal from CPU.
 The processor sets the READY signal after completing the present job to access the data.
 The microprocessor enters into WAIT state while the READY pin is disabled.

Single Bit Serial I/O ports:

 SID (input) - Serial input data line

 SOD (output) - Serial output data line
 These signals are used for serial communication.

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UNIT 3
1.Write notes on Interfacing Types

There are two types of interfacing in context of the 8085 processor.

Memory Interfacing.

I/O Interfacing.

Memory Interfacing:

While executing an instruction, there is a necessity for the microprocessor to access memory
frequently for reading various instruction codes and data stored in the memory. The interfacing
circuit aids in accessing the memory.Memory requires some signals to read from and write to
registers. Similarly the microprocessor transmits some signals for reading or writing a data.The
interfacing process involves matching the memory requirements with the microprocessor signals.
The interfacing circuit therefore should be designed in such a way that it matches the memory
signal requirements with the signals of the microprocessor. For example for carrying out a
READ process, the microprocessor should initiate a read signal which the memory requires to
read a data. In simple words, the primary function of a memory interfacing circuit is to aid the
microprocessor in reading and writing a data to the given register of a memory chip.

I/O Interfacing:

We know that keyboard and Displays are used as communication channel with outside world. So
it is necessary that we interface keyboard and displays with the microprocessor. This is called
I/O interfacing. In this type of interfacing we use latches and buffers for interfacing the
keyboards and displays with the microprocessor.But the main disadvantage with this interfacing
is that the microprocessor can perform only one function. It functions as an input device if it is
connected to buffer and as an output device if it is connected to latch. Thus the capability is very
limited in this type of interfacing.

2.Give some microprocessor applications

The 4 bit microprocessor applications

The 4 bit microprocessors are very good for low-cost and simple applications. Students will
find the 4 bit microprocessor in

- Toy : robots, remote-controlled cars, hand held games

- Calculators : financial, scientific, database
- Power tool controllers : speed controls, sequencers, measurement devices
- Simple : microwave ovens, telephone dialers, smart thermostats, shortwave scanners, TV
remote controls
- Computer peripherals : keyboard scanners, simple printers, clocks

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The 8 bit microprocessor applications

- Toys : video games, programmable robots

- Complex intelligent product controllers : VCR control and programming, security
systems, lighting system controllers
- Computer peripherals: video display, higher-speed printers. Modems, plotters,
communication controllers.
- Industrial controllers : robotics, processing control, sequence control, machine tool
control
- Instruments : logic analyzers, communication analyzers, disk drive testers, digital
oscilloscopes, smart voltmeters
The 16 bit, 32 bit and 64 bit microprocessors are frequency found in graphic oriented CAD
and CAM systems. The 32 bit and 64 bit microprocessors feature very fast operation, extreme
computing power, and megabytes, or even gigabytes, of main memory-addressing space.

3. Write notes on Memory

Memory is and essential component of microcomputer system; it stores binary
instructions and data for the microprocessor. They can be classified in two groups: prime (or
main) memory and storage memory. The R/W memory is made up of registers, and each register
can use this memory to hold programs and store data. On the other hand, the ROM stores
information permanently in the form of diodes.

Flip-Flop or Latch as a Storage Element.

It is a circuit that can store bits. A flip-flop or latch is a basic element of memory. To
write or store a bit in the latch, we need an input data bit and an enable signal.

This latch, which can store one binary bit, is called a memory cell.

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Figure shows four latches as a 4 bit Register. The number of bits stored in a register is called a
memory word.

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The requirements of a memory chip.

1. A memory chip requires address lines to identify a memory register, a chip select CS
signal.
2. The number of address lines required is determined by the number of registers in a chip
(2n)
3. If additional address lines are available in a system, chip select signal is used.
4. The control signal Read (RD ) enables the output buffer. The control signal Write ( WR )
enables the input buffer.

Memory Map and Address

Typically, in an 8- bit microprocessor system, 16 address lines are available for memory. It is
capable of identifying 216 (65,536) memory registers, each register with a 16 bit address. The
entire memory addresses can range from 0000 to FFFF in Hex.

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How the MPU writes into and Reads from Memory.

1. Places the 16 bit address on the address of the memory location where a byte is to be
stored. The interfacing logic of the memory chip decodes the address and selects the
memory register to be written into.
2. Places the byte on the data bus.
3. Send the control signal Memory. Write to enable the input buffer of the memory and then
stores the byte.
To read from memory the step are similar to that of writing into memory, except the order of
step 2 and 3.

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2. The MPU send the control signal Memory Read to enable the output buffer of the
memory chip.
3. The memory chip places the data byte on the data bus, and the MPU reads the data byte

4. Write notes on Input and Output (I/O) Devices

Input/output devices are the means through which the MPU communications with “the
outside world”. The MPU accepts binary data as input from devices such as keyboards and A/D
converters and sends data to output devices such as LEDs or printers.

There are two different methods by which an MPU can identify I/O devices:

o 8 bit address
o 16 bit address
I/Os with 8-bit Addresses (Peripheral-Mapped I/O)

The MPU uses eight address lines to identify an input or an output device. The MPU can
identify 256 input and 256 output devices with addresses ranging from 00H to FFH.

The steps in communicating with I/O device can be summarized as follows:

1. The MPU places an 8 bit address on the address bus, which is decodes by the external
decode logic.
2. The MPU sends a control signal (I/O Read or I/O Write) to enable the I/O device.
3. Data are transferred on the data bus.
I/Os with 16 bit Addresses (Memory-Mapped I/O)

The MPU uses 16 address lines to identify an I/O device; an I/O is connected as if it is a
memory register. In memory-mapped I/O, the MPU uses the same control signals (Memory Read
or Memory Write) and instructions as there of memory and follows the same steps as when it is
accessing a memory register.
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How does the system work?

In figure above let us assume that the memory address of the first R/W memory location
is 8000H and the address of the fan output port is 43H.

The example of the two byte instruction that tells the processor to turn on the fan with the
address 43H.

Memory Hex Code Code explanation

8000 D3 Out put (turn on)

8001 43 The fan

To execute this one instruction, the MPU performs the following operations.

1. MPU must read the binary code of the out instruction stored in location 8000H. To read
the code D3, the MPU places the address 8000H on the address bus, enables the memory
chip by asserting the Memory Read (MEMRD ) signal, and fetches the code D3H using
the data bus. This is called the fetch operation.
2. The code D3H in the instruction decoder and it is interpreted as a two-byte instruction.
The MPU places the next address 8001H on the address bus, asserts the MEMRD signal,
and fetches the address 43H. Now it has read the complete instruction, and is ready to
execute the instruction.
3. The MPU places the address of the fan output port (43H) on the address bus, sends a byte
to turn on the fan using the data bus, and asserts the IOWR signal to enable the output
port.

5.Explain the concept of serial communication

In telecommunication and computer science, the concept of serial communication is the
process of sending data one bit at a time, sequentially, over a communication channel or
computer bus. This is in contrast to parallel communication, where several bits are sent as a
whole, on a link with several parallel channels. Serial communication is used for all long-haul
communication and most computer networks, where the cost of cable and synchronization
difficulties make parallel communication impractical. Serial computer buses are becoming more
common even at shorter distances, as improved signal integrity and transmission speeds in newer
serial technologies have begun to outweigh the parallel bus's advantage of simplicity (no need for
serializer and deserializer, or SerDes) and to outstrip its disadvantages (clock skew, interconnect
density).

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EXAMPLES OF SERIAL COMMUNICATION ARCHITECTURES

 Morse codetelegraphy
 RS-232 (low-speed, implemented by serial ports)
 RS-422
 RS-423
 RS-485
 I²C
 SPI
 ARINC 818 Avionics Digital Video Bus
 Universal Serial Bus (moderate-speed, for connecting peripherals to computers)
 FireWire
 Ethernet

6.Explain 8251 Universal Synchronous Asynchronous Receiver Transmitter

(Usart)

The 8251 is a USART (Universal Synchronous Asynchronous Receiver Transmitter) for serial
data communication. As a peripheral device of a microcomputer system, the 8251 receives
parallel data from the CPU and transmits serial data after conversion. This device also receives
serial data from the outside and transmits parallel data to the CPU after conversion.

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Block diagram of the 8251 USART (Universal Synchronous Asynchronous Receiver

Transmitter)

The 8251 functional configuration is programmed by software. Operation between the 8251 and
a CPU is executed by program control. Table 1 shows the operation between a CPU and the
device.

Table 1 Operation between a CPU and 8251

Control Words

There are two types of control word.

1. Mode instruction (setting of function)

2. Command (setting of operation)

1) Mode Instruction

Mode instruction is used for setting the function of the 8251. Mode instruction will be in "wait
for write" at either internal reset or external reset. That is, the writing of a control word after
resetting will be recognized as a "mode instruction."Items set by mode instruction are as follows:

• Synchronous/asynchronous mode

• Stop bit length (asynchronous mode)

• Character length

• Parity bit

• Baud rate factor (asynchronous mode)

• Internal/external synchronization (synchronous mode)

• Number of synchronous characters (Synchronous mode)

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The bit configuration of mode instruction is shown in Figures 2 and 3. In the case of synchronous
mode, it is necessary to write one-or two byte sync characters. If sync characters were written, a
function will be set because the writing of sync characters constitutes part of mode instruction.

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2) Command

Command is used for setting the operation of the 8251. It is possible to write a command
whenever necessary after writing a mode instruction and sync characters.Items to be set by
command are as follows:

• Transmit Enable/Disable

• Receive Enable/Disable

• DTR, RTS Output of data.

• Resetting of error flag.

• Sending to break characters

• Internal resetting

• Hunt mode (synchronous mode)

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Status Word

It is possible to see the internal status of the 8251 by reading a status word. The bit configuration
of status word is shown in Figure

Pin Description

D 0 to D 7 (l/O terminal)

This is bidirectional data bus which receives control words and transmits data from the CPU and
sends status words and received data to CPU.

RESET (Input terminal)

A "High" on this input forces the 8251 into "reset status." The device waits for the writing of
"mode instruction." The min. reset width is six clock inputs during the operating status of CLK.

CLK (Input terminal)

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CLK signal is used to generate internal device timing. CLK signal is independent of RXC or
TXC. However, the frequency of CLK must be greater than 30 times the RXC and TXC at
Synchronous mode and Asynchronous "x1" mode, and must be greater than 5 times at
Asynchronous "x16" and "x64" mode.

WR (Input terminal)

This is the "active low" input terminal which receives a signal for writing transmit data and
control words from the CPU into the 8251.

RD (Input terminal)

This is the "active low" input terminal which receives a signal for reading receive data and status
words from the 8251.

C/D (Input terminal)

This is an input terminal which receives a signal for selecting data or command words and status
words when the 8251 is accessed by the CPU. If C/D = low, data will be accessed. If C/D = high,
command word or status word will be accessed.

CS (Input terminal)

This is the "active low" input terminal which selects the 8251 at low level when the CPU
accesses. Note: The device won’t be in "standby status"; only setting CS = High.

TXD (output terminal)

This is an output terminal for transmitting data from which serial-converted data is sent out. The
device is in "mark status" (high level) after resetting or during a status when transmit is disabled.
It is also possible to set the device in "break status" (low level) by a command.

TXRDY (output terminal)

This is an output terminal which indicates that the 8251is ready to accept a transmitted data
character. But the terminal is always at low level if CTS = high or the device was set in "TX
disable status" by a command. Note: TXRDY status word indicates that transmit data character is
receivable, regardless of CTS or command. If the CPU writes a data character, TXRDY will be
reset by the leading edge or WR signal.

TXEMPTY (Output terminal)

This is an output terminal which indicates that the 8251 has transmitted all the characters and had
no data character. In "synchronous mode," the terminal is at high level, if transmit data
characters are no longer remaining and sync characters are automatically transmitted. If the CPU
writes a data character, TXEMPTY will be reset by the leading edge of WR signal. Note : As the

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transmitter is disabled by setting CTS "High" or command, data written before disable will be
sent out. Then TXD and TXEMPTY will be "High". Even if a data is written after disable, that
data is not sent out and TXE will be "High".After the transmitter is enabled, it sent out. (Refer to
Timing Chart of Transmitter Control and Flag Timing)

TXC (Input terminal)

This is a clock input signal which determines the transfer speed of transmitted data. In
"synchronous mode," the baud rate will be the same as the frequency of TXC. In "asynchronous
mode", it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16 or 1/64
the TXC. The falling edge of TXC sifts the serial data out of the 8251.

RXD (input terminal)

This is a terminal which receives serial data.

RXRDY (Output terminal)

This is a terminal which indicates that the 8251 contains a character that is ready to READ. If the
CPU reads a data character, RXRDY will be reset by the leading edge of RD signal. Unless the
CPU reads a data character before the next one is received completely, the preceding data will be
lost. In such a case, an overrun error flag status word will be set.

RXC (Input terminal)

This is a clock input signal which determines the transfer speed of received data. In
"synchronous mode," the baud rate is the same as the frequency of RXC. In "asynchronous
mode," it is possible to select the baud rate factor by mode instruction. It can be 1, 1/16, 1/64 the
RXC.

SYNDET/BD (Input or output terminal)

This is a terminal whose function changes according to mode. In "internal synchronous mode."
this terminal is at high level, if sync characters are received and synchronized. If a status word is
read, the terminal will be reset. In "external synchronous mode, "this is an input terminal. A
"High" on this input forces the 8251 to start receiving data characters.

In "asynchronous mode," this is an output terminal which generates "high level"output upon the
detection of a "break" character if receiver data contains a "low-level" space between the stop
bits of two continuous characters. The terminal will be reset, if RXD is at high level. After Reset
is active, the terminal will be output at low level.

DSR (Input terminal)

This is an input port for MODEM interface. The input status of the terminal can be recognized
by the CPU reading status words.

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DTR (Output terminal)

This is an output port for MODEM interface. It is possible to set the status of DTR by a
command.

CTS (Input terminal)

This is an input terminal for MODEM interface which is used for controlling a transmit circuit.
The terminal controls data transmission if the device is set in "TX Enable" status by a command.
Data is transmitable if the terminal is at low level.

RTS (Output terminal)

This is an output port for MODEM interface. It is possible to set the status RTS by a command.

7. Write Notes On8255 Programmable Peripheral Interface 255 PPI Chip

The 8255 Programmable Peripheral Interface(PPI)
• It is one of the most widely used I/O chips.
• It has three separately accessible ports: A, B,and C
• The individual ports can be programmed to beinput or output.
• Port A (PA0-PA7) -> all inputs or all outputs.
• Port B (PB0-PB7) -> all inputs or all outputs.
• Port C (PC0-PC7) -> all inputs or all outputs orcan be programmed individually.
• CU : upper bits (PC4-PC7)
• CL : lower bits (PC0-PC3)

Pin diagram

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Diagram of the 8255

BLBLOCK DIAGRAM

I/O Modes Of 8255 I/O Mode of the 8255

ADDRESSING OF 8255

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8255 INTERFACING WITH LCD

7.Write notes on Programmable Keyboard/Display Interface - 8279

A programmable keyboard and display interfacing chip.
Scans and encodes up to a 64-key keyboard.
Controls up to a 16-digit numerical display.
Keyboard has a built-in FIFO 8 character buffer.
The display is controlled from an internal 16x8 RAM that stores the coded display information.

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Pinout Definition 8279

 A0: Selects data (0) or control/status (1) for reads and writes between micro and 8279.
 BD: Output that blanks the displays.
 CLK: Used internally for timing. Max is 3 MHz.
 CN/ST: Control/strobe, connected to the control key on the keyboard.
 CS: Chip select that enables programming, reading the keyboard, etc.
 DB7-DB0: Consists of bidirectional pins that connect to data bus on micro.
 IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.
 OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least significant
nibble of display.
 RD(WR): Connects to micro's IORC or RD signal, reads data/status registers.
 RESET: Connects to system RESET.
 RL7-RL0: Return lines are inputs used to sense key depression in the keyboard matrix.
 Shift: Shift connects to Shift key on keyboard.
 SL3-SL0: Scan line outputs scan both the keyboard and displays.

8. What is RS232?

RS232 is a popular communications protocol for connecting modems and data acquisition
devices to computers. RS232 devices can be plugged straight into the computer's serial port
(also known as the COM or Comms port). Examples of data acquisition devices include
GPS receivers, electronic balances, data loggers, temperature interfaces and other
measurement instruments.

The RS232 Standard

RS stands for recommended standard. In the 60's a standards committee now known as the
Electronic Industries Association developed an interface to connect computer terminals to
modems. Over the years this has been updated: the most commonly used version of the
standard is RS232C (sometimes known as EIA232); the most recent is RS232E. The
standard defines the electrical and mechanical characteristics of the connection - including
the function of the signals and handshake pins, the voltage levels and maximum bit rate.

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That's a good question. The answer is that the RS232 standard was created for just one
specific situation and the difficulties come when it is used for something else. The standard
was defined to connect computers to modems. Any other use is outside of the standard. The
authors of the standard had in mind the situation below:

The standard defines how computers ( it calls them Data Terminal Equipment or DTEs)
connect to modems ( it calls them Data Communication Equipment or DCEs). The standard
says that computers should be fitted with a 25 way plug whilst modems should have a 25
way D socket. The interconnecting lead between a computer and a modem should be simply
pin1—pin1, pin2—pin2, etc. The main signals and their direction of flow are described
below. It is important to note that a signal which is an output from a computer is an input to
a modem and vice versa. This means that you can never tell from the signal name alone
whether it is an input or an output from a particular piece of equipment. Also, instead of
being a DCE device, a data acquisition device might be configured as DTE. In this case you
need an adaptor or the RS232 cable wired differently to normal. When the PC is connected
to a DTE instrument, some of the cable wires must cross over.

TXD Transmitted Data, Pin 2 of 25 way D

This is the serial encoded data sent from a computer to a modem to be transmitted over
the telephone line.

RXD Received Data, Pin 3 of 25 way D

This is the serial encoded data received by a computer from a modem which has in turn
received it over the telephone line.

DSR Data Set Ready, Pin 6 of 25 way D

This should be set true by a modem whenever it is powered on. It can be read by the
computer to determine that the modem is on line.

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DTR Data Terminal Ready, Pin 20 of 25 way D

This should be set true by a computer whenever it is powered on. It can be read by the
modem to determine that the computer is on line.

RTS Request to Send, Pin 4 of 25 way D

This is set true by a computer when it wishes to transmit data.

CTS Clear To Send, Pin 5 of 25 Way D

This is set true by a modem to allow the computer to transmit data. The standard envisaged
that when a computer wished to transmit data it would set its RTS. The local modem would
then arbitrate with the distant modem for use of the telephone line. If it succeeded it would
set CTS and the computer would transmit data. The distant modem would use its CTS to
prevent any transmission by the distant computer.

DCD Data Carrier Detect, Pin 8 of 25 Way D

This is set true by a modem when it detects the data carrier signal on the telephone line.

PC Serial Ports
A nine pin D plug has become the standard fitting for the serial ports of PCs, although it's
nothing to do with the RS232 standard. The pin connections used are:

Pin Direction Signal

1 Input DCD Data Carrier Detect
2 Input RXD Received Data
3 Output TXD Transmitted Data
4 Output DTR Data Terminal Ready
5 Signal Ground
6 Input DSR Data Set Ready
7 Output RTS Request To Send
8 Input CTS Clear To Send
9 Input RI Ring Indicator
How Fast Can Instruments send data over RS232?

The speed of RS232 communications is expressed in Baud. The unit is named after Jean
Maurice-Emile Baudot (1845-1903), a French telegraph engineer and the inventor of the
first teleprinter. It was proposed at the International Telegraph Conference of 1927. The
maximum speed, according to the standard, is 20000 Baud. However, modern equipment
can operate much faster than this. No matter how fast (or slow) your connection - the
maximum number of readings per second you can take from your instrument depends on the
software. The length of the cable also plays a part in maximum speed. The longer the cable,
the greater the cable's capacitance and the slower the speed at which you can obtain
accurate results. A large capacitance means voltage changes on one signal wire may be
transmitted to an adjacent signal wire. Fifty feet is commonly quoted as the maximum
distance, but this is not specified in the standard.

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UNIT 4
1. Give In Detail The Evolution From 8080/8085 To 8086

􀂾 Intel introduced 8086 microprocessor in 1978. This 16-bit microprocessor was a major improvement
over the previous generation of 8080/8085 series of microprocessors.

Overview or Features of 8086

 It is a 16-bit Microprocessor(μp).It’s ALU, internal registers works with 16bit binary word.
 8086 has a 20 bit address bus can access up to 220= 1 MB memory locations.
 8086 has a 16bit data bus. It can read or write data to a memory/port either 16bits or 8 bit at a
time.
 It can support up to 64K I/O ports.
 It provides 14, 16 -bit registers.
 Frequency range of 8086 is 6-10 MHz
 It has multiplexed address and data bus AD0- AD15 and A16 – A19.
 It requires single phase clock with 33% duty cycle to provide internal timing.
 It requires +5V power supply.
 8086 is designed to operate in two modes, Minimum mode and Maximum mode.
o The minimum mode is selected by applying logic 1 to the MN / MX# input pin. This is a
single microprocessor configuration.
o The maximum mode is selected by applying logic 0 to the MN / MX# input pin. This is a
multi micro processors configuration.

2. Explain the Architecture of 8086 / Functional Block diagram of 8086

 8086 has two blocks Bus Interfacing Unit(BIU) and Execution Unit(EU).

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 The BIU performs all bus operations such as instruction fetching, reading and writing operands
for memory and calculating the addresses of the memory operands. The instruction bytes are
transferred to the instruction queue.

 EU executes instructions from the instruction system byte queue.

 Both units operate asynchronously to give the 8086 an overlapping instruction fetch and
execution mechanism which is called as Pipelining. This results in efficient use of the system bus
and system performance.

 BIU contains Instruction queue, Segment registers, Instruction pointer, Address adder.

 EU contains Control circuitry, Instruction decoder, ALU, Pointer and Index register,Flag register.

BUS INTERFACE UNIT:

 It provides a full 16 bit bidirectional data bus and 20 bit address bus.

 The bus interface unit is responsible for performing all external bus operations.

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 Specifically it has the following functions:

 Instruction fetch Instruction queuing, Operand fetch and storage, Address relocation and Bus
control.

 The BIU uses a mechanism known as an instruction stream queue to implement pipeline
architecture.

 This queue permits prefetch of up to six bytes of instruction code. When ever the queue of the
BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the program
by perfecting the next sequential instruction.

 These perfecting instructions are held in its FIFO queue. With its 16 bit data bus, the BIU fetches
two instruction bytes in a single memory cycle.

 After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to
the empty location nearest the output.

 The EU accesses the queue from the output end. It reads one instruction byte after the other from
the output of the queue. If the queue is full and the EU is not requesting access to operand in
memory.

 These intervals of no bus activity, which may occur between bus cycles are known as Idle state.

 If the BIU is already in the process of fetching an instruction when the EU request it to read or
write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle
before initiating the operand read / write cycle.

 The BIU also contains a dedicated adder which is used to generate the 20bit physical address that
is output on the address bus. This address is formed by adding an appended 16 bit segment
address and a 16 bit offset address.

 For example: The physical address of the next instruction to be fetched is formed by combining
the current contents of the code segment CS register and the current contents of the instruction
pointer IP register.

EXECUTION UNIT

 The Execution unit is responsible for decoding and executing all instructions.

 The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write bys
cycles to memory or I/O and perform the operation specified by the instruction on the operands.

 During the execution of the instruction, the EU tests the status and control flags and updates them
based on the results of executing the instruction.

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 If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of
the queue.

 When the EU executes a branch or jump instruction, it transfers control to a location

corresponding to another set of sequential instructions.

 Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.

General purpose registers

The 8086 microprocessor has a total of fourteen registers that are accessible to the programmer.
It is divided into four groups. They are:

 Four General purpose registers

 Four Index/Pointer registers
 Four Segment registers
 Two Other registers

General purpose registers:

Accumulator register consists of two 8-bit registers AL and AH, which can be combined
together and used as a 16-bit register AX. AL in this case contains the loworder byte of the word,
and AH contains the high-order byte. Accumulator can be used for I/O operations and string
manipulation.

Base register consists of two 8-bit registers BL and BH, which can be combined together and
used as a 16-bit register BX. BL in this case contains the low-order byte of the word, and BH
contains the high-order byte. BX register usually contains a data pointer used for based, based
indexed or register indirect addressing.

Count register consists of two 8-bit registers CL and CH, which can be combined together and
used as a 16-bit register CX. When combined, CL register contains the loworder byte of the
word, and CH contains the high-order byte. Count register can be used in Loop, shift/rotate
instructions and as a counter in string manipulation

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Data register consists of two 8-bit registers DL and DH, which can be combined together and
used as a 16-bit register DX. When combined, DL register contains the low order byte of the
word, and DH contains the high-order byte. Data register can be used as a port number in I/O
operations. In integer 32-bit multiply and divide instruction the DX register contains high-order
word of the initial or resulting number.

3. Explain the Pin Diagram of 8086 and Pin description of 8086

Figure shows the Pin diagram of 8086. The description follows it.

 The Microprocessor 8086 is a 16-bit CPU available in different clock rates and packaged in a 40
pin CERDIP or plastic package.
 The 8086 operates in single processor or multiprocessor configuration to achieve high
performance. The pins serve a particular function in minimum mode (single processor mode ) and
other function in maximum mode configuration (multiprocessor mode ).
 The 8086 signals can be categorised in three groups.
o The first are the signal having common functions in minimum as well as maximum
mode.
o The second are the signals which have special functions for minimum mode
o The third are the signals having special functions for maximum mode.
 The following signal descriptions are common for both modes.
 AD15-AD0 : These are the time multiplexed memory I/O address and data lines.
o Address remains on the lines during T1 state, while the data is available on the data bus
during T2, T3, Tw and T4. These lines are active high and float to a tristate during
interrupt acknowledge and local bus hold acknowledge cycles.

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 A19/S6,A18/S5,A17/S4,A16/S3 : These are the time multiplexed address and status lines.
o During T1 these are the most significant address lines for memory operations.
o During I/O operations, these lines are low.
o During memory or I/O operations, status information is available on those lines for
T2,T3,Tw and T4.
o The status of the interrupt enable flag bit is updated at the beginning of each clock cycle.
o The S4 and S3 combinely indicate which segment register is presently being used for
memory accesses as in below fig.
o These lines float to tri-state off during the local bus hold acknowledge. The status line S6
is always low.
o The address bit are separated from the status bit using latches controlled by the ALE
signal.

S4 S3 Indication

0 0 Alternate Data

0 1 Stack

1 0 Code or None

1 1 Data

0 0 Whole word

0 1 Upper byte from or to even address

1 0 Lower byte from or to even address

 BHE/S7: The bus high enable is used to indicate the transfer of data over the higher order ( D15-
D8 ) data bus as shown in table. It goes low for the data transfer over D15-D8 and is used to
derive chip selects of odd address memory bank or peripherals. BHE is low during T1 for read,
write and interrupt acknowledge cycles, whenever a byte is to be transferred on higher byte of
data bus. The status information is available during T2, T3 and T4. The signal is active low and
tristated during hold. It is low during T1 for the first pulses of the interrupt acknowledge cycle.

 RD – Read: This signal on low indicates the peripheral that the processor is performing memory
or I/O read operation. RD is active low and shows the state for T2, T3, Tw of any read cycle. The
signal remains tristated during the hold acknowledge.

 READY: This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by the
8284A clock generator to provide ready input to the 8086. the signal is active high.

 INTR-Interrupt Request: This is a triggered input. This is sampled during the last clock cycles
of each instruction to determine the availability of the request. If any interrupt request is pending,
the processor enters the interrupt acknowledge cycle. This can be internally masked by resulting
the interrupt enable flag. This signal is active high and internally synchronized.

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 TEST: This input is examined by a ‘WAIT’ instruction. If the TEST pin goes low, execution will
continue, else the processor remains in an idle state. The input is synchronized internally during
each clock cycle on leading edge of clock.

 CLK- Clock Input: The clock input provides the basic timing for processor operation and bus
control activity. Its an asymmetric square wave with 33% duty cycle.

The following pin functions are for the minimum mode operation of 8086.

 M/IO – Memory/IO: This is a status line logically equivalent to S2 in maximum mode. When it
is low, it indicates the CPU is having an I/O operation, and when it is high, it indicates that the
CPU is having a memory operation. This line becomes active high in the previous T4 and remains
active till final T4 of the current cycle. It is tristated during local bus “hold acknowledge “.

 INTA – Interrupt Acknowledge : This signal is used as a read strobe for interrupt acknowledge
cycles. i.e. when it goes low, the processor has accepted the interrupt.
 ALE – Address Latch Enable : This output signal indicates the availability of the valid address
on the address/data lines, and is connected to latch enable input of latches. This signal is active
high and is never tristated.

 DT/R – Data Transmit/Receive: This output is used to decide the direction of data flow through
the transreceivers (bidirectional buffers). When the processor sends out data, this signal is high
and when the processor is receiving data, this signal is low.

 DEN – Data Enable : This signal indicates the availability of valid data over the address/data
lines. It is used to enable the transreceivers ( bidirectional buffers ) to separate the data from the

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multiplexed address/data signal. It is active from the middle of T2 until the middle of T4. This is
tristated during ‘ hold acknowledge’ cycle.

 HOLD, HLDA- Acknowledge : When the HOLD line goes high, it indicates to the processor
that another master is requesting the bus access. The processor, after receiving the HOLD request,
issues the hold acknowledge signal on HLDA pin, in the middle of the next clock cycle after
completing the current bus cycle.

 At the same time, the processor floats the local bus and control lines. When the processor detects
the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input, and is should
be externally synchronized. If the DMA request is made while the CPU is performing a memory
or I/O cycle, it will release the local bus during T4 provided :

1. The request occurs on or before T2 state of the current cycle.

2. The current cycle is not operating over the lower byte of a word.
3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.

The following pin functions are applicable for maximum mode operation of 8086.

 S2, S1, S0 – Status Lines : These are the status lines which reflect the type of operation, being
carried out by the processor. These become activity during T4 of the previous cycle and active
during T1 and T2 of the current bus cycles.

 LOCK : This output pin indicates that other system bus master will be prevented fromgaining the
system bus, while the LOCK signal is low. The LOCK signal is activated by the ‘LOCK’ prefix
instruction and remains active until the completion of the next instruction. When the CPU is
executing a critical instruction which requires the system bus, the LOCK prefix instruction
ensures that other processors connected in the system will not gain the control of the bus.

The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may
be connected to an external bus controller. By prefetching the instruction, there is a considerable
speeding up in instruction execution in 8086. This is known as instruction pipelining.

S2 S1 S0 Indication

0 0 0 Interrupt Acknowledge

0 0 1 Read I/O port

0 1 0 Write I/O port

0 1 1 Halt

1 0 0 Code Access

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1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive

 At the starting the CS:IP is loaded with the required address from which the execution is to be
started. Initially, the queue will be empty an the microprocessor starts a fetch operation to bring
one byte (the first byte) of instruction code, if the CS:IP address is odd or two bytes at a time, if
the CS:IP address is even.

 The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and
is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining
part of code lie in second byte.

 The second byte is then decoded in continuation with the first byte to decide the instruction
length and the number of subsequent bytes to be treated as instruction data. The queue is updated
after every byte is read from the queue but the fetch cycle is initiated by BIU only if at least two
bytes of the queue are empty and the EU may be concurrently executing the fetched instructions.

 The next byte after the instruction is completed is again the first opcode byte of the next
instruction. A similar procedure is repeated till the complete execution of the program. The fetch
operation of the next instruction is overlapped with the execution of the current instruction. As in
the architecture, there are two separate units, namely Execution unit and Bus interface unit.

 While the execution unit is busy in executing an instruction, after it is completely decoded, the
bus interface unit may be fetching the bytes of the next instruction from memory, depending upon
the queue status.

QS1 QS0 Indication

0 0 No Operation

0 1 First Byte of the opcode from the queue

1 0 Empty Queue

Subsequent Byte from the Queue

1 1

 RQ/GT0, RQ/GT1 – Request/Grant : These pins are used by the other local bus master in
maximum mode, to force the processor to release the local bus at the end of the processor current
bus cycle.

 Each of the pin is bidirectional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins
have internal pull-up resistors and may be left unconnected. Request/Grant sequence is as
follows:

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1.A pulse of one clock wide from another bus master requests the bus access to 8086.
2.During T4(current) or T1(next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that it will enter
the ‘hold acknowledge’ state at next cycle. The CPU bus interface unit is likely to be
disconnected from the local bus of the system.
3.A one clock wide pulse from the another master indicates to the 8086 that the hold request is
about to end and the 8086 may regain control of the local bus at the next clock cycle. Thus each
master to master exchange of the local bus is a sequence of 3 pulses. There must be at least one
dead clock cycle after each bus exchange. The request and grant pulses are active low.For the
bus request those are received while 8086 is performing memory or I/O cycle, the granting of the
bus is governed by the rules as in case of HOLD and HLDA in minimum mode.

4. Write Notes On The Signals

Status signal:

 The four most significant address lines A19 through A16 are also multiplexed but in this case
with status signals S6 through S3. These status bits are output on the bus at the same time that
data are transferred over the other bus lines.
 Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment
registers are used to generate the physical address that was output on the address bus during the
current bus cycle.Code S4S3 = 00 identifies a register known as extra segment register as the
source of the segment address.
 Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level
of the internal enable flag. The last status bit S6 is always at the logic 0 level.

S3 Segment Register
S4
0 0 Extra

0 1 Stack

1 0 Code / none

1 1 Data

Memory segment status codes

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Control Signals :

 The control signals are provided to support the 8086 memory I/O interfaces. They control
functions such as when the bus is to carry a valid address in which direction data are to be
transferred over the bus, when valid write data are on the bus and when to put read data on the
system bus.

 ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus.
This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.

 Another control signal that is produced during the bus cycle is BHE bank high enable. Logic 0 on
this used as a memory enable signal for the most significant byte half of the data bus D8 through
D1. These lines also serves a second function, which is as the S7 status line.

 Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in
which direction data are to be transferred over the bus. The logic level of M/IO tells external
circuitry whether a memory or I/O transfer is taking place over the bus. Logic 1 at this output
signals a memory operation and logic 0 an I/O operation.

 The direction of data transfer over the bus is signaled by the logic level output at DT/R. When
this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode.
Therefore, data are either written into memory or output to an I/O device. On the other hand,
logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from
memory or input of data from an input port.

 The signal read RD and write WR indicates that a read bus cycle or a write bus cycle is in
progress. The 8086 switches WR to logic 0 to signal external device that valid write or output
data are on the bus.

 On the other hand, RD indicates that the 8086 is performing a read of data of the bus. During read
operations, one other control signal is also supplied. This is DEN ( data enable) and it signals
external devices when they should put data on the bus. There is one other control signal that is
involved with the memory and I/O interface. This is the READY signal.

 READY signal is used to insert wait states into the bus cycle such that it is extended by a number
of clock periods. This signal is provided by an external clock generator device and can be
supplied by the memory or I/O sub-system to signal the 8086 when they are ready to permit the
data transfer to be completed.

Interrupt signals :

 The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge
( INTA).
 INTR is an input to the 8086 that can be used by an external device to signal that it need to be
serviced.
 Logic 1 at INTR represents an active interrupt request. When an interrupt request has been
recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA
output.

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 The TEST input is also related to the external interrupt interface. Execution of a WAIT
instruction causes the 8086 to check the logic level at the TEST input.
 If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086 no
longer executes instructions, instead it repeatedly checks the logic level of the TEST input
waiting for its transition back to logic 0.
 As TEST switches to 0, execution resume with the next instruction in the program. This feature
can be used to synchronize the operation of the 8086 to an event in external hardware.
 There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and the reset
interrupt RESET.
 On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service routine. The
RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0
initializes the internal register of the 8086 and initiates a reset service routine.

DMA Interface signals :

 The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and
HLDA signals.
 When an external device wants to take control of the system bus, it signals to the 8086 by
switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters
the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE,
M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state.
 The 8086 signals external device that it is in this state by switching its HLDA output to logic 1
level.

General Bus Operation

 The 8086 has a combined address and data bus commonly referred as a time multiplexed address
and data bus.
 The main reason behind multiplexing address and data over the same pins is the maximum
utilisation of processor pins and it facilitates the use of 40 pin standard DIP package.
 The bus can be demultiplexed using a few latches and transreceivers, when ever required.
 Basically, all the processor bus cycles consist of at least four clock cycles. These are referred to
as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus
only for one cycle.
 The negative edge of this ALE pulse is used to separate the address and the data or status
information. In maximum mode, the status lines S0, S1 and S2 are used to indicate the type of
operation.
 Status bits S3 to S7 are multiplexed with higher order address bits and the BHE signal. Address is
valid during T1 while status bits S3 to S7 are valid during T2 through T4.

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Maximum mode

 In the maximum mode, the 8086 is operated by strapping the MN/MX pin to ground.
 In this mode, the processor derives the status signal S2, S1, S0. Another chip called bus controller
derives the control signal using this status information .
 In the maximum mode, there may be more than one microprocessor in the system configuration.

Minimum mode

 In a minimum mode 8086 system, the microprocessor 8086 is operated in minimum mode by
strapping its MN/MX pin to logic 1.
 In this mode, all the control signals are given out by the microprocessor chip itself.
 There is a single microprocessor in the minimum mode system.

5. Explain The addressing Modes Of 8086

Definition: An instruction acts on any number of operands.The way an instruction accesses its
operands is called its Addressing modes.

Operands may be of three types :


o Implicit
o Explicit
o Both Implicit and Explicit.

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Implicit operands mean that the instruction by definition has some specific operands. The
programmers do NOT select these operands.

Example: Implicit operands

XLAT ; automatically takes AL and BX as

operands
AAM ; it operates on the contents of AX.

Explicit operands mean the instruction operates on the operands specified by the programmer.

Example: Explicit operands

MOV AX, BX; it takes AX and BX as

operands
XCHG SI, DI; it takes SI and DI as operands

Implicit and explicit operands

Example: Implicit/Explicit operands

MUL BX; automatically multiply BX explicitly times

AX

The location of an operand value in memory space is called the Effective Address (EA)

We can classify the addressing modes of 8086 into four groups:

 Immediate addressing
 Register addressing
 Memory addressing
 I/O port addressing

The first three Addresssing modes are clearly explained.

Immediate addressing mode & Register addressing mode

Immediate Addressing Mode

In this addressing mode, the operand is stored as part of the instruction. The immediate operand,
which is stored along with the instruction, resides in the code segment -- not in the data segment.

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This addressing mode is also faster to execute an instruction because the operand is read with the
instruction from memory. Here are some examples:

Example: Immediate Operands

MOV AL, 20 ; move the constant 20 into register AL

ADD AX, 5 ; add constant 5 to register EAX
MOV DX, offset msg ; move the address of message to
register DX

Register addressing mode

In this addressing mode, the operands may be:

 reg16: 16-bit general registers: AX, BX, CX, DX, SI, DI, SP or BP.
 reg8 : 8-bit general registers: AH, BH, CH, DH, AL, BL, CL, or DL.
 Sreg : segment registers: CS, DS, ES, or SS. There is an exception: CS cannot be a destination.

For register addressing modes, there is no need to compute the effective address. The operand is
in a register and to get the operand there is no memory access involved.

Example: Register Operands

MOV AX, BX ; mov reg16, reg16

ADD AX, SI ; add reg16, reg16
MOV DS, AX ; mov Sreg, reg16

Some rules in register addressing modes:

1. You may not specify CS as the destination operand.

Example: mov CS, 02h –> wrong

2. Only one of the operands can be a segment register. You cannot move data from one segment
register to another with a single mov instruction. To copy the value of cs to ds, you would have
to use some sequence like:

mov ds,cs -> wrong

mov ax, cs
mov ds, ax -> the way we do it

You should never use the segment registers as data registers to hold arbitrary values. They
should only contain segment addresses.

Memory Addressing Modes

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Memory (RAM) is the main component of a computer to store temporary data and machine instructions.
In a program, programmers many times need to read from and write into memory locations.

There are different forms of memory addressing modes

1. Direct Addressing
2. Register indirect addressing
3. Based addressing
4. Indexed addressing
5. Based indexed addressing
6. Based indexed with displacement

Direct Addressing Mode & Register Indirect Addressing Mode

Direct Addressing Mode

The instruction mov al,ds:[8088h] loads the AL register with a copy of the byte at memory
location 8088h. Likewise, the instruction mov ds:[1234h],dl stores the value in the dl register to
memory location 1234h. By default, all displacement-only values provide offsets into the data
segment. If you want to provide an offset into a different segment, you must use a segment
override prefix before your address. For example, to access location 1234h in the extra segment
(es) you would use an instruction of the form mov ax,es:[1234h]. Likewise, to access this
location in the code segment you would use the instruction mov ax, cs:[1234h]. The ds: prefix in
the previous examples is not a segment override.

The instruction mov al,ds:[8088h] is same as mov al, [8088h]. If not mentioned DS register is
taken by default.

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Register Indirect Addressing Mode

The 80x86 CPUs let you access memory indirectly through a register using the register indirect
addressing modes. There are four forms of this addressing mode on the 8086, best demonstrated
by the following instructions:

mov al, [bx]

mov al, [bp]
mov al, [si]
mov al, [di]

Code Example

MOV BX, 100H

MOV AL, [BX]

The [bx], [si], and [di] modes use the ds segment by default. The [bp] addressing mode uses the
stack segment (ss) by default. You can use the segment override prefix symbols if you wish to
access data in different segments. The following instructions demonstrate the use of these
overrides:

mov al, cs:[bx]

mov al, ds:[bp]
mov al, ss:[si]
mov al, es:[di]

Intel refers to [bx] and [bp] as base addressing modes and bx and bp as base registers (in fact, bp
stands for base pointer). Intel refers to the [si] and [di] addressing modes as indexed addressing
modes (si stands for source index, di stands for destination index). However, these addressing
modes are functionally equivalent. This text will call these forms register indirect modes to be
consistent.

Based Addressing Mode and Indexed Addressing Modes

Based Addressing Mode

8-bit or 16-bit instruction operand is added to the contents of a base register (BX or BP), the
resulting value is a pointer to location where data resides.

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Mov al, [bx],[si]

Mov bl , [bp],[di]
Mov cl , [bp],[di]

Code Example

If bx=1000h
si=0880h
Mov AL, [1000+880]
Mov AL,[1880]

Indexed Addressing Modes

The indexed addressing modes use the following syntax:

mov al, [bx+disp]

mov al, [bp+disp]
mov al, [si+disp]
mov al, [di+disp]

Code Example

MOV BX, 100H

MOV AL, [BX + 15]
MOV AL, [BX + 16]

If bx contains 1000h, then the instruction mov cl, [bx+20h] will load cl from memory location
ds:1020h. Likewise, if bp contains 2020h, mov dh, [bp+1000h] will load dh from location
ss:3020. The offsets generated by these addressing modes are the sum of the constant and the
specified register. The addressing modes involving bx, si, and di all use the data segment, the
[bp+disp] addressing mode uses the stack segment by default. As with the register indirect
addressing modes, you can use the segment override prefixes to specify a different segment:

mov al, ss:[bx+disp]

mov al, es:[bp+disp]
mov al, cs:[si+disp]
mov al, ss:[di+disp]

Based Indexed Addressing Modes & Based Indexed Plus Displacement Addressing Mode

Based Indexed Addressing Modes

The based indexed addressing modes are simply combinations of the register indirect addressing
modes. These addressing modes form the offset by adding together a base register (bx or bp) and
an index register (si or di). The allowable forms for these addressing modes are:

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mov al, [bx+si]

mov al, [bx+di]
mov al, [bp+si]
mov al, [bp+di]

Code Example

MOV BX, 100H

MOV SI, 200H
MOV AL, [BX + SI]
INC BX
INC SI

Suppose that bx contains 1000h and si contains 880h. Then the instruction mov al,[bx][si] would
load al from location DS:1880h. Likewise, if bp contains 1598h and di contains 1004, mov ax,
[bp+di] will load the 16 bits in ax from locations SS:259C and SS:259D. The addressing modes
that do not involve bp use the data segment by default. Those that have bp as an operand use the
stack segment by default.

Based Indexed Plus Displacement Addressing Mode

These addressing modes are a slight modification of the base/indexed addressing modes with the
addition of an eight bit or sixteen bit constant. The following are some examples of these
addressing modes

mov al, disp[bx][si]

mov al, disp[bx+di]
mov al, [bp+si+disp]
mov al, [bp][di][disp]

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Code Example

MOV BX, 100H

MOV SI, 200H
MOV AL, [BX + SI +100H]
INC BX
INC SI

6. Explain Pointer Registers

These registers can also be called as Special Purpose registers.

Stack Pointer (SP) is a 16-bit register pointing to program stack, ie it is used to hold the address
of the top of stack. The stack is maintained as a LIFO with its bottom at the start of the stack
segment (specified by the SS segment register).Unlike the SP register, the BP can be used to
specify the offset of other program segments.

Base Pointer (BP) is a 16-bit register pointing to data in stack segment. It is usually used by
subroutines to locate variables that were passed on the stack by a calling program. BP register is
usually used for based, based indexed or register indirect addressing.

Source Index (SI) is a 16-bit register. SI is used for indexed, based indexed and register indirect
addressing, as well as a source data address in string manipulation instructions. Used in
conjunction with the DS register to point to data locations in the data segment.

Destination Index (DI) is a 16-bit register. Used in conjunction with the ES register in string
operations. DI is used for indexed, based indexed and register indirect addressing, as well as a
destination data address in string manipulation instructions. In short, Destination Index and SI
Source Index registers are used to hold address.

Segment Registers

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Most of the registers contain data/instruction offsets within 64 KB memory segment. There are
four different 64 KB segments for instructions, stack, data and extra data. To specify where in 1
MB of processor memory these 4 segments are located the processor uses four segment registers.

Code segment (CS) is a 16-bit register containing address of 64 KB segment with processor
instructions. The processor uses CS segment for all accesses to instructions referenced by
instruction pointer (IP) register. CS register cannot be changed directly. The CS register is
automatically updated during far jump, far call and far return instructions.

Stack segment (SS) is a 16-bit register containing address of 64KB segment with program stack.
By default, the processor assumes that all data referenced by the stack pointer (SP) and base
pointer (BP) registers is located in the stack segment. SS register can be changed directly using
POP instruction.

Data segment (DS) is a 16-bit register containing address of 64KB segment with program data.
By default, the processor assumes that all data referenced by general registers (AX, BX, CX,
DX) and index register (SI, DI) is located in the data segment. DS register can be changed
directly using POP and LDS instructions.

Extra segment (ES) used to hold the starting address of Extra segment. Extra segment is
provided for programs that need to access a second data segment. Segment registers cannot be
used in arithmetic operations.

Other registers of 8086

Instruction Pointer (IP) is a 16-bit register. This is a crucially important register which is used
to control which instruction the CPU executes. The ip, or program counter, is used to store the
memory location of the next instruction to be executed. The CPU checks the program counter to
ascertain which instruction to carry out next. It then updates the program counter to point to the
next instruction. Thus the program counter will always point to the next instruction to be
executed.

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Flag Register contains a group of status bits called flags that indicate the status of the CPU or
the result of arithmetic operations. There are two types of flags:

1. The status flags which reflect the result of executing an instruction. The programmer cannot
set/reset these flags directly.
2. The control flags enable or disable certain CPU operations. The programmer can set/reset
these bits to control the CPU's operation.

Nine individual bits of the status register are used as control flags (3 of them) and status flags (6
of them).The remaining 7 are not used.
A flag can only take on the values 0 and 1. We say a flag is set if it has the value 1.The status
flags are used to record specific characteristics of arithmetic and of logical instructions.

Control Flags: There are three control flags

1. The Direction Flag (D): Affects the direction of moving data blocks by such instructions as
MOVS, CMPS and SCAS. The flag values are 0 = up and 1 = down and can be set/reset by the
STD (set D) and CLD (clear D) instructions.

2. The Interrupt Flag (I): Dictates whether or not system interrupts can occur. Interrupts are
actions initiated by hardware block such as input devices that will interrupt the normal execution
of programs. The flag values are 0 = disable interrupts or 1 = enable interrupts and can be
manipulated by the CLI (clear I) and STI (set I) instructions.

3. The Trap Flag (T): Determines whether or not the CPU is halted after the execution of each
instruction. When this flag is set (i.e. = 1), the programmer can single step through his program
to debug any errors. When this flag = 0 this feature is off. This flag can be set by the INT 3
instruction.

Status Flags: There are six status flags

1. The Carry Flag (C): This flag is set when the result of an unsigned arithmetic operation is
too large to fit in the destination register. This happens when there is an end carry in an addition
operation or there an end borrows in a subtraction operation. A value of 1 = carry and 0 = no
carry.

2. The Overflow Flag (O): This flag is set when the result of a signed arithmetic operation is too
large to fit in the destination register (i.e. when an overflow occurs). Overflow can occur when
adding two numbers with the same sign (i.e. both positive or both negative). A value of 1 =
overflow and 0 = no overflow.

3. The Sign Flag (S): This flag is set when the result of an arithmetic or logic operation is
negative. This flag is a copy of the MSB of the result (i.e. the sign bit). A value of 1 means
negative and 0 = positive.

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4. The Zero Flag (Z): This flag is set when the result of an arithmetic or logic operation is equal
to zero. A value of 1 means the result is zero and a value of 0 means the result is not zero.

5. The Auxiliary Carry Flag (A): This flag is set when an operation causes a carry from bit 3 to
bit 4 (or a borrow from bit 4 to bit 3) of an operand. A value of 1 = carry and 0 = no carry.

6. The Parity Flag (P): This flags reflects the number of 1s in the result of an operation. If the
number of 1s is even its value = 1 and if the number of 1s is odd then its value = 0.

7. Explain 8086 Instruction Set and its Classification

The instructions of 8086 are classified into SIX groups. They are:

1. DATA TRANSFER INSTRUCTIONS

2. ARITHMETIC INSTRUCTIONS
3. BIT MANIPULATION INSTRUCTIONS
4. STRING INSTRUCTIONS
5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS
6. PROCESS CONTROL INSTRUCTIONS

1.DATA TRANSFER INSTRUCTIONS

The DATA TRANSFER INSTRUCTIONS are those, which transfers the DATA from any one
source to any one destination.The datas may be of any type. They are again classified into four
groups.They are:

GENERAL – PURPOSE BYTE SIMPLE INPUT AND SPECIAL ADDRESS FLAG

OR WORD TRANSFER OUTPUTPORT TRANSFER TRANSFER TRANSFER
INSTRUCTIONS INSTRUCTION INSTRUCTION INSTRUCTIONS
MOV LEA LAHF
PUSH LDS SAHF
POP IN LES PUSHF
XCHG OUT POPF
XLAT

2.ARITHMETIC INSTRUCTIONS

These instructions are those which are useful to perform Arithmetic calculations, such as
addition, subtraction, multiplication and division.They are again classified into four groups.They
are:

ADDITION SUBTRACTION MULTIPLICATION DIVISION

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INSTRUCTIONS INSTRUCTIONS INSTRUCTIONS INSTRUCTIONS

ADD SUB MUL DIV
ADC SBB IMUL IDIV
INC DEC AAM AAD
AAA NEG CBW
DAA CMP CWD
AAS
DAS

3.BIT MANIPULATION INSTRUCTIONS

These instructions are used to perform Bit wise operations.

LOGICAL INSTRUCTIONS SHIFT INSTRUCTIONS ROTATE INSTRUCTIONS

NOT SHL / SAL ROL
AND SHR ROR
OR SAR RCL
XOR RCR
TEST

4. STRING INSTRUCTIONS

The string instructions function easily on blocks of memory.They are user friendly instructions,
which help for easy program writing and execution. They can speed up the manipulating
code.They are useful in array handling, tables and records.

STRING INSTRUCTIONS
REP
REPE / REPZ
REPNE / REPNZ
MOVS / MOVSB / MOVSW
COMPS / COMPSB /
COMPSW
SCAS / SCASB / SCASW
LODS / LODSB / LODSW
STOS / STOSB / STOSW

5.PROGRAM EXECUTION TRANSFER INSTRUCTIONS

These instructions transfer the program control from one address to other address. ( Not in a
sequence). They are again classified into four groups.They are:

UNCONDITIONAL CONDITIONAL ITERATION CONTROL INTERRUPT

TRANSFER TRANSFER INSTRUCTIONS INSTRUCTIONS

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INSTRUCTIONS INSTRUCTIONS
CALL JA / JNBE JLE / JNG LOOP INT
RET JAE / JNB JNC LOOPE / LOOPZ INTO
JMP JB / JNAE JNE / JNZ LOOPNE / LOOPNZ IRET
JBE / JNA JNO JCXZ
JC JNP / JPO
JE / JZ JNS
JG / JNLE JO
JGE / JNL
JL / JNGE JP / JPE
JS

6.PROCESS CONTROL INSTRUCTIONS

These instructions are used to change the process of the Microprocessor. They change the
process with the stored information. They are again classified into Two groups.They are:

FLAG SET / CLEAR EXTERNAL HARDWARE

INSTRUCTIONS SYNCHRONIZATION
INSTRUCTIONS
STC HLT
CLC WAIT
CMC ESC
STD LOCK
CLD
STI NOP
CLI

8.Write notes on Interrupts

Definition: The meaning of ‘interrupts’ is to break the sequence of operation.While the cpu is
executing a program,on ‘interrupt’ breaks the normal sequence of execution of instructions,
diverts its execution to some other program called Interrupt Service Routine (ISR).After
executing ISR , the control is transferred back again to the main program.Interrupt processing is
an alternative to polling.

Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices, that provide
or require data at relatively low data transfer rate.

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Types of Interrupts: There are two types of Interrupts in 8086. They are:

(i)Hardware Interrupts and

(ii)Software Interrupts

(i) Hardware Interrupts (External Interrupts). The Intel microprocessors support hardware
interrupts through:

 Two pins that allow interrupt requests, INTR and NMI

 One pin that acknowledges, INTA, the interrupt requested on INTR.

INTR and NMI

 INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI
instructions or using more complicated method of updating the FLAGS register with the help of
the POPF instruction.
 When an interrupt occurs, the processor stores FLAGS register into stack, disables further
interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt
processing routine address of which is stored in location 4 * <interrupt type>. Interrupt
processing routine should return with the IRET instruction.
 NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt.
Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location
0008h. This interrupt has higher priority than the maskable interrupt.
 – Ex: NMI, INTR.

(ii) Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be
caused by:

 INT instruction - breakpoint interrupt. This is a type 3 interrupt.

 INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
 INTO instruction - interrupt on overflow
 Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU
processes this interrupt it clears TF flag before calling the interrupt processing routine.
 Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type
7).
 Software interrupt processing is the same as for the hardware interrupts.
 - Ex: INT n (Software Instructions)
 Control is provided through:
o IF and TF flag bits
o IRET and IRETD

Performance of Hardware Interrupts

 NMI : Non maskable interrupts - TYPE 2 Interrupt

 INTR : Interrupt request - Between 20H and FFH

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Interrupt Priority Structure

Performance of Software Interrupts

1. It decrements SP by 2 and pushes the flag register on the stack.

2. Disables INTR by clearing the IF.
3. It resets the TF in the flag Register.
5. It decrements SP by 2 and pushes CS on the stack.
6. It decrements SP by 2 and pushes IP on the stack.
7. Fetch the ISR address from the interrupt vector table.

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UNIT 5
1. Compare Microprocessor and Microcontroller

MICROCONTROLLERS AND MICROPROCESSORS

A controller is used to control some process. At one time, controllers were built exclusively from
logic components, and were usually large, heavy boxes. Later on, microprocessors were used and the
entire controller could fit on a small circuit board.

A CPU built into a single VLSI chip is called microprocessor. The simplified block diagram of the CPU
is shown in the Fig. 1.1. It contains arithmetic and logic units (ALU), Instruction decode and control unit,
Instruction register, Program counter (PC), clock circuit (internal or external), reset circuit (internal or
external) and registers. For example, Intel 8085 is 8-bit microprocessor and Intel 8086/8088 is 16-bit
microprocessor. Microprocessor is general-purpose digital computer central processing unit (CPU). The
microprocessor is general-purpose device and additional external circuitry is added to make it
microcomputer.

A digital computer having microprocessor as the CPU along with I/O devices and memory is known as
microcomputer. The block diagram in the Fig. 1.2 shows a microcomputer.

A microcontroller is a highly integrated chip, which includes on single chip, all or most of the parts
needed for a controller. The microcontroller typically includes: CPU (Central Processing Unit), RAM
(Random Access Memory), EPROM/PROM/ROM (Erasable Programmable Read Only Memory), I/O

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(input/output) – serial and parallel, timers, interrupt controller. For example, Intel 8051 is 8-bit
microcontroller and Intel 8096 is 16-bit microcontroller.

By only including the features specific to the task (control), cost is relatively low. A typical
microcontroller has bit manipulation instructions, easy and direct access to I/O (input/output), and quick
and efficient interrupt processing. Figure 1.3 shows the block diagram of a typical microcontroller.

2. What Are the Types of Microcontrollers?

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Microcontrollers can be classified on the basis of internal bus width, architecture, memory and instruction
set.

THE 8-BIT MICROCONTROLLER

When the ALU performs arithmetic and logical operations on a byte (8-bits) at an instruction, the
microcontroller is an 8-bit microcontroller. The internal bus width of 8-bit microcontroller is of 8-bit.

THE 16-BIT MICROCONTROLLER

When the ALU performs arithmetic and logical operations on a word (16-bits) at an instruction, the
microcontroller is an 16-bit microcontroller. The internal bus width of 16-bit microcontroller is of 16-bit.
Examples of 16-bit microcontrollers are Intel 8096 family and Motorola MC68HC12 and MC68332
families. The performance and computing capability of 16 bit microcontrollers are enhanced with greater
precision as compared to the 8-bit microcontrollers.

THE 32-BIT MICROCONTROLLER

When the ALU performs arithmetic and logical operations on a double word (32- bits) at an instruction,
the microcontroller is an 32-bit microcontroller. The internal bus width of 32-bit microcontroller is of 32-
bit. Examples of 32-bit microcontrollers are Intel 80960 family and Motorola M683xx and Intel/Atmel
251 family. The performance and computing capability of 32 bit microcontrollers are enhanced with
greater precision as compared to the 16-bit microcontrollers.

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3. Explain 8051 Microcontroller Internal Architecture in Detail

As can be seen on the image above, there is nothing particularly remarkable about MCU 8051:

4 kilobytes of ROM is neither too little nor too much.

128 bytes of RAM (SFR registers included) can satisfy the basic needs, but is not really astounding.

4 ports totaling 32 I/O lines, are usually sufficient for connecting to the environs and are by no means
luxury. Obviously, 8051 configuration is intended to satisfy the needs of programmers developing the
controlling devices and instruments. This is one part of its key to success: there is nothing missing, yet
there is no lavishness; it is meant for the average user. The other clue can be found in the organization of
RAM, Central Processor Unit (CPU), and ports - all of which maximally utilize the available resources
and allow further upgrades.

Types of Memory

The 8051 has three very general types of memory. To effectively program the 8051 it is necessary to have
a basic understanding of these memory types. The memory types are illustrated in the following graphic.
They are: On-Chip Memory, External Code Memory, and External RAM.

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On-Chip Memory refers to any memory (Code, RAM, or other) that physically exists on the
microcontroller itself. On-chip memory can be of several types, but we'll get into that shortly.

External Code Memory is code (or program) memory that resides off-chip. This is often in the form of
an external EPROM.

External RAM is RAM memory that resides off-chip. This is often in the form of standard static RAM or
flash RAM.

Code Memory

Code memory is the memory that holds the actual 8051 program that is to be run. This memory is limited
to 64K and comes in many shapes and sizes: Code memory may be found on-chip, either burned into the
microcontroller as ROM or EPROM. Code may also be stored completely off-chip in an external ROM
or, more commonly, an external EPROM. Flash RAM is also another popular method of storing a

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program. Various combinations of these memory types may also be used--that is to say, it is possible to
have 4K of code memory on-chip and 64k of code memory off-chip in an EPROM.

When the program is stored on-chip the 64K maximum is often reduced to 4k, 8k, or 16k. This varies
depending on the version of the chip that is being used. Each version offers specific capabilities and one
of the distinguishing factors from chip to chip is how much ROM/EPROM space the chip has.

However, code memory is most commonly implemented as off-chip EPROM.

External RAM

As an obvious opposite of Internal RAM, the 8051 also supports what is called External RAM.

As the name suggests, External RAM is any random access memory which is found off-chip. Since the
memory is off-chip it is not as flexible in terms of accessing, and is also slower. For example, to
increment an Internal RAM location by 1 requires only 1 instruction and 1 instruction cycle. To increment
a 1-byte value stored in External RAM requires 4 instructions and 7 instruction cycles. In this case,
external memory is 7 times slower! What External RAM loses in speed and flexibility it gains in quantity.
While Internal RAM is limited to 128 bytes (256 bytes with an 8052), the 8051 supports External RAM
up to 64K.

On-Chip Memory

As mentioned at the beginning of this chapter, the 8051 includes a certain amount of on-chip memory.
On-chip memory is really one of two types: Internal RAM and Special Function Register (SFR) memory.
The layout of the 8051's internal memory is presented in the following memory map: \ As is illustrated in
this map, the 8051 has a bank of 128 bytes of Internal RAM. This Internal RAM is found on-chip on the
8051 so it is the fastest RAM available, and it is also the most flexible in terms of reading, writing, and
modifying it’s contents. Internal RAM is volatile, so when the 8051 is reset this memory is cleared.

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The 128 bytes of internal ram is subdivided as shown on the memory map. The first 8 bytes (00h - 07h)
are "register bank 0". By manipulating certain SFRs, a program may choose to use register banks 1, 2, or
3. These alternative register banks are located in internal RAM in addresses 08h through 1Fh. We'll
discuss "register banks" more in a later chapter. For now it is sufficient to know that they "live" and are
part of internal RAM.

Bit Memory also lives and is part of internal RAM. We'll talk more about bit memory very shortly, but for
now just keep in mind that bit memory actually resides in internal RAM, from addresses 20h through 2Fh.

The 80 bytes remaining of Internal RAM, from addresses 30h through 7Fh, may be used by user variables
that need to be accessed frequently or at high-speed. This area is also utilized by the microcontroller as a
storage area for the operating stack. This fact severely limits the 8051’s stack since, as illustrated in the
memory map, the area reserved for the stack is only 80 bytes--and usually it is less since this 80 bytes has
to be shared between the stack and user variables.

Register Banks

The 8051 uses 8 "R" registers which are used in many of its instructions. These "R" registers are
numbered from 0 through 7 (R0, R1, R2, R3, R4, R5, R6, and R7). These registers are generally used to

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assist in manipulating values and moving data from one memory location to another. For example, to add
the value of R4 to the Accumulator, we would execute the following instruction:

ADD A,R4

Thus if the Accumulator (A) contained the value 6 and R4 contained the value 3, the Accumulator would
contain the value 9 after this instruction was executed.

However, as the memory map shows, the "R" Register R4 is really part of Internal RAM. Specifically, R4
is address 04h. This can be see in the bright green section of the memory map. Thus the above instruction
accomplishes the same thing as the following operation:

ADD A,04h

This instruction adds the value found in Internal RAM address 04h to the value of the Accumulator,
leaving the result in the Accumulator. Since R4 is really Internal RAM 04h, the above instruction
effectively accomplished the same thing.

But watch out! As the memory map shows, the 8051 has four distinct register banks. When the 8051 is
first booted up, register bank 0 (addresses 00h through 07h) is used by default. However, your program
may instruct the 8051 to use one of the alternate register banks; i.e., register banks 1, 2, or 3. In this case,
R4 will no longer be the same as Internal RAM address 04h. For example, if your program instructs the
8051 to use register bank 3, "R" register R4 will now be synonomous with Internal RAM address 1Ch.

The concept of register banks adds a great level of flexibility to the 8051, especially when dealing with
interrupts (we'll talk about interrupts later). However, always remember that the register banks really
reside in the first 32 bytes of Internal RAM.

Bit Memory

The 8051, being a communications-oriented microcontroller, gives the user the ability to access a number
of bit variables. These variables may be either 1 or 0.

There are 128 bit variables available to the user, numberd 00h through 7Fh. The user may make use of
these variables with commands such as SETB and CLR. For example, to set bit number 24 (hex) to 1 you
would execute the instruction:

SETB 24h

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It is important to note that Bit Memory is really a part of Internal RAM. In fact, the 128 bit variables
occupy the 16 bytes of Internal RAM from 20h through 2Fh. Thus, if you write the value FFh to Internal
RAM address 20h you’ve effectively set bits 00h through 07h. That is to say that:

MOV 20h,#0FFh

is equivalent to:

SETB 00h SETB 01h SETB 02h

SETB 03h SETB 04h SETB 05h

SETB 06h SETB 07h

As illustrated above, bit memory isn’t really a new type of memory. It’s really just a subset of Internal
RAM. But since the 8051 provides special instructions to access these 16 bytes of memory on a bit by bit
basis it is useful to think of it as a separate type of memory. However, always keep in mind that it is just a
subset of Internal RAM--and that operations performed on Internal RAM can change the values of the bit
variables.

Programming Tip: If your program does not use bit variables, you may use Internal RAM
locations 20h through 2Fh for your own use. But if you plan to use bit variables, be very careful
about using addresses from 20h through 2Fh as you may end up overwriting the value of your
bits!

Bit variables 00h through 7Fh are for user-defined functions in their programs. However, bit variables
80h and above are actually used to access certain SFRs on a bit-by-bit basis. For example, if output lines
P0.0 through P0.7 are all clear (0) and you want to turn on the P0.0 output line you may either execute:

MOV P0,#01h

or you may execute:

SETB 80h

4. What Are SFRs?

The 8051 is a flexible microcontroller with a relatively large number of modes of operations. Your
program may inspect and/or change the operating mode of the 8051 by manipulating the values of the
8051's Special Function Registers (SFRs).

Special Function Register (SFR) Memory

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Special Function Registers (SFRs) are areas of memory that control specific functionality of the 8051
processor. For example, four SFRs permit access to the 8051’s 32 input/output lines. Another SFR allows
a program to read or write to the 8051’s serial port. Other SFRs allow the user to set the serial baud rate,
control and access timers, and configure the 8051’s interrupt system.

SFRs are accessed as if they were normal Internal RAM. The only difference is that Internal RAM is from
address 00h through 7Fh whereas SFR registers exist in the address range of 80h through FFh.

Each SFR has an address (80h through FFh) and a name. The following chart provides a graphical
presentation of the 8051's SFRs, their names, and their address. As you can see, although the address
range of 80h through FFh offer 128 possible addresses, there are only 21 SFRs in a standard 8051. All
other addresses in the SFR range (80h through FFh) are considered invalid. Writing to or reading from
these registers may produce undefined values or behavior.

SFR Types

As mentioned in the chart itself, the SFRs that have a blue background are SFRs related to the I/O ports.
The 8051 has four I/O ports of 8 bits, for a total of 32 I/O lines. Whether a given I/O line is high or low
and the value read from the line are controlled by the SFRs in green.

The SFRs with yellow backgrouns are SFRs which in some way control the operation or the configuration
of some aspect of the 8051. For example, TCON controls the timers, SCON controls the serial port.

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The remaining SFRs, with green backgrounds, are "other SFRs." These SFRs can be thought of as
auxillary SFRs in the sense that they don't directly configure the 8051 but obviously the 8051 cannot
operate without them. For example, once the serial port has been configured using SCON, the program
may read or write to the serial port using the SBUF register.

Programming Tip: The SFRs whose names appear in red in the chart above are SFRs that may
be accessed via bit operations (i.e., using the SETB and CLR instructions). The other SFRs
cannot be accessed using bit operations. As you can see, all SFRs that whose addresses are
divisible by 8 can be accessed with bit operations.

SFR Descriptions

This section will endeavor to quickly overview each of the standard SFRs found in the above SFR chart
map. It is not the intention of this section to fully explain the functionality of each SFR--this information
will be covered in separate chapters of the tutorial. This section is to just give you a general idea of what
each SFR does.

P0 (Port 0, Address 80h, Bit-Addressable): This is input/output port 0. Each bit of this SFR
corresponds to one of the pins on the microcontroller. For example, bit 0 of port 0 is pin P0.0, bit 7 is pin
P0.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to a low level.

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Programming Tip: While the 8051 has four I/O port (P0, P1, P2, and P3), if your hardware uses
external RAM or external code memory (i.e., your program is stored in an external ROM or
EPROM chip or if you are using external RAM chips) you may not use P0 or P2. This is because
the 8051 uses ports P0 and P2 to address the external memory. Thus if you are using external
RAM or code memory you may only use ports P1 and P3 for your own use.

SP (Stack Pointer, Address 81h): This is the stack pointer of the microcontroller. This SFR indicates
where the next value to be taken from the stack will be read from in Internal RAM. If you push a value
onto the stack, the value will be written to the address of SP + 1. That is to say, if SP holds the value 07h,
a PUSH instruction will push the value onto the stack at address 08h. This SFR is modified by all
instructions which modify the stack, such as PUSH, POP, LCALL, RET, RETI, and whenever interrupts
are provoked by the microcontroller.

Programming Tip: The SP SFR, on startup, is initialized to 07h. This means the stack will start
at 08h and start expanding upward in internal RAM. Since alternate register banks 1, 2, and 3 as
well as the user bit variables occupy internal RAM from addresses 08h through 2Fh, it is
necessary to initialize SP in your program to some other value if you will be using the alternate
register banks and/or bit memory. It's not a bad idea to initialize SP to 2Fh as the first instruction
of every one of your programs unless you are 100% sure you will not be using the register banks
and bit variables.

DPL/DPH (Data Pointer Low/High, Addresses 82h/83h): The SFRs DPL and DPH work together to
represent a 16-bit value called the Data Pointer. The data pointer is used in operations regarding external
RAM and some instructions involving code memory. Since it is an unsigned two-byte integer value, it can
represent values from 0000h to FFFFh (0 through 65,535 decimal).

PCON (Power Control, Addresses 87h): The Power Control SFR is used to control the 8051's power
control modes. Certain operation modes of the 8051 allow the 8051 to go into a type of "sleep" mode
which requires much less power. These modes of operation are controlled through PCON. Additionally,
one of the bits in PCON is used to double the effective baud rate of the 8051's serial port.

TCON (Timer Control, Addresses 88h, Bit-Addressable): The Timer Control SFR is used to configure
and modify the way in which the 8051's two timers operate. This SFR controls whether each of the two
timers is running or stopped and contains a flag to indicate that each timer has overflowed. Additionally,
some non-timer related bits are located in the TCON SFR. These bits are used to configure the way in

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which the external interrupts are activated and also contain the external interrupt flags which are set when
an external interrupt has occured.

TMOD (Timer Mode, Addresses 89h): The Timer Mode SFR is used to configure the mode of
operation of each of the two timers. Using this SFR your program may configure each timer to be a 16-bit
timer, an 8-bit autoreload timer, a 13-bit timer, or two separate timers. Additionally, you may configure
the timers to only count when an external pin is activated or to count "events" that are indicated on an
external pin.

TL0/TH0 (Timer 0 Low/High, Addresses 8Ah/8Ch): These two SFRs, taken together, represent timer
0. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers
always count up. What is configurable is how and when they increment in value.

TL1/TH1 (Timer 1 Low/High, Addresses 8Bh/8Dh): These two SFRs, taken together, represent timer
1. Their exact behavior depends on how the timer is configured in the TMOD SFR; however, these timers
always count up. What is configurable is how and when they increment in value.

P1 (Port 1, Address 90h, Bit-Addressable): This is input/output port 1. Each bit of this SFR
corresponds to one of the pins on the microcontroller. For example, bit 0 of port 1 is pin P1.0, bit 7 is pin
P1.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to a low level.

SCON (Serial Control, Addresses 98h, Bit-Addressable): The Serial Control SFR is used to configure
the behavior of the 8051's on-board serial port. This SFR controls the baud rate of the serial port, whether
the serial port is activated to receive data, and also contains flags that are set when a byte is successfully
sent or received.

SBUF (Serial Control, Addresses 99h): The Serial Buffer SFR is used to send and receive data via the
on-board serial port. Any value written to SBUF will be sent out the serial port's TXD pin. Likewise, any
value which the 8051 receives via the serial port's RXD pin will be delivered to the user program via
SBUF. In other words, SBUF serves as the output port when written to and as an input port when read
from.

P2 (Port 2, Address A0h, Bit-Addressable): This is input/output port 2. Each bit of this SFR
corresponds to one of the pins on the microcontroller. For example, bit 0 of port 2 is pin P2.0, bit 7 is pin
P2.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to a low level.

IE (Interrupt Enable, Addresses A8h): The Interrupt Enable SFR is used to enable and disable specific
interrupts. The low 7 bits of the SFR are used to enable/disable the specific interrupts, where as the

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highest bit is used to enable or disable ALL interrupts. Thus, if the high bit of IE is 0 all interrupts are
disabled regardless of whether an individual interrupt is enabled by setting a lower bit.

P3 (Port 3, Address B0h, Bit-Addressable): This is input/output port 3. Each bit of this SFR
corresponds to one of the pins on the microcontroller. For example, bit 0 of port 3 is pin P3.0, bit 7 is pin
P3.7. Writing a value of 1 to a bit of this SFR will send a high level on the corresponding I/O pin whereas
a value of 0 will bring it to a low level.

IP (Interrupt Priority, Addresses B8h, Bit-Addressable): The Interrupt Priority SFR is used to specify
the relative priority of each interrupt. On the 8051, an interrupt may either be of low (0) priority or high
(1) priority. An interrupt may only interrupt interrupts of lower priority. For example, if we configure the
8051 so that all interrupts are of low priority except the serial interrupt, the serial interrupt will always be
able to interrupt the system, even if another interrupt is currently executing. However, if a serial interrupt
is executing no other interrupt will be able to interrupt the serial interrupt routine since the serial interrupt
routine has the highest priority.

PSW (Program Status Word, Addresses D0h, Bit-Addressable): The Program Status Word is used to
store a number of important bits that are set and cleared by 8051 instructions. The PSW SFR contains the
carry flag, the auxiliary carry flag, the overflow flag, and the parity flag. Additionally, the PSW register
contains the register bank select flags which are used to select which of the "R" register banks are
currently selected.

ACC (Accumulator, Addresses E0h, Bit-Addressable): The Accumulator is one of the most-used SFRs
on the 8051 since it is involved in so many instructions. The Accumulator resides as an SFR at E0h,
which means the instruction MOV A,#20h is really the same as MOV E0h,#20h. However, it is a good
idea to use the first method since it only requires two bytes whereas the second option requires three
bytes.

B (B Register, Addresses F0h, Bit-Addressable): The "B" register is used in two instructions: the
multiply and divide operations. The B register is also commonly used by programmers as an auxiliary
register to temporarily store values.

Other SFRs

The chart above is a summary of all the SFRs that exist in a standard 8051. All derivative
microcontrollers of the 8051 must support these basic SFRs in order to maintain compatability with the
underlying MSCS51 standard. A common practice when semiconductor firms wish to develop a new
8051 derivative is to add additional SFRs to support new functions that exist in the new chip.

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However, since the DS80C320 provides many new features that the standard 8051 does not, there must be
some way to control and configure these new features. This is accomplished by adding additional SFRs to
those listed here. For example, since the DS80C320 supports two serial ports (as opposed to just one on
the 8051), the SFRs SBUF2 and SCON2 have been added. In addition to all the SFRs listed above, the
DS80C320 also recognizes these two new SFRs as valid and uses their values to determine the mode of
operation of the secondary serial port. Obviously, these new SFRs have been assigned to SFR addresses
that were unused in the original 8051. In this manner, new 8051 derivative chips may be developed which
will run existing 8051 programs.

5. Write Notes On Basic Registers Of Microcontroller

The Accumulator

If you’ve worked with any other assembly languages you will be familiar with the concept of an
Accumulator register.

The Accumulator, as it’s name suggests, is used as a general register to accumulate the results of a large
number of instructions. It can hold an 8-bit (1-byte) value and is the most versatile register the 8051 has
due to the shear number of instructions that make use of the accumulator. More than half of the 8051’s
255 instructions manipulate or use the accumulator in some way.

For example, if you want to add the number 10 and 20, the resulting 30 will be stored in the Accumulator.
Once you have a value in the Accumulator you may continue processing the value or you may store it in
another register or in memory.

The "R" registers

The "R" registers are a set of eight registers that are named R0, R1, etc. up to and including R7.

These registers are used as auxillary registers in many operations. To continue with the above example,
perhaps you are adding 10 and 20. The original number 10 may be stored in the Accumulator whereas the
value 20 may be stored in, say, register R4. To process the addition you would execute the command:

ADD A,R4

After executing this instruction the Accumulator will contain the value 30.

You may think of the "R" registers as very important auxillary, or "helper", registers. The Accumulator
alone would not be very useful if it were not for these "R" registers.

The "R" registers are also used to temporarily store values. For example, let’s say you want to add the
values in R1 and R2 together and then subtract the values of R3 and R4. One way to do this would be:

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MOV A,R3 ;Move the value of R3 into the accumulator ADD A,R4 ;Add the value of R4 MOV
R5,A ;Store the resulting value temporarily in R5 MOV A,R1 ;Move the value of R1 into the
accumulator ADD A,R2 ;Add the value of R2 SUBB A,R5 ;Subtract the value of R5 (which now
contains R3 + R4)

As you can see, we used R5 to temporarily hold the sum of R3 and R4. Of course, this isn’t the most
efficient way to calculate (R1+R2) - (R3 +R4) but it does illustrate the use of the "R" registers as a way to
store values temporarily.

The "B" Register

The "B" register is very similar to the Accumulator in the sense that it may hold an 8-bit (1-byte) value.

The "B" register is only used by two 8051 instructions: MUL AB and DIV AB. Thus, if you want to
quickly and easily multiply or divide A by another number, you may store the other number in "B" and
make use of these two instructions.

Aside from the MUL and DIV instructions, the "B" register is often used as yet another temporary storage
register much like a ninth "R" register.

The Data Pointer (DPTR)

The Data Pointer (DPTR) is the 8051’s only user-accessable 16-bit (2-byte) register. The Accumulator,
"R" registers, and "B" register are all 1-byte values.

DPTR, as the name suggests, is used to point to data. It is used by a number of commands which allow
the 8051 to access external memory. When the 8051 accesses external memory it will access external
memory at the address indicated by DPTR.

While DPTR is most often used to point to data in external memory, many programmers often take
advantge of the fact that it’s the only true 16-bit register available. It is often used to store 2-byte values
which have nothing to do with memory locations.

The Program Counter (PC)

The Program Counter (PC) is a 2-byte address which tells the 8051 where the next instruction to execute
is found in memory. When the 8051 is initialized PC always starts at 0000h and is incremented each time
an instruction is executed. It is important to note that PC isn’t always incremented by one. Since some
instructions require 2 or 3 bytes the PC will be incremented by 2 or 3 in these cases.

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The Program Counter is special in that there is no way to directly modify it’s value. That is to say, you
can’t do something like PC=2430h. On the other hand, if you execute LJMP 2430h you’ve effectively
accomplished the same thing.

It is also interesting to note that while you may change the value of PC (by executing a jump instruction,
etc.) there is no way to read the value of PC. That is to say, there is no way to ask the 8051 "What address
are you about to execute?" As it turns out, this is not completely true: There is one trick that may be used
to determine the current value of PC. This trick will be covered in a later chapter.

The Stack Pointer (SP)

The Stack Pointer, like all registers except DPTR and PC, may hold an 8-bit (1-byte) value. The Stack
Pointer is used to indicate where the next value to be removed from the stack should be taken from.

When you push a value onto the stack, the 8051 first increments the value of SP and then stores the value
at the resulting memory location.

When you pop a value off the stack, the 8051 returns the value from the memory location indicated by
SP, and then decrements the value of SP.

This order of operation is important. When the 8051 is initialized SP will be initialized to 07h. If you
immediately push a value onto the stack, the value will be stored in Internal RAM address 08h. This
makes sense taking into account what was mentioned two paragraphs above: First the 8051 will increment
the value of SP (from 07h to 08h) and then will store the pushed value at that memory address (08h).

SP is modified directly by the 8051 by six instructions: PUSH, POP, ACALL, LCALL, RET, and RETI.
It is also used intrinsically whenever an interrupt is triggered.

6.Explain The Addressing Modes

An "addressing mode" refers to how you are addressing a given memory location. In summary, the
addressing modes are as follows, with an example of each:

Immediate
MOV A,#20h
Addressing

Direct Addressing MOV A,30h

Indirect Addressing MOV A,@R0

External Direct MOVX A,@DPTR

Code Indirect MOVC A,@A+DPTR

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Each of these addressing modes provides important flexibility.

Immediate Addressing

Immediate addressing is so-named because the value to be stored in memory immediately follows the
operation code in memory. That is to say, the instruction itself dictates what value will be stored in
memory.

For example, the instruction:

MOV A,#20h

This instruction uses Immediate Addressing because the Accumulator will be loaded with the value that
immediately follows; in this case 20 (hexidecimal).

Immediate addressing is very fast since the value to be loaded is included in the instruction. However,
since the value to be loaded is fixed at compile-time it is not very flexible.

Direct Addressing

Direct addressing is so-named because the value to be stored in memory is obtained by directly retrieving
it from another memory location. For example:

MOV A,30h

This instruction will read the data out of Internal RAM address 30 (hexidecimal) and store it in the
Accumulator.

Direct addressing is generally fast since, although the value to be loaded isn’t included in the instruction,
it is quickly accessable since it is stored in the 8051’s Internal RAM. It is also much more flexible than
Immediate Addressing since the value to be loaded is whatever is found at the given address--which may
be variable.

Also, it is important to note that when using direct addressing any instruction which refers to an address
between 00h and 7Fh is referring to Internal Memory. Any instruction which refers to an address between
80h and FFh is referring to the SFR control registers that control the 8051 microcontroller itself.

The obvious question that may arise is, "If direct addressing an address from 80h through FFh refers to
SFRs, how can I access the upper 128 bytes of Internal RAM that are available on the 8052?" The answer

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is: You can’t access them using direct addressing. As stated, if you directly refer to an address of 80h
through FFh you will be referring to an SFR. However, you may access the 8052’s upper 128 bytes of
RAM by using the next addressing mode, "indirect addressing."

Indirect Addressing

Indirect addressing is a very powerful addressing mode which in many cases provides an exceptional
level of flexibility. Indirect addressing is also the only way to access the extra 128 bytes of Internal RAM
found on an 8052.

Indirect addressing appears as follows:

MOV A,@R0

This instruction causes the 8051 to analyze the value of the R0 register. The 8051 will then load the
accumulator with the value from Internal RAM which is found at the address indicated by R0.

For example, let’s say R0 holds the value 40h and Internal RAM address 40h holds the value 67h. When
the above instruction is executed the 8051 will check the value of R0. Since R0 holds 40h the 8051 will
get the value out of Internal RAM address 40h (which holds 67h) and store it in the Accumulator. Thus,
the Accumulator ends up holding 67h.

Indirect addressing always refers to Internal RAM; it never refers to an SFR. Thus, in a prior example we
mentioned that SFR 99h can be used to write a value to the serial port. Thus one may think that the
following would be a valid solution to write the value ‘1’ to the serial port:

MOV R0,#99h ;Load the address of the serial port MOV @R0,#01h ;Send 01 to the serial port --
WRONG!!

This is not valid. Since indirect addressing always refers to Internal RAM these two instructions would
write the value 01h to Internal RAM address 99h on an 8052. On an 8051 these two instructions would
produce an undefined result since the 8051 only has 128 bytes of Internal RAM.

External Direct

External Memory is accessed using a suite of instructions which use what I call "External Direct"
addressing. I call it this because it appears to be direct addressing, but it is used to access external
memory rather than internal memory.

There are only two commands that use External Direct addressing mode:

MOVX A,@DPTR MOVX @DPTR,A

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As you can see, both commands utilize DPTR. In these instructions, DPTR must first be loaded with the
address of external memory that you wish to read or write. Once DPTR holds the correct external
memory address, the first command will move the contents of that external memory address into the
Accumulator. The second command will do the opposite: it will allow you to write the value of the
Accumulator to the external memory address pointed to by DPTR.

External Indirect

External memory can also be accessed using a form of indirect addressing which I call External Indirect
addressing. This form of addressing is usually only used in relatively small projects that have a very small
amount of external RAM. An example of this addressing mode is:

MOVX @R0,A

Once again, the value of R0 is first read and the value of the Accumulator is written to that address in
External RAM. Since the value of @R0 can only be 00h through FFh the project would effectively be
limited to 256 bytes of External RAM. There are relatively simple hardware/software tricks that can be
implemented to access more than 256 bytes of memory using External Indirect addressing; however, it is
usually easier to use External Direct addressing if your project has more than 256 bytes of External RAM.

7. Write Notes On Interrupts

An interrupt is a special feature which allows the 8051 to provide the illusion of "multi-tasking," although
in reality the 8051 is only doing one thing at a time. The word "interrupt" can often be subsituted with the
word "event."

An interrupt is triggered whenever a corresponding event occurs. When the event occurs, the 8051
temporarily puts "on hold" the normal execution of the program and executes a special section of code
referred to as an interrupt handler. The interrupt handler performs whatever special functions are required
to handle the event and then returns control to the 8051 at which point program execution continues as if
it had never been interrupted.

The topic of interrupts is somewhat tricky and very important. For that reason, an entire chapter will be
dedicated to the topic. For now, suffice it to say that Interrupts can cause program flow to change.

Interrupts

As the name implies, an interrupt is some event which interrupts normal program execution.

As stated earlier, program flow is always sequential, being altered only by those instructions which
expressly cause program flow to deviate in some way. However, interrupts give us a mechanism to "put

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on hold" the normal program flow, execute a subroutine, and then resume normal program flow as if we
had never left it. This subroutine, called an interrupt handler, is only executed when a certain event
(interrupt) occurs. The event may be one of the timers "overflowing," receiving a character via the serial
port, transmitting a character via the serial port, or one of two "external events." The 8051 may be
configured so that when any of these events occur the main program is temporarily suspended and control
passed to a special section of code which presumably would execute some function related to the event
that occured. Once complete, control would be returned to the original program. The main program never
even knows it was interrupted.

The ability to interrupt normal program execution when certain events occur makes it much easier and
much more efficient to handle certain conditions. If it were not for interrupts we would have to manually
check in our main program whether the timers had overflown, whether we had received another character
via the serial port, or if some external event had occured. Besides making the main program ugly and hard
to read, such a situation would make our program inefficient since we’d be burning precious "instruction
cycles" checking for events that usually don’t happen.

For example, let’s say we have a large 16k program executing many subroutines performing many tasks.
Let’s also suppose that we want our program to automatically toggle the P3.0 port every time timer 0
overflows. The code to do this isn’t too difficult:

JNB TF0,SKIP_TOGGLE CPL P3.0 CLR TF0 SKIP_TOGGLE: ...

Since the TF0 flag is set whenever timer 0 overflows, the above code will toggle P3.0 every time timer 0
overflows. This accomplishes what we want, but is inefficient. The JNB instruction consumes 2
instruction cycles to determine that the flag is not set and jump over the unnecessary code. In the event
that timer 0 overflows, the CPL and CLR instruction require 2 instruction cycles to execute. To make the
math easy, let’s say the rest of the code in the program requires 98 instruction cycles. Thus, in total, our
code consumes 100 instruction cycles (98 instruction cycles plus the 2 that are executed every iteration to
determine whether or not timer 0 has overflowed). If we’re in 16-bit timer mode, timer 0 will overflow
every 65,536 machine cycles. In that time we would have performed 655 JNB tests for a total of 1310
instruction cycles, plus another 2 instruction cycles to perform the code. So to achieve our goal we’ve
spent 1312 instruction cycles. So 2.002% of our time is being spent just checking when to toggle P3.0.
And our code is ugly because we have to make that check every iteration of our main program loop.

Luckily, this isn’t necessary. Interrupts let us forget about checking for the condition. The microcontroller
itself will check for the condition automatically and when the condition is met will jump to a subroutine

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(called an interrupt handler), execute the code, then return. In this case, our subroutine would be nothing
more than:

CPL P3.0 RETI

First, you’ll notice the CLR TF0 command has disappeared. That’s because when the 8051 executes our
"timer 0 interrupt routine," it automatically clears the TF0 flag. You’ll also notice that instead of a normal
RET instruction we have a RETI instruction. The RETI instruction does the same thing as a RET
instruction, but tells the 8051 that an interrupt routine has finished. You must always end your interrupt
handlers with RETI.

Thus, every 65536 instruction cycles we execute the CPL instruction and the RETI instruction. Those two
instructions together require 3 instruction cycles, and we’ve accomplished the same goal as the first
example that required 1312 instruction cycles. As far as the toggling of P3.0 goes, our code is 437 times
more efficient! Not to mention it’s much easier to read and understand because we don’t have to
remember to always check for the timer 0 flag in our main program. We just setup the interrupt and forget
about it, secure in the knowledge that the 8051 will execute our code whenever it’s necessary.

The same idea applies to receiving data via the serial port. One way to do it is to continuously check the
status of the RI flag in an endless loop. Or we could check the RI flag as part of a larger program loop.
However, in the latter case we run the risk of missing characters--what happens if a character is received
right after we do the check, the rest of our program executes, and before we even check RI a second
character has come in. We will lose the first character. With interrupts, the 8051 will put the main
program "on hold" and call our special routine to handle the reception of a character. Thus, we neither
have to put an ugly check in our main code nor will we lose characters.

We can configure the 8051 so that any of the following events will cause an interrupt:

• Timer 0 Overflow.

• Timer 1 Overflow.

• Reception/Transmission of Serial Character.

• External Event 0.

• External Event 1.

In other words, we can configure the 8051 so that when Timer 0 Overflows or when a character is
sent/received, the appropriate interrupt handler routines are called.

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Obviously we need to be able to distinguish between various interrupts and executing different code
depending on what interrupt was triggered. This is accomplished by jumping to a fixed address when a
given interrupt occurs.

By consulting the above chart we see that whenever Timer 0 overflows (i.e., the TF0 bit is set), the main
program will be temporarily suspended and control will jump to 000BH. It is assumed that we have code
at address 000BH that handles the situation of Timer 0 overflowing.

Setting Up Interrupts

By default at powerup, all interrupts are disabled. This means that even if, for example, the TF0 bit is set,
the 8051 will not execute the interrupt. Your program must specifically tell the 8051 that it wishes to
enable interrupts and specifically which interrupts it wishes to enable.

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As you can see, each of the 8051’s interrupts has its own bit in the IE SFR. You enable a given interrupt
by setting the corresponding bit. For example, if you wish to enable Timer 1 Interrupt, you would execute
either:

MOV IE,#08h

or

SETB ET1

Both of the above instructions set bit 3 of IE, thus enabling Timer 1 Interrupt. Once Timer 1 Interrupt is
enabled, whenever the TF1 bit is set, the 8051 will automatically put "on hold" the main program and
execute the Timer 1 Interrupt Handler at address 001Bh.

However, before Timer 1 Interrupt (or any other interrupt) is truly enabled, you must also set bit 7 of IE.
Bit 7, the Global Interupt Enable/Disable, enables or disables all interrupts simultaneously. That is to say,
if bit 7 is cleared then no interrupts will occur, even if all the other bits of IE are set. Setting bit 7 will
enable all the interrupts that have been selected by setting other bits in IE. This is useful in program
execution if you have time-critical code that needs to execute. In this case, you may need the code to
execute from start to finish without any interrupt getting in the way. To accomplish this you can simply
clear bit 7 of IE (CLR EA) and then set it after your time-criticial code is done.

So, to sum up what has been stated in this section, to enable the Timer 1 Interrupt the most common
approach is to execute the following two instructions:

SETB ET1 SETB EA

Thereafter, the Timer 1 Interrupt Handler at 01Bh will automatically be called whenever the TF1 bit is set
(upon Timer 1 overflow).

Polling Sequence

The 8051 automatically evaluates whether an interrupt should occur after every instruction. When
checking for interrupt conditions, it checks them in the following order:

• External 0 Interrupt

• Timer 0 Interrupt

• External 1 Interrupt

• Timer 1 Interrupt

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• Serial Interrupt

This means that if a Serial Interrupt occurs at the exact same instant that an External 0 Interrupt occurs,
the External 0 Interrupt will be executed first and the Serial Interrupt will be executed once the External 0
Interrupt has completed.

Interrupt Priorities

The 8051 offers two levels of interrupt priority: high and low. By using interrupt priorities you may
assign higher priority to certain interrupt conditions.

For example, you may have enabled Timer 1 Interrupt which is automatically called every time Timer 1
overflows. Additionally, you may have enabled the Serial Interrupt which is called every time a character
is received via the serial port. However, you may consider that receiving a character is much more
important than the timer interrupt. In this case, if Timer 1 Interrupt is already executing you may wish
that the serial interrupt itself interrupts the Timer interrupt. When the serial interrupt is complete, control
passes back to Timer 1 Interrupt and finally back to the main program. You may accomplish this by
assigning a high priority to the Serial Interrupt and a low priority to the Timer 1 Interrupt.

Interrupt priorities are controlled by the IP SFR (B8h). The IP SFR has the following format:

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8. Write Notes On Timers

The 8051 comes equipped with two timers, both of which may be controlled, set, read, and configured
individually. The 8051 timers have three general functions: 1) Keeping time and/or calculating the
amount of time between events, 2) Counting the events themselves, or 3) Generating baud rates for the
serial port.

The three timer uses are distinct so we will talk about each of them separately. The first two uses will be
discussed in this chapter while the use of timers for baud rate generation will be discussed in the chapter
relating to serial ports.

How does a timer count?

How does a timer count? The answer to this question is very simple: A timer always counts up. It doesn’t
matter whether the timer is being used as a timer, a counter, or a baud rate generator: A timer is always
incremented by the microcontroller.

USING TIMERS TO MEASURE TIME

Obviously, one of the primary uses of timers is to measure time. We will discuss this use of timers first
and will subsequently discuss the use of timers to count events. When a timer is used to measure time it is
also called an "interval timer" since it is measuring the time of the interval between two events.

How long does a timer take to count?

First, it’s worth mentioning that when a timer is in interval timer mode (as opposed to event counter
mode) and correctly configured, it will increment by 1 every machine cycle. As you will recall from the

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previous chapter, a single machine cycle consists of 12 crystal pulses. Thus a running timer will be
incremented:

11,059,000 / 12 = 921,583

921,583 times per second. Unlike instructions--some of which require 1 machine cycle, others 2, and
others 4--the timers are consistent: They will always be incremented once per machine cycle. Thus if a
timer has counted from 0 to 50,000 you may calculate:

50,000 / 921,583 = .0542

.0542 seconds have passed. In plain English, about half of a tenth of a second, or one-twentieth of a
second.

Obviously it’s not very useful to know .0542 seconds have passed. If you want to execute an event once
per second you’d have to wait for the timer to count from 0 to 50,000 18.45 times. How can you wait
"half of a time?" You can’t. So we come to another important calculation.

Let’s say we want to know how many times the timer will be incremented in .05 seconds. We can do
simple multiplication:

.05 * 921,583 = 46,079.15.

This tells us that it will take .05 seconds (1/20th of a second) to count from 0 to 46,079. Actually, it will
take it .049999837 seconds--so we’re off by .000000163 seconds--however, that’s close enough for
government work. Consider that if you were building a watch based on the 8051 and made the above
assumption your watch would only gain about one second every 2 months. Again, I think that’s accurate
enough for most applications--I wish my watch only gained one second every two months!

Obviously, this is a little more useful. If you know it takes 1/20th of a second to count from 0 to 46,079
and you want to execute some event every second you simply wait for the timer to count from 0 to 46,079
twenty times; then you execute your event, reset the timers, and wait for the timer to count up another 20
times. In this manner you will effectively execute your event once per second, accurate to within
thousandths of a second.

Thus, we now have a system with which to measure time. All we need to review is how to control the
timers and initialize them to provide us with the information we need.

Timer SFRs

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As mentioned before, the 8051 has two timers which each function essentially the same way. One timer is
TIMER0 and the other is TIMER1. The two timers share two SFRs (TMOD and TCON) which control
the timers, and each timer also has two SFRs dedicated solely to itself (TH0/TL0 and TH1/TL1).

We’ve given SFRs names to make it easier to refer to them, but in reality an SFR has a numeric address.
It is often useful to know the numeric address that corresponds to an SFR name. The SFRs relating to
timers are:

When you enter the name of an SFR into an assembler, it internally converts it to a number. For example,
the command:

MOV TH0,#25h

moves the value 25h into the TH0 SFR. However, since TH0 is the same as SFR address 8Ch this
command is equivalent to:

MOV 8Ch,#25h

Now, back to the timers. First, let’s talk about Timer 0.

Timer 0 has two SFRs dedicated exclusively to itself: TH0 and TL0. Without making things too
complicated to start off with, you may just think of this as the high and low byte of the timer. That is to
say, when Timer 0 has a value of 0, both TH0 and TL0 will contain 0. When Timer 0 has the value 1000,
TH0 will hold the high byte of the value (3 decimal) and TL0 will contain the low byte of the value (232
decimal). Reviewing low/high byte notation, recall that you must multiply the high byte by 256 and add
the low byte to calculate the final value. That is to say:

TH0 * 256 + TL0 = 1000 3 * 256 + 232 = 1000

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Timer 1 works the exact same way, but it’s SFRs are TH1 and TL1.

Since there are only two bytes devoted to the value of each timer it is apparent that the maximum value a
timer may have is 65,535. If a timer contains the value 65,535 and is subsequently incremented, it will
reset--or overflow--back to 0.

The TMOD SFR

Let’s first talk about our first control SFR: TMOD (Timer Mode). The TMOD SFR is used to control the
mode of operation of both timers. Each bit of the SFR gives the microcontroller specific information
concerning how to run a timer. The high four bits (bits 4 through 7) relate to Timer 1 whereas the low
four bits (bits 0 through 3) perform the exact same functions, but for timer 0.

The individual bits of TMOD have the following functions:

TMOD (89h) SFR

As you can see in the above chart, four bits (two for each timer) are used to specify a mode of operation.
The modes of operation are:

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13-bit
Time Mode (mode 0)

Timer mode "0" is a 13-bit timer. This is a relic that was kept around in the 8051 to maintain
compatability with it’s predecesor, the 8048. Generally the 13-bit timer mode is not used in new
development.

When the timer is in 13-bit mode, TLx will count from 0 to 31. When TLx is incremented from 31, it will
"reset" to 0 and increment THx. Thus, effectively, only 13 bits of the two timer bytes are being used: bits
0-4 of TLx and bits 0-7 of THx. This also means, in essence, the timer can only contain 8192 values. If
you set a 13-bit timer to 0, it will overflow back to zero 8192 machine cycles later.

Again, there is very little reason to use this mode and it is only mentioned so you won’t be surprised if
you ever end up analyzing archaeic code which has been passed down through the generations (a
generation in a programming shop is often on the order of about 3 or 4 months).

16-bit Time Mode (mode 1)

Timer mode "1" is a 16-bit timer. This is a very commonly used mode. It functions just like 13-bit mode
except that all 16 bits are used.

TLx is incremented from 0 to 255. When TLx is incremented from 255, it resets to 0 and causes THx to
be incremented by 1. Since this is a full 16-bit timer, the timer may contain up to 65536 distinct values. If
you set a 16-bit timer to 0, it will overflow back to 0 after 65,536 machine cycles.

8-bit Time Mode (mode 2)

Timer mode "2" is an 8-bit auto-reload mode. What is that, you may ask? Simple. When a timer is in
mode 2, THx holds the "reload value" and TLx is the timer itself. Thus, TLx starts counting up. When
TLx reaches 255 and is subsequently incremented, instead of resetting to 0 (as in the case of modes 0 and
1), it will be reset to the value stored in THx.

For example, let’s say TH0 holds the value FDh and TL0 holds the value FEh. If we were to watch the
values of TH0 and TL0 for a few machine cycles this is what we’d see:

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As you can see, the value of TH0 never changed. In fact, when you use mode 2 you almost always set
THx to a known value and TLx is the SFR that is constantly incremented.

What’s the benefit of auto-reload mode? Perhaps you want the timer to always have a value from 200 to
255. If you use mode 0 or 1, you’d have to check in code to see if the timer had overflowed and, if so,
reset the timer to 200. This takes precious instructions of execution time to check the value and/or to
reload it. When you use mode 2 the microcontroller takes care of this for you. Once you’ve configured a
timer in mode 2 you don’t have to worry about checking to see if the timer has overflowed nor do you
have to worry about resetting the value--the microcontroller hardware will do it all for you.

The auto-reload mode is very commonly used for establishing a baud rate which we will talk more about
in the Serial Communications chapter.

Split Timer Mode (mode 3)

Timer mode "3" is a split-timer mode. When Timer 0 is placed in mode 3, it essentially becomes two
separate 8-bit timers. That is to say, Timer 0 is TL0 and Timer 1 is TH0. Both timers count from 0 to 255
and overflow back to 0. All the bits that are related to Timer 1 will now be tied to TH0.

While Timer 0 is in split mode, the real Timer 1 (i.e. TH1 and TL1) can be put into modes 0, 1 or 2
normally--however, you may not start or stop the real timer 1 since the bits that do that are now linked to
TH0. The real timer 1, in this case, will be incremented every machine cycle no matter what.

The only real use I can see of using split timer mode is if you need to have two separate timers and,
additionally, a baud rate generator. In such case you can use the real Timer 1 as a baud rate generator and
use TH0/TL0 as two separate timers.

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The TCON SFR

Finally, there’s one more SFR that controls the two timers and provides valuable information about them.
The TCON SFR has the following structure:

TCON (88h) SFR

As you may notice, we’ve only defined 4 of the 8 bits. That’s because the other 4 bits of the SFR don’t
have anything to do with timers--they have to do with Interrupts and they will be discussed in the chapter
that addresses interrupts.

A new piece of information in this chart is the column "bit address." This is because this SFR is "bit-
addressable." What does this mean? It means if you want to set the bit TF1--which is the highest bit of
TCON--you could execute the command:

MOV TCON, #80h

... or, since the SFR is bit-addressable, you could just execute the command:

SETB TF1

This has the benefit of setting the high bit of TCON without changing the value of any of the other bits of
the SFR. Usually when you start or stop a timer you don’t want to modify the other values in TCON, so
you take advantage of the fact that the SFR is bit-addressable.

Initializing a Timer

Now that we’ve discussed the timer-related SFRs we are ready to write code that will initialize the timer
and start it running.

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As you’ll recall, we first must decide what mode we want the timer to be in. In this case we want a 16-bit
timer that runs continuously; that is to say, it is not dependent on any external pins.

We must first initialize the TMOD SFR. Since we are working with timer 0 we will be using the lowest 4
bits of TMOD. The first two bits, GATE0 and C/T0 are both 0 since we want the timer to be independent
of the external pins. 16-bit mode is timer mode 1 so we must clear T0M1 and set T0M0. Effectively, the
only bit we want to turn on is bit 0 of TMOD. Thus to initialize the timer we execute the instruction:

MOV TMOD,#01h

Timer 0 is now in 16-bit timer mode. However, the timer is not running. To start the timer running we
must set the TR0 bit We can do that by executing the instruction:

SETB TR0

Upon executing these two instructions timer 0 will immediately begin counting, being incremented once
every machine cycle (every 12 crystal pulses).

Reading the Timer

There are two common ways of reading the value of a 16-bit timer; which you use depends on your
specific application. You may either read the actual value of the timer as a 16-bit number, or you may
simply detect when the timer has overflowed.

Reading the value of a Timer

If your timer is in an 8-bit mode--that is, either 8-bit AutoReload mode or in split timer mode--then
reading the value of the timer is simple. You simply read the 1-byte value of the timer and you’re done.

However, if you’re dealing with a 13-bit or 16-bit timer the chore is a little more complicated. Consider
what would happen if you read the low byte of the timer as 255, then read the high byte of the timer as 15.
In this case, what actually happened was that the timer value was 14/255 (high byte 14, low byte 255) but
you read 15/255. Why? Because you read the low byte as 255. But when you executed the next
instruction a small amount of time passed--but enough for the timer to increment again at which time the
value rolled over from 14/255 to 15/0. But in the process you’ve read the timer as being 15/255.
Obviously there’s a problem there.

The solution? It’s not too tricky, really. You read the high byte of the timer, then read the low byte, then
read the high byte again. If the high byte read the second time is not the same as the high byte read the
first time you repeat the cycle. In code, this would appear as:

REPEAT: MOV A,TH0

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MOV R0,TL0

CJNE A,TH0,REPEAT

...

In this case, we load the accumulator with the high byte of Timer 0. We then load R0 with the low byte of
Timer 0. Finally, we check to see if the high byte we read out of Timer 0--which is now stored in the
Accumulator--is the same as the current Timer 0 high byte. If it isn’t it means we’ve just "rolled over" and
must reread the timer’s value--which we do by going back to REPEAT. When the loop exits we will have
the low byte of the timer in R0 and the high byte in the Accumulator.

Another much simpler alternative is to simply turn off the timer run bit (i.e. CLR TR0), read the timer
value, and then turn on the timer run bit (i.e. SETB TR0). In that case, the timer isn’t running so no
special tricks are necessary. Of course, this implies that your timer will be stopped for a few machine
cycles. Whether or not this is tolerable depends on your specific application.

Detecting Timer Overflow

Often it is necessary to just know that the timer has reset to 0. That is to say, you are not particularly
interest in the value of the timer but rather you are interested in knowing when the timer has overflowed
back to 0.

Whenever a timer overflows from it’s highest value back to 0, the microcontroller automatically sets the
TFx bit in the TCON register. This is useful since rather than checking the exact value of the timer you
can just check if the TFx bit is set. If TF0 is set it means that timer 0 has overflowed; if TF1 is set it
means that timer 1 has overflowed.

We can use this approach to cause the program to execute a fixed delay. As you’ll recall, we calculated
earlier that it takes the 8051 1/20th of a second to count from 0 to 46,079. However, the TFx flag is set
when the timer overflows back to 0. Thus, if we want to use the TFx flag to indicate when 1/20th of a
second has passed we must set the timer initially to 65536 less 46079, or 19,457. If we set the timer to
19,457, 1/20th of a second later the timer will overflow. Thus we come up with the following code to
execute a pause of 1/20th of a second:

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MOV TH0,#76;High byte of 19,457 (76 * 256 = 19,456) MOV TL0,#01;Low byte of 19,457
(19,456 + 1 = 19,457) MOV TMOD,#01;Put Timer 0 in 16-bit mode SETB TR0;Make Timer 0
start counting JNB TF0,$;If TF0 is not set, jump back to this same instruction

In the above code the first two lines initialize the Timer 0 starting value to 19,457. The next two
instructions configure timer 0 and turn it on. Finally, the last instruction JNB TF0,$, reads "Jump, if TF0
is not set, back to this same instruction." The "$" operand means, in most assemblers, the address of the
current instruction. Thus as long as the timer has not overflowed and the TF0 bit has not been set the
program will keep executing this same instruction. After 1/20th of a second timer 0 will overflow, set the
TF0 bit, and program execution will then break out of the loop.

Setting the Serial Port Baud Rate

Once the Serial Port Mode has been configured, as explained above, the program must configure the
serial port’s baud rate. This only applies to Serial Port modes 1 and 3. The Baud Rate is determined based
on the oscillator’s frequency when in mode 0 and 2. In mode 0, the baud rate is always the oscillator
frequency divided by 12. This means if you’re crystal is 11.059Mhz, mode 0 baud rate will always be
921,583 baud. In mode 2 the baud rate is always the oscillator frequency divided by 64, so a 11.059Mhz
crystal speed will yield a baud rate of 172,797.

In modes 1 and 3, the baud rate is determined by how frequently timer 1 overflows. The more frequently
timer 1 overflows, the higher the baud rate. There are many ways one can cause timer 1 to overflow at a
rate that determines a baud rate, but the most common method is to put timer 1 in 8-bit auto-reload mode
(timer mode 2) and set a reload value (TH1) that causes Timer 1 to overflow at a frequency appropriate to
generate a baud rate.

To determine the value that must be placed in TH1 to generate a given baud rate, we may use the
following equation (assuming PCON.7 is clear).

TH1 = 256 - ((Crystal / 384) / Baud)

If PCON.7 is set then the baud rate is effectively doubled, thus the equation becomes:

TH1 = 256 - ((Crystal / 192) / Baud)

For example, if we have an 11.059Mhz crystal and we want to configure the serial port to 19,200 baud we
try plugging it in the first equation:

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TH1 = 256 - ((Crystal / 384) / Baud) TH1 = 256 - ((11059000 / 384) / 19200 ) TH1 = 256 -
((28,799) / 19200) TH1 = 256 - 1.5 = 254.5

As you can see, to obtain 19,200 baud on a 11.059Mhz crystal we’d have to set TH1 to 254.5. If we set it
to 254 we will have achieved 14,400 baud and if we set it to 255 we will have achieved 28,800 baud.
Thus we’re stuck...

But not quite... to achieve 19,200 baud we simply need to set PCON.7 (SMOD). When we do this we
double the baud rate and utilize the second equation mentioned above. Thus we have: TH1 = 256 -
((Crystal / 192) / Baud) TH1 = 256 - ((11059000 / 192) / 19200) TH1 = 256 - ((57699) / 19200) TH1 =
256 - 3 = 253

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QUESTION BANK

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QUESTION BANK

TWO MARKS

UNIT I

1. What is Microprocessor?
2. What are the basic units of a microprocessor?
3. What is Software and Hardware?
4. What is assembly language?
5. What are machine language and assembly language programs?
6. What is the drawback in machine language and assembly language programs?
7. Define bit, byte and word.
8. What is a bus?
9. Why data bus is bi-directional?
10. Why address bus is unidirectional?
11. What is the function of microprocessor in a system?
12. What are the modes in which 8086 can operate?
13. What is the data and address size in 8086?
14. Explain the function of M/IO in 8086.
15. Write the flags of 8086.

UNIT II

16. What are the interrupts of 8086?

17. How clock signal is generated in 8086? What is the maximum internalclock frequency of
8086?
18. Write the special functions carried by the general purpose registers of8086.
19. What is pipelined architecture?
20. What are the functional units available in 8086 architecture?
21. List the segment registers of 8086.
22. Define machine cycle.
23. Define T-State.
24. List the components of microprocessor (single board microcomputer)based system
25. When the 8085 processor checks for an interrupt?
26. What is interrupt acknowledge cycle?
27. How the interrupts are affected by system reset?
28. What is Software interrupts?
29. What is Hardware interrupt?
30. What is the difference between Hardware and Software interrupt?
31. What is Vectored and Non- Vectored interrupt?
32. List the Software and Hardware interrupts of 8085?
33. What is TRAP?
34. Whether HOLD has higher priority than TRAP or not?
35. What is masking and why it is required?
36. When the 8085 processor accept hardware interrupt?
37. When the 8085 processor will disable the interrupt system?

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38. What is the function performed by Dl instruction?

39. What is the function performed by El instruction?
40. How the vector address is generated for the INTR interrupt of 8085?
41. What is the Hardware interrupts of 8085?
42. Which interrupt has highest priority in 8085? What is the priority ofother interrupts?

UNIT III

43. Why interfacing is needed for 1/0 devices?

44. What is the difference between CPU bus and system bus?
45. What does memory-mapping mean?
46. What is interrupt 1/0?
47. Why EPROM is mapped at the beginning of memory space in 8085system?
48. What is the need for system clock and how it is generated in 8085?
49. What is DMA?
50. What is the need for Port?
51. What is a port?
52. Give some examples of port devices used in 8085 microprocessor based system?
53. Write a short note on INTEL 8255?
54. What is the drawback in memory mapped I/0?
55. How DMA is initiated?
56. What is processor cycle (Machine cycle)?
57. What is Instruction cycle?
58. What is fetch and execute cycle?
59. What is Block and Demand transfer mode DMA?
60. What is the need for timing diagram?
61. How many machine cycles constitute one instruction cycle in 8085?
62. Define opcode and operand.
63. What is opcode fetch cycle?
64. What operation is performed during first T -state of every machine cyclein 8085 ?
65. Why status signals are provided in microprocessor?
66. How the 8085 processor differentiates a memory access (read/write)and 1/0 access
(read/write)?
67. How clock signals are generated in 8085 and what is the frequency ofthe internal clock?
68. What happens to the 8085 processor when it is reset?
69. What are the operations performed by ALU of 8085?
70. What is a flag?
71. List the flags of 8085
72 What is ALE?
73. Explain the function of IO/M in 8085.
74. Where is the READY signal used?
75. What is HOLD and HLDA and how it is used?
76. What is Polling?
77. What are the different types of Polling?

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78. What is the need for interrupt controller?

79. List some of the features of INTEL 8259 (Programmable Interrupt
Controller)
80. What is a programmable peripheral device?
81. What is synchronous data transfer scheme?
82. What is asynchronous data transfer scheme?
83. What are the operating modes of 8212?
84. Explain the working of a handshake output port
85. What are the internal devices of 8255?
86. What is baud rate?
87. What is USART?
88. What are the functions performed by INTEL 8251A?
89. What is an Interrupt?
90. What are the control words of 8251A and what are its functions?
91. What is the information that can be obtained from the status word of8251?
92. Give some examples of input devices to microprocessor-based system.
93. What are the tasks involved in keyboard interface?
94. How a keyboard matrix is formed in keyboard interface using 8279?
95. What is scanning in keyboard and what is scan time?
96. What is scanning in display and what is the scan time?
97. What are the internal devices of a typical DAC?
98. What is settling or conversion time in DAC?
99. What are the different types of ADC?
100. Define stack
101. What is program counter? How is it useful in program execution?
102. How the microprocessor is synchronized with peripherals?
103. What is a minimum system and how it is formed in 8085?

UNIT V

104. What is meant by microcontroller?

105. List the features of 8051 microcontroller?
106. Explain the operating mode0 of 8051 serial ports?
107 Explain the operating mode2 of 8051 serial ports?
108. Explain the mode3 of 8051 serial ports?
109. Explain the interrupts of 8051 microcontroller?
110. Write a program to perform multiplication of 2 numbers using 8051?
111. Write a program to mask the 0th &7th bit using 8051?
112. List the addressing modes of 8051?
113. Write about CALL statement in 8051?
114. Write about the jump statement?
115. Write program to load accumulator, DPH&DPL using 8051?
116. Write a program to find the 2’s complement using 8051?
117. Write a program to add 2 8-bit numbers using 8051?
118. Write a program to swap two numbers using 8051?
119. Write a program to subtract 2 8-bit numbers &exchange the digits using8051?

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120. Write a program to subtract the contents of R1 of Bank 0from the contentsof R0 of Bank 2
using 8051?

11 MARKS

1. Draw & explain the architecture of 8085 microprocessor

• Block Diagram
• Registers Available
• Function Of Accumulator
• Explanation about all blocks in the block diagram

2. Draw the Pin Diagram of 8085 and explain the function of various signals.
• Pin Diagram
• Explanation about all signals

3. Explain the instruction classification & instruction sets

• Data Transfer Instructions
• Arithmetic Instructions
• Logical Instructions
• Branch Instructions
• Machine Control Instructions

4. Write a program to sort the numbers in ascending and descending order.

• Program
• Result Verification

5.Draw the timing diagram of the following Instructions

• PUSH
• IN Port A
• STA 5000
• MVI A, 08
• Explain the machine cycles needed for every Instructions and
draw the timing diagram

6. Explain the 8085 based microcomputer system

7. With neat sketch explain the functions of 8255 PPI.

• Block Diagram
• Explanation about all the ports available.
• Explanation about the modes of transfer
• Explain the control Word Register

8. With neat sketch explain the functions of 8251.

• Block Diagram

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CS T42 - MICROPROCESSORS AND MICROCONTROLLERS Dept of CSE

• Types of data transfer

• Explanation about all the blocks.
• Explain the control Word Register, Status Register

9. With neat sketch explain the function of DMA contoller.

• Block Diagram
• Explanation about all blocks in the block diagram

10.With neat sketch explain the function of Programmable Interrupt Controller.

• Block Diagram
• Explanation about all blocks in the block diagram

11.With neat sketch explain the function of Keyboard and display controller.
• Block Diagram
• Types of Display Available
• Types of keys available
• Explanation about all blocks in the block diagram

12. With neat sketch explain the function of A/D converter.

• Fundamental steps
• Figure
• Explain the functions.

13. With neat sketch explain the function of D/A converter.

• Fundamental steps
• Figure
• Explain the functions.

14.With neat sketch explain the architecture of 8051 microcontroller.

• Block Diagram
• Explanation about all blocks in the block diagram

15. Draw the Pin Diagram of 8051 and explain the function of various
signals.
• Pin Diagram
• Explanation about all signals

16. List the various Instruction available in 8051 microcontroller.

• Data Transfer Instructions
• Arithmetic Instructions
• Logical Instructions
• Boolean variable Manipulation Instructions
• Program and Machine Control Instructions

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