a Dual/Quad Low Power, High Speed

JFET Operational Amplifiers

OP282/OP482
FEATURES PIN CONNECTIONS
High Slew Rate: 9 V/ms 8-Lead Narrow-Body SOIC 8-Lead Epoxy DIP
Wide Bandwidth: 4 MHz (S Suffix) (P Suffix)
Low Supply Current: 250 mA/Amplifier
Low Offset Voltage: 3 mV OUT A 1 8 V+ OUT A 1 8 V+
Low Bias Current: 100 pA OP282
–IN A 2 7 OUT B –IN A 2 7 OUT B
Fast Settling Time OP282
+IN A 3 6 –IN B +IN A 3 6 –IN B
Common-Mode Range Includes V+
Unity Gain Stable V– 4 5 +IN B V– 4 5 +IN B
OP-482

APPLICATIONS
Active Filters
Fast Amplifiers 14-Lead Epoxy DIP 14-Lead Narrow-Body SOIC
Integrators (P Suffix) (S Suffix)
Supply Current Monitoring
OUT A 1 14 OUT D OUT A 1 14 OUT B

–IN A 2 13 –IN D –IN A 2 13 –IN D

+IN A 3 12 +IN D +IN A 3 12 +IN D

GENERAL DESCRIPTION OP482
The OP282/OP482 dual and quad operational amplifiers feature V+ 4 OP482 11 V– V+ 4 11 V–

excellent speed at exceptionally low supply currents. Slew rate +IN B 5 10 +IN C +IN B 5 10 +IN C

exceeds 7 V/µs with supply current under 250 µA per amplifier. –IN B 6 9 –IN C –IN B 6 9 –IN C
These unity gain stable amplifiers have a typical gain bandwidth OUT B 7 8 OUT C OUT B 7 8 OUT C
of 4 MHz.
The JFET input stage of the OP282/OP482 insures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 volts of each supply, low
power consumption and high slew rate, the OP282/OP482 are
ideal for battery-powered systems or power restricted applica-
tions. An input common-mode range that includes the positive
supply makes the OP282/OP482 an excellent choice for high-
side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. Both dual and quad amplifiers are available
in plastic and ceramic DIP plus SOIC surface mount packages.

REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703
OP282/OP482–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = 615.0 V, T S A = +258C unless otherwise noted)
Parameter Symbol Conditions Min Typ Max Units
INPUT CHARACTERISTICS
Offset Voltage VOS OP282 0.2 3 mV
OP282, –40 ≤ TA ≤ +85°C 4.5 mV
Offset Voltage VOS OP482 0.2 4 mV
OP482, –40 ≤ TA ≤ +85°C 6 mV
Input Bias Current IB VCM = 0 V 3 100 pA
VCM = 0 V, Note 1 500 pA
Input Offset Current IOS VCM = 0 V 1 50 pA
VCM = 0 V, Note 1 250 pA
Input Voltage Range –11 +15 V
Common-Mode Rejection CMR –11 V ≤ VCM ≤ +15 V, –40 ≤ TA ≤ +85°C 70 90 dB
Large Signal Voltage Gain AVO RL = 10 kΩ 20 V/mV
RL = 10 kΩ, –40 ≤ TA ≤ +85°C 15 V/mV
Offset Voltage Drift ∆VOS/∆T 10 µV/°C
Bias Current Drift ∆IB/∆T 8 pA/°C
OUTPUT CHARACTERISTICS
Output Voltage Swing VO RL = 10 kΩ –13.5 ± 13.9 13.5 V
Short Circuit Limit ISC Source 3 10 mA
Sink –8 –12 mA
Open-Loop Output Impedance ZOUT f = 1 MHz 200 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VS = ± 4.5 V to ± 18 V,
–40 ≤ TA ≤ +85°C 25 316 µV/V
Supply Current/Amplifier ISY VO = 0 V, 40 ≤ TA ≤ +85°C 210 250 µA
Supply Voltage Range VS ± 4.5 ± 18 V
DYNAMIC PERFORMANCE
Slew Rate SR RL = 10 kΩ 7 9 V/µs
Full-Power Bandwidth BWP 1% Distortion 125 kHz
Settling Time tS To 0.01% 1.6 µs
Gain Bandwidth Product GBP 4 MHz
Phase Margin ØO 55 Degrees
NOISE PERFORMANCE
Voltage Noise en p-p 0.1 Hz to 10 Hz 1.3 µV p-p
Voltage Noise Density en f = 1 kHz 36 nV/√Hz
Current Noise Density in 0.01 pA/√Hz
NOTE
1
The input bias and offset currents are tested at TA = TJ = +85°C. Bias and offset currents are guaranteed but not tested at –40 °C.
Specifications subject to change without notice.

WAFER TEST LIMITS (@ V = 615.0 V, T = +258C unless otherwise noted)

S A

Parameter Symbol Conditions Limit Units

Offset Voltage VOS OP282 3 mV max
Offset Voltage VOS OP482 4 mV max
Input Bias Current IB VCM = 0 V 100 pA max
Input Offset Current IOS VCM = 0 V 50 pA max
Input Voltage Range 1 –11, +15 V min/max
Common-Mode Rejection CMRR –11 V ≤ VCM ≤ +15 V 70 dB min
Power Supply Rejection Ratio PSRR V = ± 4.5 V to ± 18 V 316 µV/V
Large Signal Voltage Gain AVO RL = 10 kΩ 20 V/mV min
Output Voltage Range VO RL = 10 kΩ ± 13.5 V min
Supply Current/Amplifier ISY VO = 0 V, RL = ∞ 250 µA max
NOTES
Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard
product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.
1
Guaranteed by CMR test.
Specifications subject to change without notice.

–2– REV. B
 OP282/OP482
ABSOLUTE MAXIMUM RATINGS DICE CHARACTERISTICS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V
Differential Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . 36 V
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Storage Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Operating Temperature Range
OP282A, OP482A . . . . . . . . . . . . . . . . . . –55°C to +125°C
OP282G, OP482G . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Junction Temperature Range
P, S Packages . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Lead Temperature Range (Soldering, 60 sec) . . . . . . +300°C

Package Type uJA2 uJC Units

8-Pin Plastic DIP (P) 103 43 °C/W OP282 Die Size 0.063 3 0.060 Inch, 3,780 Sq. Mils
8-Pin SOIC (S) 158 43 °C/W
14-Pin Plastic DIP (P) 83 39 °C/W
14-Pin SOIC (S) 120 36 °C/W
NOTES
1
For supply voltages less than ± 18 V, the absolute maximum input voltage is
equal to the supply voltage.
2
θJA is specified for the worst case conditions, i.e., θJA is specified for device in
socket for cerdip, P-DIP; θJA is specified for device soldered in circuit board for
SOIC package.

ORDERING GUIDE

Temperature Package Package

Model Range Description Option
OP282GP –40°C to +85°C 8-Pin Plastic DIP N-8
OP282GS –40°C to +85°C 8-Pin SOIC SO-8
OP482GP –40°C to +85°C 14-Pin Plastic DIP N-14
OP482GS –40°C to +85°C 14-Pin SOIC SO-14

OP482 Die Size 0.070 3 0.098 Inch, 6,860 Sq. Mils

REV. B –3–
OP282/OP482
APPLICATIONS INFORMATION PHASE INVERSION
The OP282 and OP482 are single and dual JFET op amps that Most JFET-input amplifiers will invert the phase of the input
have been optimized for high speed at low power. This signal if either input exceeds the input common-mode range.
combination makes these amplifiers excellent choices for battery For the OP282 and OP482 negative signals in excess of approxi-
powered or low power applications requiring above average mately 14 volts will cause phase inversion. The cause of this
performance. Applications benefiting from this performance effect is saturation of the input stage leading to the forward-
combination include telecom, geophysical exploration, portable biasing of a drain-gate diode. A simple fix for this in noninverting
medical equipment and navigational instrumentation. applications is to place a resistor in series with the noninverting
input. This limits the amount of current through the forward-
HIGH SIDE SIGNAL CONDITIONING biased diode and prevents the shutting down of the output
There are many applications that require the sensing of signals stage. For the OP282/OP482, a value of 200 kΩ has been found
near the positive rail. OP282s and OP482s have been tested and to work. However, this adds a significant amount of noise.
guaranteed over a common-mode range (–11 V ≤ VCM ≤ +15 V)
15
that includes the positive supply.
One application where this is commonly used is in the sensing of 10
power supply currents. This enables it to be used in current
sensing applications such as the partial circuit shown in Figure
5
1. In this circuit, the voltage drop across a low value resistor,
such as the 0.1 Ω shown here, is amplified and compared to 7.5

V IN
volts. The output can then be used for current limiting. 0

+15V 0.1 Ω -5

500k
-10
100k
RL
100k
-15
-15 -10 -5 0 5 10 15
VOUT
+ 1/2
OP282
Figure 2. OP282 Phase Reversal
100k
ACTIVE FILTERS
The OP282 and OP482’s wide bandwidth and high slew rates
make either an excellent choice for many filter applications.
Figure 1. Phase Inversion There are many types of active filter configurations, but the four
most popular configurations are Butterworth, elliptical, Bessel,
and Chebyshev. Each type has a response that is optimized for a
given characteristic as shown in Table I.

PROGRAMMABLE STATE-VARIABLE FILTER

Table I.

Amplitude Amplitude
Type Selectivity Overshoot Phase (Pass Band) (Stop Band)
Butterworth Moderate Good Max Flat
Chebyshev Good Moderate Nonlinear Equal Ripple
Elliptical Best Poor Equal Ripple Equal Ripple
Bessel (Thompson) Poor Best Linear

–4– REV. B
 OP282/OP482
The circuit shown in Figure 3 can be used to accurately 1  D1 
program the “Q,” the cutoff frequency fC, and the gain of a two fc =  
2πR1C1  256 
pole state-variable filter. OP482s have been used in this design
because of their high bandwidths, low power and low noise. where D1 is the digital code for the DAC.
This circuit takes only three packages to build because of the
Gain of this circuit is set by adjusting D3. The gain equation is:
quad configuration of the op amps and DACs.
The DACs shown are all used in the voltage mode so all values R4  D 3 
Gain =  
are dependent only on the accuracy of the DAC and not on the R5  256 
absolute values of the DAC’s resistive ladders. This make this
circuit unusually accurate for a programmable filter. DAC 2 is used to set the “Q” of the circuit. Adjusting this DAC
controls the amount of feedback from the bandpass node to the
Adjusting DAC 1 changes the signal amplitude across R1; input summing node. Note that the digital value of the DAC is
therefore, the DAC attenuation times R1 determines the in the numerator, therefore zero code is not a valid operating point.
amount of signal current that charges the integrating capacitor,
C1. This cutoff frequency can now be expressed as: R2  256 
Q=  
R3  D2 

R7
2k

1/4
R4
DAC8408 2k 1/4
DAC8408 C1
1000pF 1/4 C1
VIN R5 DAC8408 1000pF
- 2k
R1
- -
+ 2k
- R1
1/4 + + 2k
OP482 1/4 + - -
1/4
OP482 OP482
1/4 + +
1/4 LOW
OP482
OP482 1/4 PASS
HIGH PASS OP482

R6
2k 1/4
R3 DAC8408
2k
BANDPASS
R2

-
1k -
+ 1/4
+
1/4 OP482
OP482

Figure 3.

REV. B –5–
OP282/OP482
OP282/OP482 SPICE MACRO MODEL minor changes in the circuit values. Contact ADI for a copy of
Figure 4 shows the OP282 SPICE macro model. The model for the latest SPICE model diskette for both listings.
the OP482 is similar to that of the OP282, but there are some

99

I1
V2

8
4
9 D1
IN-
J1 J2
G1 R5
2 7
R2 C3

IOS CIN 3
EOS 98
1 R1 5 6
EREF D2
C2
IN+ 10
R3 R4
V3

50

C4 C14

13 14 19
11 12 20 21
R6 G2 G3 G11 R21
E13
E2 C5 C6 C13

R7 R8 R9 R19 R22

98

99

D5 D6
ISY R27
G19
R25 D3 25 V4
23

R23
29 L5 30
G15 24
VOUT
C15 V5

98 D4 26
27 28 R28
G20
R26
G17 G18

D7 D8

50

Figure 4.

–6– REV. B
 OP282/OP482
OP282 SPICE MACRO MODEL *
* Node assignments * COMMON-MODE GAIN NETWORK
* noninverting input WITH ZERO AT 11 KHZ
* inverting input *
* positive supply R21 20 21 1E6
* negative supply R22 21 98 1
* output C14 20 21 14.38E-12
* E13 98 20 3 24 31.62
.SUBCKT OP282 1 2 99 50 30 *
* * POLE AT 15 MHZ
* INPUT STAGE & POLE AT 15 MHZ *
* R23 23 98 1E6
R1 1 3 5E11 C15 23 98 10.6E-15
R2 2 3 5E11 G15 98 23 19 24 1E-6
R3 5 50 3871.3 *
R4 6 50 3871.3 * OUTPUT STAGE
CIN 1 2 5E-12 *
C2 5 6 1.37E-12 R25 24 99 5E6
I1 99 4 0.1E-3 R26 24 50 5E6
IOS 1 2 5E-13 ISY 99 50 107E-6
EOS 7 1 POLY(1) 21 24 200E-6 1 R27 29 99 700
J1 5 2 4 JX R28 29 50 700
J2 6 7 4 JX L5 29 30 1E-8
* G17 27 50 23 29 1.43E-3
EREF 98 0 24 01 G18 28 50 29 23 1.43E-3
* G19 29 99 99 23 1.43E-3
* GAIN STAGE & POLE AT 124 HZ G20 50 29 23 50 1.43E-3
* V4 25 29 2.8
R5 9 98 1.16E8 V5 29 26 3.5
C3 9 98 1.11E-11 D3 23 25 DX
G1 98 9 56 2.58E-4 D4 26 23 DX
V2 99 8 1.2 D5 99 27 DX
V3 10 50 1.2 D6 99 28 DX
D1 9 8 DX D7 50 27 DY
D2 10 9 DX D8 50 28 DY
* *
* NEGATIVE ZERO AT 4 MHZ * MODELS USED
* *
R6 11 12 1E6 .MODEL JX PJF(BETA = 3.34E-4
R7 12 98 1 VTO = –2.000 IS = 3E-12)
C4 11 12 39.8E-15 .MODEL DX D(IS = 1E-15)
E2 11 98 9 24 1E6 .MODEL DY D(IS = 1E-15 BV = 50)
* .ENDS OP282
* POLE AT 15 MHZ
*
R8 13 98 1E6
C5 13 98 10.6E-15
G2 98 13 12 24 1E-6
*
* POLE AT 15 MHZ
*
R9 14 98 1E6
C6 14 98 10.6E-15
G3 98 14 13 24 1E-6
*
* POLE AT 15 MHZ
*
R19 19 98 1E6
C13 19 98 10.6E-15
G11 98 19 14 24 1E-6

REV. B –7–
OP282/OP482
80 0 35 70
TA = +25°C VS = ±15V AVCL = +1
VS = ±15V VS = ±15V
L 2kΩ
30 60 RL = NEGATIVE EDGE
RL= 10k
60 45 VIN = 100mV p-p

OPEN-LOOP GAIN – V/MV

OPEN-LOOP GAIN – dB

25 50

PHASE – Degrees

OVERSHOOT – %
40 90 AVCL = +1
20 40
POSITIVE EDGE

135 15 30
20

10 20
0 180
5 10

0
1k 10k 100k 1M 10M 100M –75 –50 –25 0 25 50 75 100 125 0 100 200 300 400 500
FREQUENCY – Hz LOAD CAPACITANCE – pF
TEMPERATURE – °C

Figure 5. Open-Loop Gain, Phase Figure 8. Open-Loop Gain (V/mV) Figure 11. Small Signal Overshoot
vs. Frequency vs. Load Capacitance

60 25 1000
TA = +25°C VS = ±15V
50 VS = ±15V – SR
AVCL= +100 VCM = 0
CLOSED-LOOP GAIN – dB

INPUT BIAS CURRENT – pA

20
40 VS= ±15V 100
SLEW RATE – V/µs

RL= 10k
30 L
15 CL= 50pF
AVCL = +10
20 10

10 10
AVCL = +1
+ SR
0 1.0
5
–10

–20 0.1
1k 10k 100k 1M 10M 100M –75 –50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
FREQUENCY – Hz TEMPERATURE –°C
TEMPERATURE – °C

Figure 6. Closed-Loop Gain vs. Figure 9. OP282/OP482 Slew Rate Figure 12. OP282 Input Bias Current
Frequency vs. Temperature vs. Temperature

60 50 80 1000
GAIN BANDWIDTH PRODUCT – MH Z

VS = ±15V VS = ±15V
Hz

VS = ±15V
RL = 10k 70 TA = +25°C TA = +25°C
INPUT BIAS CURRENT – pA
PHASE MARGIN – Degrees

VOLTAGE NOISE DENSITY – nV/

55 4.5 100
60

ØM GBW 50
50 4.0 10
40

30
45 3.5 1
20

10
40 3.0 0.1
0
–75 –50 –25 0 25 50 75 100 125 10 100 1k 10k –15 –10 –5 0 5 10 15
TEMPERATURE – °C FREQUENCY – Hz COMMON - MODE VOLTAGE – V

Figure 7. OP482 Phase Margin and Figure 10. Voltage Noise Density Figure 13. OP282 Input Bias Current
Gain Bandwidth Product vs. vs. Frequency vs. Common-Mode Voltage
Temperature

–8– REV. B
 OP282/OP482
1.15 20 600
TA = +25°C
RELATIVE SUPPLY CURRENT – ISY

15 TA = +25°C

OUTPUT VOLTAGE SWING – Volts

1.10 RL = 10k Ω 500 VS = ±15V
TA = +25°C 10
1.05 AVCL = 1000

IMPEDANCE – Ω
400
5

1.00 0 300

–5
0.95 200
–10
0.90 AVCL = 100 AVCL= +10
100
–15 AVCL= 1

0.85 –20 0
0 ±5 ±10 ±15 ±20 0 ±5 ±10 ±15 ±20 100 1k 10k 100k 1M
SUPPLY VOLTAGE – Volts SUPPLY VOLTAGE – Volts FREQUENCY – Hz

Figure 14. Relative Supply Current Figure 17. Output Voltage Swing Figure 20. OP482 Closed-Loop Out-
vs. Supply Voltage vs. Supply Voltage put Impedance vs. Frequency

1.20 16 100
VS = ±15V
ABSOLUTE OUTPUT VOLTAGE – Volts

∆V = 100mV
RELATIVE SUPPLY CURRENT – ISY

1.15 VSUP = ±15 14 TA = +25°C

80 + PSRR TA = +25°C
VS = ±15V
1.10 12
60
POSITIVE

PSRR – dB
1.05 10
SWING – PSRR
1.00 8 40

NEGATIVE
0.95 6
SWING 20
0.90 4
0
0.85 2

0.80 0 –20
–75 –50 –25 0 25 50 75 100 125 100 1k 10k 100 1k 10k 100k 1M
TEMPERATURE – °C LOAD RESISTANCE – Ω FREQUENCY – Hz

Figure 15. Relative Supply Current Figure 18. Maximum Output Voltage Figure 21. OP282 Power Supply
vs. Temperature vs. Load Resistance Rejection Ratio (PSRR) vs. Frequency

20 30 100
TA = +25°C
VS = ±15V
MAXIMUM OUTPUT SWING – Volts

VS = ±15V
SHORT CIRCUIT CURRENT – mA

25 80 VS = ±15V
SINK AVCL = +1 VCM = 100mV
15 RL = 10k Ω
TA = +25°C
20 60
CMRR – dB

10 15 40

SOURCE 10 20
5
5 0

0 –20
–75 –50 –25 0 25 50 75 100 125 1k 10k 100k 1M 100 1k 10k 100k 1M
TEMPERATURE – °C FREQUENCY – Hz FREQUENCY – Hz

Figure 16. OP282/OP482 Short Figure 19. Maximum Output Swing Figure 22. OP282 Common-Mode
Circuit Current vs. Temperature vs. Frequency Rejection Ratio (CMRR) vs. Frequency

REV. B –9–
OP282/OP482
280 320 700

VS = ±15V 280 VS = ±15V

240 600
TA= +25°C -40°C ≤ TA ≤ +125°C
315 × OP282 240 300 × OP482
200 (630 OP AMPS ) 500 1200 OP AMPS
200

UNITS
400
UNITS

UNITS
160
160
120 300
120
80 200
80

40 40 100

0 0 0
-2000 -1600 -1200 -800 -400 0 400 800 1200 1600 2000 0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32
VOS – µV TCVOS – µV/°C TCVOS – µV/°C

Figure 23. VOS Distribution "P" Figure 25. OP282 TCVOS (µ V/°C) Figure 27. OP482 TCVOS Distribution
Package Distribution "P" Package "Z" Package

280 320 700

VS = ±15V
280 VS = ±15V
240 TA = +25°C 600
320 × OP282 -40°C ≤ TA ≤ +85°C
(640 OP AMPS) 240 300 × OP482
200 500
1200 OP AMPS
200
UNITS

160 400
UNITS

UNITS
160
120 300
120
80 200
80

40 100
40

0 0 0
–2000 –1600 –1200 –800 –400 0 400 800 1200 1600 2000 0 4 8 12 16 20 24 28 32 0 4 8 12 16 20 24 28 32
VOS – µV TCVOS – µV/°C TCVOS – µV/°C

Figure 24. VOS Distribution "Z" Figure 26. OP282 TCVOS (µ V/°C) Figure 28. TCVOS Distribution "P"
Package Distribution "Z" Package Package

700
700
TA = +25°C TA = +25°C
VS = ±15V 600 VS = ±15V
600
300 3 OP482 300 3 OP482
1200 OP AMPS 500 1200 OP AMPS
500

400 400
UNITS
UNITS

300 300

200 200

100 100

0 0
–2000 –1600 –1200 –800 –400 0 400 800 1200 1600 2000 –2000 –1600 –1200 –800 –400 0 400 800 1200 1600 2000

V OS – µV VOS – µV

Figure 29. OP482 VOS Distribution “Z” Figure 30. OP482 VOS Distribution “P”
Package Package

–10– REV. B
 OP282/OP482
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

8-Lead Narrow-Body SOIC 8-Lead Epoxy DIP

(S Suffix) (P Suffix)

14-Lead Narrow-Body SOIC

14-Lead Epoxy DIP
(S Suffix)
(P Suffix)

20-Position Chip Carrier

(RC Suffix)

REV. B –11–
–12–
REV. B
PRINTED IN U.S.A. C1597–24–11/91